powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code
Remove duplicated code in MPC8xxx XES boards and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> CC: Peter Tyser <ptyser@xes-inc.com>
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@ -34,57 +34,16 @@
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#ifdef CONFIG_PCI1
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static struct pci_controller pci1_hose;
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#endif
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif
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#ifdef CONFIG_PCIE2
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static struct pci_controller pcie2_hose;
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#endif
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#ifdef CONFIG_PCIE3
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static struct pci_controller pcie3_hose;
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#endif
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/*
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* 85xx and 86xx share naming conventions, but different layout.
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* Correlate names to CPU-specific values to share common
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* PCI code.
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*/
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#if defined(CONFIG_MPC85xx)
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#define MPC8xxx_DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
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#define MPC8xxx_DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2
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#define MPC8xxx_DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3
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#define MPC8xxx_PORDEVSR_IO_SEL MPC85xx_PORDEVSR_IO_SEL
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#define MPC8xxx_PORDEVSR_IO_SEL_SHIFT MPC85xx_PORDEVSR_IO_SEL_SHIFT
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#define MPC8xxx_PORBMSR_HA MPC85xx_PORBMSR_HA
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#define MPC8xxx_PORBMSR_HA_SHIFT MPC85xx_PORBMSR_HA_SHIFT
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#elif defined(CONFIG_MPC86xx)
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#define MPC8xxx_DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIEX1
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#define MPC8xxx_DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIEX2
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#define MPC8xxx_DEVDISR_PCIE3 0 /* 8641 doesn't have PCIe3 */
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#define MPC8xxx_PORDEVSR_IO_SEL MPC8641_PORDEVSR_IO_SEL
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#define MPC8xxx_PORDEVSR_IO_SEL_SHIFT MPC8641_PORDEVSR_IO_SEL_SHIFT
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#define MPC8xxx_PORBMSR_HA MPC8641_PORBMSR_HA
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#define MPC8xxx_PORBMSR_HA_SHIFT MPC8641_PORBMSR_HA_SHIFT
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#endif
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void pci_init_board(void)
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{
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struct fsl_pci_info pci_info[3];
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int first_free_busno = 0;
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int num = 0;
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int pcie_ep;
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__maybe_unused int pcie_configured;
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#if defined(CONFIG_MPC85xx)
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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#elif defined(CONFIG_MPC86xx)
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immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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#endif
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u32 devdisr = in_be32(&gur->devdisr);
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#ifdef CONFIG_PCI1
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u32 pordevsr = in_be32(&gur->pordevsr);
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int pcie_ep;
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struct fsl_pci_info pci_info;
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 devdisr = in_be32(&gur->devdisr);
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uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
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uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
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uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
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@ -92,8 +51,13 @@ void pci_init_board(void)
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uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
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SET_STD_PCI_INFO(pci_info[num], 1);
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pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
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SET_STD_PCI_INFO(pci_info, 1);
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set_next_law(pci_info.mem_phys,
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law_size_bits(pci_info.mem_size), pci_info.law);
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set_next_law(pci_info.io_phys,
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law_size_bits(pci_info.io_size), pci_info.law);
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pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs);
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printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n",
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pci_32 ? 32 : 64,
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pcix ? "PCIX" : "PCI",
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@ -102,66 +66,18 @@ void pci_init_board(void)
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pcie_ep ? "agent" : "host",
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pci_arb ? "arbiter" : "external-arbiter");
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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first_free_busno = fsl_pci_init_port(&pci_info,
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&pci1_hose, first_free_busno);
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} else {
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printf("PCI1: disabled\n");
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}
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#elif defined CONFIG_MPC8548
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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/* PCI1 not present on MPC8572 */
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
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#endif
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#ifdef CONFIG_PCIE1
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pcie_configured = is_serdes_configured(PCIE1);
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if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
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SET_STD_PCIE_INFO(pci_info[num], 1);
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pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
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printf("PCIE1: connected as %s\n",
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pcie_ep ? "Endpoint" : "Root Complex");
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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} else {
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printf("PCIE1: disabled\n");
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}
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#else
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setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1);
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#endif /* CONFIG_PCIE1 */
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#ifdef CONFIG_PCIE2
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pcie_configured = is_serdes_configured(PCIE2);
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if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
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SET_STD_PCIE_INFO(pci_info[num], 2);
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pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
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printf("PCIE2: connected as %s\n",
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pcie_ep ? "Endpoint" : "Root Complex");
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie2_hose, first_free_busno);
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} else {
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printf("PCIE2: disabled\n");
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}
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#else
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setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2);
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#endif /* CONFIG_PCIE2 */
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#ifdef CONFIG_PCIE3
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pcie_configured = is_serdes_configured(PCIE3);
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if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
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SET_STD_PCIE_INFO(pci_info[num], 3);
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pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
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printf("PCIE3: connected as %s\n",
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pcie_ep ? "Endpoint" : "Root Complex");
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie3_hose, first_free_busno);
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} else {
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printf("PCIE3: disabled\n");
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}
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#else
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setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3);
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#endif /* CONFIG_PCIE3 */
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fsl_pcie_init_board(first_free_busno);
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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@ -39,14 +39,6 @@ struct law_entry law_table[] = {
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/* NAND LAW covers 2 NAND flashes */
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SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_512K, LAW_TRGT_IF_LBC),
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#endif
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#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
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SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
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SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
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#endif
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#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
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SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
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SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
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#endif
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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@ -38,14 +38,6 @@ struct law_entry law_table[] = {
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/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
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SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
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SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
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#if CONFIG_SYS_PCI1_MEM_PHYS
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SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1),
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SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_1),
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#endif
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#if CONFIG_SYS_PCI2_MEM_PHYS
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SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),
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SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2),
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#endif
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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@ -37,18 +37,6 @@
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struct law_entry law_table[] = {
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SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
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SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
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#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
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SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
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SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
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#endif
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#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
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SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
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SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
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#endif
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#ifdef CONFIG_SYS_PCIE3_MEM_PHYS
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SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3),
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SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3),
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#endif
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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@ -37,18 +37,6 @@
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struct law_entry law_table[] = {
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SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
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SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
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#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
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SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
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SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
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#endif
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#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
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SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
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SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
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#endif
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#ifdef CONFIG_SYS_PCIE3_MEM_PHYS
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SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3),
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SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3),
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#endif
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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