ARM64: zynqmp: Add support for zc1751 with DC cards
Support ZynqMP zc1751 with DC cards. Signed-off-by: Michal Simek <michal.simek@xilinx.com>utp
Michal Simek
parent
da81db61d5
commit
6c0c958de8
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@ -83,7 +83,10 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
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dtb-$(CONFIG_ARCH_ZYNQMP) += \
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zynqmp-ep108.dtb \
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zynqmp-zcu102.dtb \
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zynqmp-zcu102-revB.dtb
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zynqmp-zcu102-revB.dtb \
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zynqmp-zc1751-xm015-dc1.dtb \
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zynqmp-zc1751-xm016-dc2.dtb \
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zynqmp-zc1751-xm019-dc5.dtb
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dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
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dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb
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dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
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@ -0,0 +1,211 @@
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/*
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* dts file for Xilinx ZynqMP zc1751-xm015-dc1
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*
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* (C) Copyright 2015, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk.dtsi"
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/ {
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model = "ZynqMP zc1751-xm015-dc1 RevA";
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compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
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aliases {
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ethernet0 = &gem3;
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gpio0 = &gpio;
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i2c0 = &i2c1;
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mmc0 = &sdhci0;
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mmc1 = &sdhci1;
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rtc0 = &rtc;
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serial0 = &uart0;
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spi0 = &qspi;
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usb0 = &usb0;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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};
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};
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/* fpd_dma clk 667MHz, lpd_dma 500MHz */
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&fpd_dma_chan1 {
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status = "okay";
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xlnx,include-sg; /* for testing purpose */
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xlnx,overfetch; /* for testing purpose */
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xlnx,ratectrl = <0>; /* for testing purpose */
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xlnx,src-issue = <31>;
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};
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&fpd_dma_chan2 {
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status = "okay";
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xlnx,ratectrl = <100>; /* for testing purpose */
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xlnx,src-issue = <4>; /* for testing purpose */
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};
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&fpd_dma_chan3 {
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status = "okay";
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};
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&fpd_dma_chan4 {
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status = "okay";
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xlnx,include-sg; /* for testing purpose */
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};
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&fpd_dma_chan5 {
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status = "okay";
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};
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&fpd_dma_chan6 {
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status = "okay";
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xlnx,include-sg; /* for testing purpose */
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};
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&fpd_dma_chan7 {
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status = "okay";
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};
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&fpd_dma_chan8 {
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status = "okay";
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xlnx,include-sg; /* for testing purpose */
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};
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&gem3 {
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status = "okay";
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local-mac-address = [00 0a 35 00 02 90];
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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phy0: phy@0 {
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reg = <0>;
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};
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};
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&gpio {
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status = "okay";
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};
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&gpu {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <400000>;
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eeprom@55 {
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compatible = "at,24c64"; /* 24AA64 */
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reg = <0x55>;
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};
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};
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&qspi {
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status = "okay";
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flash@0 {
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compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <108000000>; /* Based on DC1 spec */
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partition@qspi-fsbl-uboot { /* for testing purpose */
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label = "qspi-fsbl-uboot";
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reg = <0x0 0x100000>;
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};
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partition@qspi-linux { /* for testing purpose */
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label = "qspi-linux";
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reg = <0x100000 0x500000>;
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};
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partition@qspi-device-tree { /* for testing purpose */
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label = "qspi-device-tree";
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reg = <0x600000 0x20000>;
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};
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partition@qspi-rootfs { /* for testing purpose */
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label = "qspi-rootfs";
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reg = <0x620000 0x5E0000>;
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};
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};
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};
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&rtc {
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status = "okay";
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};
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&sata {
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status = "okay";
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/* SATA phy OOB timing settings */
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ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
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ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
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ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
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ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
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ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
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ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
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ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
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ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
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};
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/* eMMC */
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&sdhci0 {
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status = "okay";
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bus-width = <8>;
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};
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/* SD1 with level shifter */
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&sdhci1 {
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status = "okay";
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no-1-8-v; /* for 1.0 silicon */
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};
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&uart0 {
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status = "okay";
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};
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/* ULPI SMSC USB3320 */
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&usb0 {
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status = "okay";
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dr_mode = "host";
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};
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&xilinx_drm {
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status = "okay";
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};
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&xlnx_dp {
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status = "okay";
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};
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&xlnx_dp_sub {
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status = "okay";
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xlnx,vid-clk-pl;
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};
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&xlnx_dp_snd_pcm0 {
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status = "okay";
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};
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&xlnx_dp_snd_pcm1 {
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status = "okay";
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};
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&xlnx_dp_snd_card {
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status = "okay";
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};
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&xlnx_dp_snd_codec0 {
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status = "okay";
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};
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&xlnx_dpdma {
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status = "okay";
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};
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@ -0,0 +1,236 @@
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/*
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* dts file for Xilinx ZynqMP zc1751-xm016-dc2
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*
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* (C) Copyright 2015, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk.dtsi"
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/ {
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model = "ZynqMP zc1751-xm016-dc2 RevA";
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compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
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aliases {
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can0 = &can0;
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can1 = &can1;
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ethernet0 = &gem2;
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gpio0 = &gpio;
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i2c0 = &i2c0;
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rtc0 = &rtc;
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serial0 = &uart0;
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serial1 = &uart1;
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spi0 = &spi0;
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spi1 = &spi1;
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usb0 = &usb1;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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};
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};
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&can0 {
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status = "okay";
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};
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&can1 {
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status = "okay";
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};
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/* fpd_dma clk 667MHz, lpd_dma 500MHz */
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&fpd_dma_chan1 {
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status = "okay";
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xlnx,include-sg; /* for testing purpose */
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xlnx,overfetch; /* for testing purpose */
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xlnx,ratectrl = <0>; /* for testing purpose */
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xlnx,src-issue = <31>;
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};
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&fpd_dma_chan2 {
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status = "okay";
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xlnx,ratectrl = <100>; /* for testing purpose */
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xlnx,src-issue = <4>; /* for testing purpose */
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};
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&fpd_dma_chan3 {
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status = "okay";
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};
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&fpd_dma_chan4 {
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status = "okay";
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xlnx,include-sg; /* for testing purpose */
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};
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&fpd_dma_chan5 {
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status = "okay";
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};
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&fpd_dma_chan6 {
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status = "okay";
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xlnx,include-sg; /* for testing purpose */
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};
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&fpd_dma_chan7 {
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status = "okay";
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};
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&fpd_dma_chan8 {
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status = "okay";
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xlnx,include-sg; /* for testing purpose */
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};
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&gem2 {
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status = "okay";
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local-mac-address = [00 0a 35 00 02 90];
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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phy0: phy@5 {
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reg = <5>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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};
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};
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&gpio {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <400000>;
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tca6416_u26: gpio@20 {
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compatible = "ti,tca6416";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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/* IRQ not connected */
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};
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rtc@68 {
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compatible = "dallas,ds1339";
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reg = <0x68>;
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};
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};
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&nand0 {
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status = "okay";
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arasan,has-mdma;
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num-cs = <2>;
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partition@0 { /* for testing purpose */
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label = "nand-fsbl-uboot";
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reg = <0x0 0x0 0x400000>;
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};
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partition@1 { /* for testing purpose */
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label = "nand-linux";
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reg = <0x0 0x400000 0x1400000>;
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};
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partition@2 { /* for testing purpose */
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label = "nand-device-tree";
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reg = <0x0 0x1800000 0x400000>;
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};
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partition@3 { /* for testing purpose */
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label = "nand-rootfs";
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reg = <0x0 0x1C00000 0x1400000>;
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};
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partition@4 { /* for testing purpose */
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label = "nand-bitstream";
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reg = <0x0 0x3000000 0x400000>;
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};
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partition@5 { /* for testing purpose */
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label = "nand-misc";
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reg = <0x0 0x3400000 0xFCC00000>;
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};
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partition@6 { /* for testing purpose */
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label = "nand1-fsbl-uboot";
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reg = <0x1 0x0 0x400000>;
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};
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partition@7 { /* for testing purpose */
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label = "nand1-linux";
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reg = <0x1 0x400000 0x1400000>;
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};
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partition@8 { /* for testing purpose */
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label = "nand1-device-tree";
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reg = <0x1 0x1800000 0x400000>;
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};
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partition@9 { /* for testing purpose */
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label = "nand1-rootfs";
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reg = <0x1 0x1C00000 0x1400000>;
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};
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partition@10 { /* for testing purpose */
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label = "nand1-bitstream";
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reg = <0x1 0x3000000 0x400000>;
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};
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partition@11 { /* for testing purpose */
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label = "nand1-misc";
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reg = <0x1 0x3400000 0xFCC00000>;
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};
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};
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&rtc {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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num-cs = <1>;
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spi0_flash0: spi0_flash0@0 {
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compatible = "m25p80";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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reg = <0>;
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spi0_flash0@00000000 {
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label = "spi0_flash0";
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reg = <0x0 0x100000>;
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};
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};
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};
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&spi1 {
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status = "okay";
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num-cs = <1>;
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spi1_flash0: spi1_flash0@0 {
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compatible = "mtd_dataflash";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <20000000>;
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reg = <0>;
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spi1_flash0@00000000 {
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label = "spi1_flash0";
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reg = <0x0 0x84000>;
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};
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};
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};
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/* ULPI SMSC USB3320 */
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&usb1 {
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status = "okay";
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dr_mode = "host";
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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@ -0,0 +1,121 @@
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/*
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* dts file for Xilinx ZynqMP zc1751-xm019-dc5
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*
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* (C) Copyright 2015, Xilinx, Inc.
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*
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* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk.dtsi"
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/ {
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model = "ZynqMP zc1751-xm019-dc5 RevA";
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compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
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aliases {
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ethernet0 = &gem1;
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gpio0 = &gpio;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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mmc0 = &sdhci0;
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serial0 = &uart0;
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serial1 = &uart1;
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};
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chosen {
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bootargs = "earlycon=cdns,mmio,0xff000000,115200n8";
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stdout-path = "serial0:115200n8";
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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};
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};
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/* fpd_dma clk 667MHz, lpd_dma 500MHz */
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&fpd_dma_chan1 {
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status = "okay";
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xlnx,include-sg; /* for testing purpose */
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xlnx,overfetch; /* for testing purpose */
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xlnx,ratectrl = <0>; /* for testing purpose */
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xlnx,src-issue = <31>;
|
||||
};
|
||||
|
||||
&fpd_dma_chan2 {
|
||||
status = "okay";
|
||||
xlnx,ratectrl = <100>; /* for testing purpose */
|
||||
xlnx,src-issue = <4>; /* for testing purpose */
|
||||
};
|
||||
|
||||
&fpd_dma_chan3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan4 {
|
||||
status = "okay";
|
||||
xlnx,include-sg; /* for testing purpose */
|
||||
};
|
||||
|
||||
&fpd_dma_chan5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan6 {
|
||||
status = "okay";
|
||||
xlnx,include-sg; /* for testing purpose */
|
||||
};
|
||||
|
||||
&fpd_dma_chan7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan8 {
|
||||
status = "okay";
|
||||
xlnx,include-sg; /* for testing purpose */
|
||||
};
|
||||
|
||||
&gem1 {
|
||||
status = "okay";
|
||||
local-mac-address = [00 0a 35 00 02 90];
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* FIXME: Add device */
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* FIXME: Add device */
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1"
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_ZYNQMP_USB=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SYS_PROMPT="ZynqMP> "
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_OF_EMBED=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_ZYNQ_SDHCI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm016_dc2"
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_ZYNQMP_USB=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SYS_PROMPT="ZynqMP> "
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_OF_EMBED=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_NAND_ARASAN=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm019_dc5"
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SYS_PROMPT="ZynqMP> "
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_OF_EMBED=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_ZYNQ_SDHCI=y
|
||||
CONFIG_DM_ETH=y
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* Configuration for Xilinx ZynqMP zc1751 XM015 DC1
|
||||
*
|
||||
* (C) Copyright 2015 Xilinx, Inc.
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H
|
||||
#define __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H
|
||||
|
||||
#define CONFIG_ZYNQ_SDHCI0
|
||||
#define CONFIG_ZYNQ_SDHCI1
|
||||
#define CONFIG_ZYNQ_I2C1
|
||||
#define CONFIG_SYS_I2C_ZYNQ
|
||||
#define CONFIG_AHCI
|
||||
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
|
||||
|
||||
#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm015 dc1"
|
||||
|
||||
#define CONFIG_KERNEL_FDT_OFST_SIZE \
|
||||
"kernel_offset=0x400000\0" \
|
||||
"fdt_offset=0x2400000\0" \
|
||||
"kernel_size=0x2000000\0" \
|
||||
"fdt_size=0x80000\0" \
|
||||
"board=zc1751-dc1\0"
|
||||
|
||||
#include <configs/xilinx_zynqmp.h>
|
||||
|
||||
#endif /* __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H */
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* Configuration for Xilinx ZynqMP zc1751 XM016 DC2
|
||||
*
|
||||
* (C) Copyright 2015 Xilinx, Inc.
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H
|
||||
#define __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H
|
||||
|
||||
#define CONFIG_ZYNQ_I2C0
|
||||
#define CONFIG_SYS_I2C_ZYNQ
|
||||
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB1_XHCI_BASEADDR}
|
||||
|
||||
#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm016 dc2"
|
||||
|
||||
#define CONFIG_KERNEL_FDT_OFST_SIZE \
|
||||
"kernel_offset=0x400000\0" \
|
||||
"fdt_offset=0x2400000\0" \
|
||||
"kernel_size=0x2000000\0" \
|
||||
"fdt_size=0x80000\0" \
|
||||
"board=zc1751-dc2\0"
|
||||
|
||||
#include <configs/xilinx_zynqmp.h>
|
||||
|
||||
#endif /* __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* Configuration for Xilinx ZynqMP zc1751 XM019 DC5
|
||||
*
|
||||
* (C) Copyright 2015 Xilinx, Inc.
|
||||
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H
|
||||
#define __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H
|
||||
|
||||
#define CONFIG_ZYNQ_SDHCI0
|
||||
#define CONFIG_ZYNQ_I2C0
|
||||
#define CONFIG_ZYNQ_I2C1
|
||||
#define CONFIG_SYS_I2C_ZYNQ
|
||||
|
||||
#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm019 dc5"
|
||||
|
||||
#define CONFIG_KERNEL_FDT_OFST_SIZE \
|
||||
"kernel_offset=0x400000\0" \
|
||||
"fdt_offset=0x2400000\0" \
|
||||
"kernel_size=0x2000000\0" \
|
||||
"fdt_size=0x80000\0" \
|
||||
"board=zc1751-dc5\0"
|
||||
|
||||
#include <configs/xilinx_zynqmp.h>
|
||||
|
||||
#endif /* __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H */
|
||||
Loading…
Reference in New Issue