dm: pch: Add get_io_base op
On some newer chipset (eg: BayTrail), there is an IO base address register on the PCH device which configures the base address of a memory-mapped I/O controller. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>utp
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79d4eb627c
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@ -44,6 +44,17 @@ int pch_get_gpio_base(struct udevice *dev, u32 *gbasep)
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return ops->get_gpio_base(dev, gbasep);
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return ops->get_gpio_base(dev, gbasep);
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}
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}
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int pch_get_io_base(struct udevice *dev, u32 *iobasep)
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{
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struct pch_ops *ops = pch_get_ops(dev);
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*iobasep = 0;
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if (!ops->get_io_base)
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return -ENOSYS;
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return ops->get_io_base(dev, iobasep);
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}
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static int pch_uclass_post_bind(struct udevice *bus)
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static int pch_uclass_post_bind(struct udevice *bus)
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{
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{
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/*
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/*
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@ -41,6 +41,15 @@ struct pch_ops {
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* @return 0 if OK, -ve on error (e.g. there is no GPIO base)
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* @return 0 if OK, -ve on error (e.g. there is no GPIO base)
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*/
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*/
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int (*get_gpio_base)(struct udevice *dev, u32 *gbasep);
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int (*get_gpio_base)(struct udevice *dev, u32 *gbasep);
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/**
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* get_io_base() - get the address of IO base
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*
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* @dev: PCH device to check
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* @iobasep: Returns address of IO base if available, else 0
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* @return 0 if OK, -ve on error (e.g. there is no IO base)
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*/
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int (*get_io_base)(struct udevice *dev, u32 *iobasep);
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};
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};
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#define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops)
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#define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops)
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@ -73,4 +82,13 @@ int pch_set_spi_protect(struct udevice *dev, bool protect);
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*/
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*/
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int pch_get_gpio_base(struct udevice *dev, u32 *gbasep);
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int pch_get_gpio_base(struct udevice *dev, u32 *gbasep);
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/**
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* pch_get_io_base() - get the address of IO base
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*
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* @dev: PCH device to check
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* @iobasep: Returns address of IO base if available, else 0
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* @return 0 if OK, -ve on error (e.g. there is no IO base)
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*/
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int pch_get_io_base(struct udevice *dev, u32 *iobasep);
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#endif
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#endif
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