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Fix some typos 

This patch fixes three typos.
The first is a repetition of CONFIG_CMD_BSP.
The second makes the #endif comment match its #if.
The third is a spelling error.

Signed-off-by: Adrian Filipi <adrian.filipi@eurotech.com>
utp
Adrian Filipi 2008-05-06 16:46:37 -04:00 committed by Wolfgang Denk
parent e419e12d04
commit 8fbc985bda
3 changed files with 2 additions and 3 deletions
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1
README
View File

@ -623,7 +623,6 @@ The following options need to be configured:
CONFIG_CMD_SPI * SPI serial bus support CONFIG_CMD_SPI * SPI serial bus support
CONFIG_CMD_USB * USB support CONFIG_CMD_USB * USB support
CONFIG_CMD_VFD * VFD support (TRAB) CONFIG_CMD_VFD * VFD support (TRAB)
CONFIG_CMD_BSP * Board SPecific functions
CONFIG_CMD_CDP * Cisco Discover Protocol support CONFIG_CMD_CDP * Cisco Discover Protocol support
CONFIG_CMD_FSL * Microblaze FSL support CONFIG_CMD_FSL * Microblaze FSL support

2
cpu/arm920t/s3c24x0/usb.c
View File

@ -69,4 +69,4 @@ int usb_cpu_init_fail (void)
} }
# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */ # endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */ #endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) */

2
doc/README.nand-boot-ppc440
View File

@ -9,7 +9,7 @@ The PPC440EP(x)/GR(x) cpu's can boot directly from NAND FLASH,
completely without NOR FLASH. This can be done by using the NAND completely without NOR FLASH. This can be done by using the NAND
boot feature of the 440 NAND flash controller (NDFC). boot feature of the 440 NAND flash controller (NDFC).
Here a short desciption of the different boot stages: Here a short description of the different boot stages:
a) IPL (Initial Program Loader, integrated inside CPU) a) IPL (Initial Program Loader, integrated inside CPU)
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