tegra: video: Move LCD driver to use the DM PWM driver
Use the driver-model PWM driver in preference to the old code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>utp
parent
41fa035ce1
commit
91c08afe66
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@ -104,6 +104,10 @@
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};
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};
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};
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};
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pwm: pwm@7000a000 {
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status = "okay";
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};
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lcd_panel: panel {
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lcd_panel: panel {
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clock = <25175000>;
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clock = <25175000>;
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xres = <640>;
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xres = <640>;
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@ -84,6 +84,10 @@
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};
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};
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};
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};
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pwm: pwm@7000a000 {
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status = "okay";
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};
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lcd_panel: panel {
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lcd_panel: panel {
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clock = <42430000>;
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clock = <42430000>;
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xres = <1024>;
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xres = <1024>;
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@ -40,6 +40,10 @@
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status = "okay";
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status = "okay";
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};
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};
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pwm: pwm@7000a000 {
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status = "okay";
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};
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lcd_panel: panel {
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lcd_panel: panel {
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clock = <61715000>;
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clock = <61715000>;
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xres = <1366>;
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xres = <1366>;
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@ -65,6 +65,10 @@
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};
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};
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};
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};
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pwm: pwm@7000a000 {
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status = "okay";
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};
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lcd_panel: panel {
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lcd_panel: panel {
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/* PAZ00 has 1024x600 */
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/* PAZ00 has 1024x600 */
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clock = <54030000>;
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clock = <54030000>;
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@ -200,6 +200,10 @@
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};
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};
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};
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};
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pwm: pwm@7000a000 {
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status = "okay";
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};
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lcd_panel: panel {
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lcd_panel: panel {
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/* Seaboard has 1366x768 */
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/* Seaboard has 1366x768 */
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clock = <70600000>;
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clock = <70600000>;
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@ -52,6 +52,10 @@
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status = "disabled";
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status = "disabled";
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};
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};
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pwm: pwm@7000a000 {
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status = "okay";
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};
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lcd_panel: panel {
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lcd_panel: panel {
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clock = <33260000>;
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clock = <33260000>;
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xres = <800>;
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xres = <800>;
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@ -65,6 +65,10 @@
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};
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};
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};
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};
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pwm: pwm@7000a000 {
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status = "okay";
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};
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lcd_panel: panel {
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lcd_panel: panel {
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clock = <72072000>;
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clock = <72072000>;
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xres = <1366>;
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xres = <1366>;
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@ -9,6 +9,7 @@ config TEGRA_COMMON
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select DM_KEYBOARD
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select DM_KEYBOARD
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select DM_PCI
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select DM_PCI
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select DM_PCI_COMPAT
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select DM_PCI_COMPAT
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select DM_PWM
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select DM_SERIAL
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select DM_SERIAL
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select DM_SPI
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select DM_SPI
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select DM_SPI_FLASH
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select DM_SPI_FLASH
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@ -20,6 +20,7 @@ config PWM_ROCKCHIP
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config PWM_TEGRA
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config PWM_TEGRA
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bool "Enable support for the Tegra PWM"
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bool "Enable support for the Tegra PWM"
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depends on DM_PWM
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help
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help
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This PWM is found on Tegra 20 and other Nvidia SoCs. It supports
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This PWM is found on Tegra 20 and other Nvidia SoCs. It supports
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four channels with a programmable period and duty cycle. Only a
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four channels with a programmable period and duty cycle. Only a
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@ -6,6 +6,7 @@
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#include <common.h>
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#include <common.h>
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#include <dm.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <fdtdec.h>
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#include <pwm.h>
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#include <video.h>
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#include <video.h>
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#include <asm/system.h>
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#include <asm/system.h>
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#include <asm/gpio.h>
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#include <asm/gpio.h>
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@ -68,6 +69,7 @@ struct tegra_lcd_priv {
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unsigned pixel_clock; /* Pixel clock in Hz */
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unsigned pixel_clock; /* Pixel clock in Hz */
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uint horiz_timing[FDT_LCD_TIMING_COUNT]; /* Horizontal timing */
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uint horiz_timing[FDT_LCD_TIMING_COUNT]; /* Horizontal timing */
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uint vert_timing[FDT_LCD_TIMING_COUNT]; /* Vertical timing */
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uint vert_timing[FDT_LCD_TIMING_COUNT]; /* Vertical timing */
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struct udevice *pwm;
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int pwm_channel; /* PWM channel to use for backlight */
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int pwm_channel; /* PWM channel to use for backlight */
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enum lcd_cache_t cache_type;
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enum lcd_cache_t cache_type;
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@ -400,7 +402,8 @@ static int handle_stage(const void *blob, struct tegra_lcd_priv *priv)
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pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
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pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
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pinmux_tristate_disable(PMUX_PINGRP_GPU);
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pinmux_tristate_disable(PMUX_PINGRP_GPU);
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pwm_enable(priv->pwm_channel, 32768, 0xdf, 1);
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pwm_set_config(priv->pwm, priv->pwm_channel, 0xdf, 0xff);
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pwm_set_enable(priv->pwm, priv->pwm_channel, true);
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break;
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break;
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case STAGE_BACKLIGHT_EN:
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case STAGE_BACKLIGHT_EN:
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if (dm_gpio_is_valid(&priv->backlight_en))
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if (dm_gpio_is_valid(&priv->backlight_en))
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@ -504,12 +507,14 @@ static int tegra_lcd_probe(struct udevice *dev)
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static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
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static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
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{
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{
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struct tegra_lcd_priv *priv = dev_get_priv(dev);
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struct tegra_lcd_priv *priv = dev_get_priv(dev);
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struct fdtdec_phandle_args args;
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const void *blob = gd->fdt_blob;
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const void *blob = gd->fdt_blob;
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int node = dev->of_offset;
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int node = dev->of_offset;
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int front, back, ref;
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int front, back, ref;
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int panel_node;
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int panel_node;
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int rgb;
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int rgb;
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int bpp, bit;
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int bpp, bit;
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int ret;
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priv->disp = (struct disp_ctlr *)dev_get_addr(dev);
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priv->disp = (struct disp_ctlr *)dev_get_addr(dev);
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if (!priv->disp) {
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if (!priv->disp) {
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@ -575,12 +580,19 @@ static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
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return -EINVAL;
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return -EINVAL;
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}
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}
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priv->pwm_channel = pwm_request(blob, panel_node, "nvidia,pwm");
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if (fdtdec_parse_phandle_with_args(blob, panel_node, "nvidia,pwm",
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if (priv->pwm_channel < 0) {
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"#pwm-cells", 0, 0, &args)) {
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debug("%s: Unable to request PWM channel\n", __func__);
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debug("%s: Unable to decode PWM\n", __func__);
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return -EINVAL;
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return -EINVAL;
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}
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}
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ret = uclass_get_device_by_of_offset(UCLASS_PWM, args.node, &priv->pwm);
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if (ret) {
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debug("%s: Unable to find PWM\n", __func__);
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return -EINVAL;
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}
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priv->pwm_channel = args.args[0];
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priv->cache_type = fdtdec_get_int(blob, panel_node, "nvidia,cache-type",
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priv->cache_type = fdtdec_get_int(blob, panel_node, "nvidia,cache-type",
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FDT_LCD_CACHE_WRITE_BACK_FLUSH);
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FDT_LCD_CACHE_WRITE_BACK_FLUSH);
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