improve readability of DCD by using defines and comments
Martin T. H. Sandsmark
parent
231ed29fcb
commit
cd0e6f0b2f
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@ -15,6 +15,7 @@
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#define CCM_CCGR4 0x020C4078
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#define CCM_CCGR5 0x020C407c
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#define CCM_CCGR6 0x020C4080
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#define CCM_CBCMR 0x020c4018
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#define PMU_MISC2 0x020C8170
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@ -468,6 +468,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
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#endif /* CONFIG_SPL_BUILD */
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#define MX6_MMDC_MDSCR_CON_REQ 0x00008000
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#define MX6_MMDC_P0_MDCTL 0x021b0000
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#define MX6_MMDC_P0_MDPDC 0x021b0004
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#define MX6_MMDC_P0_MDOTC 0x021b0008
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@ -42,4 +42,15 @@
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#define MX6_IOM_DRAM_SDWE_B 0x020e0354
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#define MX6_IOM_GRP_ADDDS 0x020e05ac
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#define MX6_IOM_GRP_CTLDS 0x020e05c8
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#define MX6_IOM_GRP_DDRMODE 0x020e05c0
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#define MX6_IOM_GRP_DDRPKE 0x020e05b4
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#define MX6_IOM_GRP_DDRMODE_CTL 0x020e05b0
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#define MX6_IOM_GRP_DDR_TYPE 0x020e05d0
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#define MX6_IOM_GRP_B0DS 0x020e05c4
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#define MX6_IOM_GRP_B1DS 0x020e05cc
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#define MX6_IOM_GRP_B2DS 0x020e05d4
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#define MX6_IOM_GRP_B3DS 0x020e05d8
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#endif /*__ASM_ARCH_MX6SL_DDR_H__ */
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@ -1,5 +1,11 @@
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/* Copyright (C) 2016 The Magma Company AS */
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#define CONFIG_MX6SL 1
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/* Avoid C declarations, we only want defines */
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#undef CONFIG_SPL_BUILD
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#define __ASSEMBLY__
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/crm_regs.h>
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/* image version */
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@ -25,52 +31,71 @@ BOOT_FROM sd
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*/
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/* =============================================================================*/
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/* Enable all clocks (they are disabled by ROM code*/
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/* Enable all clocks, they are disabled by ROM code */
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/* =============================================================================*/
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/* CCGR0; CAAM */
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DATA 4 0x020c4068 0xffffffff
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DATA 4 CCM_CCGR0 0xffffffff
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/* CCGR1; I2C4, SPI, ENET */
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DATA 4 0x020c406c 0xffffffff
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DATA 4 CCM_CCGR1 0xffffffff
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/* CCGR2; I2C1, I2C2, I2C3, LCDIF, OCOTP, GPMI */
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DATA 4 0x020c4070 0xffffffff
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DATA 4 CCM_CCGR2 0xffffffff
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/* CCGR3; ENET, LCDIF, QSPI 0, IPU 0 */
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DATA 4 0x020c4074 0xffffffff
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DATA 4 CCM_CCGR3 0xffffffff
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/* CCGR4; GPMI, PCIE, QSPI 1 */
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DATA 4 0x020c4078 0xffffffff
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DATA 4 CCM_CCGR4 0xffffffff
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/* CCGR5; UART, SATA */
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DATA 4 0x020c407c 0xffffffff
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DATA 4 CCM_CCGR5 0xffffffff
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/* CCGR6; USDHC, IPU, USBOH3, CAAM EMI slow clock */
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DATA 4 0x020c4080 0xffffffff
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DATA 4 CCM_CCGR6 0xffffffff
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/* ????; seems to be in several DCDs as well in the DDR script aid */
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/* Might be General Purpose Timer #0 Controller (USB_UOG1_GPTIMER0CTRL) */
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/* However, the absolute address is wrong in that case, might be some offset */
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DATA 4 0x020c4084 0xffffffff
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/* It is CCGR7 in imx5, not defined in i.MX6SL manual */
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/* DATA 4 0x020c4084 0xffffffff */
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/* DDR clk to 400MHz */
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/* CCM Bus Clock Multiplexer Register (CCM_CBCMR) in reference manual */
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DATA 4 0x020c4018 0x00260324
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DATA 4 CCM_CBCMR 0x00260324
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/* =============================================================================*/
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/* IOMUX*/
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/* IOMUX: Set up pins for memory controller */
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/* =============================================================================*/
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/* DDR IO TYPE:*/
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/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE*/
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/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE*/
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DATA 4 0x020e05c0 0x00020000
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DATA 4 0x020e05b4 0x00000000
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/* Bit 17: DDR / CMOS Input Mode Field
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Affected pads: DRAM_DATA00, DRAM_DATA01, DRAM_DATA02, DRAM_DATA03, DRAM_DATA04,
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DRAM_DATA05, DRAM_DATA06, DRAM_DATA07, DRAM_DATA08, DRAM_DATA09,
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DRAM_DATA10, DRAM_DATA11, DRAM_DATA12, DRAM_DATA13, DRAM_DATA14,
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DRAM_DATA15, DRAM_DATA16, DRAM_DATA17, DRAM_DATA18, DRAM_DATA19,
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DRAM_DATA20, DRAM_DATA21, DRAM_DATA22, DRAM_DATA23, DRAM_DATA24,
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DRAM_DATA25, DRAM_DATA26, DRAM_DATA27, DRAM_DATA28, DRAM_DATA29,
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DRAM_DATA30, DRAM_DATA31
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0 CMOS — CMOS input mode.
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1 DIFFERENTIAL — Differential input mode.*/
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DATA 4 MX6_IOM_GRP_DDRMODE 0x00020000 /* Select differential mode */
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/* Bit 12: Pull / Keep Enable Field
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Affected pads: DRAM_DATA00, DRAM_DATA01, DRAM_DATA02, DRAM_DATA03, DRAM_DATA04,
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DRAM_DATA05, DRAM_DATA06, DRAM_DATA07, DRAM_DATA08, DRAM_DATA09,
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DRAM_DATA10, DRAM_DATA11, DRAM_DATA12, DRAM_DATA13, DRAM_DATA14,
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DRAM_DATA15, DRAM_DATA16, DRAM_DATA17, DRAM_DATA18, DRAM_DATA19,
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DRAM_DATA20, DRAM_DATA21, DRAM_DATA22, DRAM_DATA23, DRAM_DATA24,
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DRAM_DATA25, DRAM_DATA26, DRAM_DATA27, DRAM_DATA28, DRAM_DATA29,
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DRAM_DATA30, DRAM_DATA31
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0 DISABLED — Pull/Keeper Disabled
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1 ENABLED — Pull/Keeper Enabled */
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DATA 4 MX6_IOM_GRP_DDRPKE 0x00000000 /* Disable pull/keeper */
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/* CLOCK:*/
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0*/
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DATA 4 0x020e0338 0x00000030
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
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/* Don't bother setting it, 0x00000030 is the default value */
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/* DATA 4 MX6_IOM_DRAM_SDCLK0_P 0x00000030 */
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/* Control:*/
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@ -81,24 +106,24 @@ DATA 4 0x020e0338 0x00000030
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/* IOMUXC_SW_PAD_CTL_GRP_ADDDS*/
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/* IOMUXC_SW_PAD_CTL_GRP_CTLDS*/
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DATA 4 0x020e0300 0x00000030
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DATA 4 0x020e031c 0x00000030
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DATA 4 0x020e0320 0x00000030
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DATA 4 0x020e032c 0x00000000
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DATA 4 0x020e05ac 0x00000030
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DATA 4 0x020e05c8 0x00000030
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DATA 4 MX6_IOM_DRAM_CAS_B 0x00000030
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DATA 4 MX6_IOM_DRAM_RAS_B 0x00000030
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DATA 4 MX6_IOM_DRAM_RESET 0x00000030
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DATA 4 MX6_IOM_DRAM_SDBA2 0x00000000
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DATA 4 MX6_IOM_GRP_ADDDS 0x00000030
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DATA 4 MX6_IOM_GRP_CTLDS 0x00000030
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/* Data Strobes:*/
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/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL*/
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/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL ?? IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0*/
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1*/
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2*/
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3*/
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DATA 4 0x020e05b0 0x00020000
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DATA 4 0x020e0344 0x00000030
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DATA 4 0x020e0348 0x00000030
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DATA 4 0x020e034c 0x00000030
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DATA 4 0x020e0350 0x00000030
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DATA 4 MX6_IOM_GRP_DDRMODE_CTL 0x00020000
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DATA 4 MX6_IOM_DRAM_SDQS0_P 0x00000030
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DATA 4 MX6_IOM_DRAM_SDQS1_P 0x00000030
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DATA 4 MX6_IOM_DRAM_SDQS2_P 0x00000030
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DATA 4 MX6_IOM_DRAM_SDQS3_P 0x00000030
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/* Data:*/
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@ -108,46 +133,47 @@ DATA 4 0x020e0350 0x00000030
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/* IOMUXC_SW_PAD_CTL_GRP_B2DS*/
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/* IOMUXC_SW_PAD_CTL_GRP_B3DS*/
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DATA 4 0x020e05d0 0x000C0000
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DATA 4 0x020e05c4 0x00000030
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DATA 4 0x020e05cc 0x00000030
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DATA 4 0x020e05d4 0x00000030
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DATA 4 0x020e05d8 0x00000030
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DATA 4 MX6_IOM_GRP_DDR_TYPE 0x000C0000
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DATA 4 MX6_IOM_GRP_B0DS 0x00000030
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DATA 4 MX6_IOM_GRP_B1DS 0x00000030
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DATA 4 MX6_IOM_GRP_B2DS 0x00000030
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DATA 4 MX6_IOM_GRP_B3DS 0x00000030
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0*/
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1*/
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2*/
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3*/
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DATA 4 0x020e030c 0x00000030
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DATA 4 0x020e0310 0x00000030
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DATA 4 0x020e0314 0x00000030
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DATA 4 0x020e0318 0x00000030
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DATA 4 MX6_IOM_DRAM_DQM0 0x00000030
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DATA 4 MX6_IOM_DRAM_DQM1 0x00000030
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DATA 4 MX6_IOM_DRAM_DQM2 0x00000030
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DATA 4 MX6_IOM_DRAM_DQM3 0x00000030
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/* ============================================================================= */
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/* DDR Controller Registers */
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/* ============================================================================= */
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/* Manufacturer: Micron */
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/* Device Part Number: MT41J128M16HA-187E */
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/* Clock Freq.: 400MHz */
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/* Density per CS in Gb: 4 */
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/* Chip Selects used: 2 */
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/* Total DRAM density (Gb) 8 */
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/* Number of Banks: 8 */
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/* Row address: 14 */
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/* Column address: 10 */
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/* Data bus width 32 */
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/* ============================================================================= */
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/* =============================================================================*/
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/* DDR Controller Registers*/
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/* =============================================================================*/
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/* Manufacturer: Micron*/
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/* Device Part Number: MT41J128M16HA-187E*/
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/* Clock Freq.: 400MHz*/
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/* Density per CS in Gb: 4*/
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/* Chip Selects used: 2*/
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/* Total DRAM density (Gb) 8*/
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/* Number of Banks: 8*/
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/* Row address: 14*/
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/* Column address: 10*/
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/* Data bus width 32*/
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/* =============================================================================*/
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/* DDR_PHY_P0_MPZQHWCTRL: enable both one-time & periodic HW ZQ calibration.*/
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/* change ZQ_HW_PER=256ms: Original - 0xa1390003*/
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DATA 4 0x021b0800 0xa1390023
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DATA 4 MX6_MMDC_P0_MPZQHWCTRL 0xa1390023
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/* write leveling: based on Freescale board layout and T topology*/
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/* For target board: may need to run write leveling calibration*/
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/* to fine tune these settings*/
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/* If target board does not use T topology: then these registers*/
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/* should either be cleared or write leveling calibration can be run*/
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DATA 4 0x021b080c 0x001F001F
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DATA 4 0x021b0810 0x001F001F
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DATA 4 MX6_MMDC_P0_MPWLDECTRL0 0x002D0028
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DATA 4 MX6_MMDC_P0_MPWLDECTRL1 0x00280028
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/* ######################################################*/
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/* calibration values based on calibration compare of 0x00ffff00:*/
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@ -159,25 +185,34 @@ DATA 4 0x021b0810 0x001F001F
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/* MPDGCTRL1 PHY0*/
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/* MPRDDLCTL PHY0*/
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/* MPWRDLCTL PHY0*/
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DATA 4 0x021b083c 0x407E007F
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DATA 4 0x021b0840 0x00690069
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DATA 4 0x021b0848 0x42424645
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DATA 4 0x021b0850 0x3B383630
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/*DATA 4 MX6_MMDC_P0_MPDGCTRL0 0x407E007F*/
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/*DATA 4 MX6_MMDC_P0_MPDGCTRL1 0x00690069*/
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/* Read DQS gating calibration */
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DATA 4 MX6_MMDC_P0_MPDGCTRL0 0x420C0204
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DATA 4 MX6_MMDC_P0_MPDGCTRL1 0x01700168
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/* DATA 4 MX6_MMDC_P0_MPRDDLCTL 0x42424645 */
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/* DATA 4 MX6_MMDC_P0_MPWRDLCTL 0x3B383630 */
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/* Read calibration */
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DATA 4 MX6_MMDC_P0_MPRDDLCTL 0x3E3E4446
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/* Write calibration */
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DATA 4 MX6_MMDC_P0_MPWRDLCTL 0x38343830
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/* DDR_PHY_P0_MPREDQBY0DL3*/
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/* DDR_PHY_P0_MPREDQBY1DL3*/
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/* DDR_PHY_P0_MPREDQBY2DL3*/
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/* DDR_PHY_P0_MPREDQBY3DL3*/
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DATA 4 0x021b081c 0x33333333
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DATA 4 0x021b0820 0x33333333
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DATA 4 0x021b0824 0x33333333
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DATA 4 0x021b0828 0x33333333
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DATA 4 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333
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DATA 4 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333
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DATA 4 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333
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DATA 4 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333
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/* Complete calibration by forced measurement:*/
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/* DDR_PHY_P0_MPMUR0: frc_msr*/
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DATA 4 0x021b08b8 0x00000800
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DATA 4 MX6_MMDC_P0_MPMUR0 0x00000800
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/* MMDC0_MDPDC*/
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/* MMDC0_MDOTC*/
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@ -185,54 +220,78 @@ DATA 4 0x021b08b8 0x00000800
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/* MMDC0_MDCFG1*/
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/* MMDC0_MDCFG2*/
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/* MMDC0_MDMISC*/
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DATA 4 0x021b0004 0x00020024
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DATA 4 0x021b0008 0x00333040
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DATA 4 0x021b000c 0x3F435313
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DATA 4 0x021b0010 0xB68E8B63
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DATA 4 0x021b0014 0x01FF00DB
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DATA 4 0x021b0018 0x00081740
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DATA 4 MX6_MMDC_P0_MDPDC 0x00020024
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DATA 4 MX6_MMDC_P0_MDOTC 0x00333040
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DATA 4 MX6_MMDC_P0_MDCFG0 0x3F435313
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DATA 4 MX6_MMDC_P0_MDCFG1 0xB68E8B63
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DATA 4 MX6_MMDC_P0_MDCFG2 0x01FF00DB
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DATA 4 MX6_MMDC_P0_MDMISC 0x00091740
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/* MMDC0_MDSCR: set the Configuration request bit during MMDC set up*/
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/* MMDC0_MDRWD; recommend to maintain the default values*/
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/* MMDC0_MDOR*/
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/* CS0_END*/
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/* =============================================================== */
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/* MMDC initialization sequence from 32.4.2 in the i.MX6SL manual */
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/* =============================================================== */
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/* MMDC0_MDCTL*/
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DATA 4 0x021b001c 0x00008000
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DATA 4 0x021b002c 0x000026d2
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DATA 4 0x021b0030 0x00431023
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DATA 4 0x021b0040 0x0000004F
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DATA 4 0x021b0000 0xC3190000
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/* Set the Configuration request bit during MMDC set up*/
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DATA 4 MX6_MMDC_P0_MDSCR MX6_MMDC_MDSCR_CON_REQ
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/* Delay register; recommend to maintain the default values*/
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DATA 4 MX6_MMDC_P0_MDRWD 0x000026d2
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/* Out of reset delay register */
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/* CKE HIGH to a valid command: 0 cycles */
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/* Time from SDE enable to CKE rise: 1 cycle */
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/* In case that DDR reset# is low, will wait */
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/* until it's high and thenwait this period until */
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/* rising CKE. (JEDEC value is 500 us) */
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/* Time from SDE enable to DDR reset# high: 14 cycles */
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DATA 4 MX6_MMDC_P0_MDOR 0x00431023
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/* CS0_END. Defines the absolute last address */
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/* associated with CS0 with increments of 256Mb. */
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/* CS0_END=AXI_ADDRESS[31:25] bits. */
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/* MMDC0_MDASP[CS0_END] should be set to */
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/* DDR_CS_SIZE/32M + 0x3f (channel 0 base address */
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/* begins at 0x80000000) */
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/* 512MB / 256Mbit => 16 + 0x3F => 0x4F */
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DATA 4 MX6_MMDC_P0_MDASP 0x0000004F
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/*DATA 4 MX6_MMDC_P0_MDASP 0x0000004F*/
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/*DATA 4 MX6_MMDC_P0_MDCTL 0xC3190000*/
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DATA 4 MX6_MMDC_P0_MDCTL 0x83190000
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/* Mode register writes*/
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/* MMDC0_MDSCR: MR2 write: CS0*/
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/* MMDC0_MDSCR: MR3 write: CS0*/
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/* MMDC0_MDSCR: MR1 write: CS0*/
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/* MMDC0_MDSCR: MR0 write: CS0*/
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/* MMDC0_MDSCR: ZQ calibration command sent to device on CS0*/
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DATA 4 0x021b001c 0x04008032
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DATA 4 0x021b001c 0x00008033
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DATA 4 0x021b001c 0x00048031
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DATA 4 0x021b001c 0x05208030
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DATA 4 0x021b001c 0x04008040
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/* MMDC0_MDSCR: MR2 write: Bank 0, CS0
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Load Mode Register Command
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DDR3, set correct CMD_CS, CMD_BA, CMD_ADDR_LSB, CMD_ADDR_MSB)*/
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DATA 4 MX6_MMDC_P0_MDSCR 0x02008032
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/*DATA 4 MX6_MMDC_P0_MDSCR 0x04008032*/
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DATA 4 MX6_MMDC_P0_MDSCR 0x00008033
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DATA 4 MX6_MMDC_P0_MDSCR 0x00048031
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DATA 4 MX6_MMDC_P0_MDSCR 0x05208030
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/* MMDC0_MDSCR: ZQ calibration command sent to device on CS0 */
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DATA 4 MX6_MMDC_P0_MDSCR 0x04008040
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/* MMDC0_MDSCR: MR2 write: CS1*/
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/* MMDC0_MDSCR: MR3 write: CS1*/
|
||||
/* MMDC0_MDSCR: MR1 write: CS1*/
|
||||
/* MMDC0_MDSCR: MR0 write: CS1*/
|
||||
/* MMDC0_MDSCR: ZQ calibration command sent to device on CS1*/
|
||||
DATA 4 0x021b001c 0x0400803A
|
||||
DATA 4 0x021b001c 0x0000803B
|
||||
DATA 4 0x021b001c 0x00048039
|
||||
DATA 4 0x021b001c 0x05208038
|
||||
DATA 4 0x021b001c 0x04008048
|
||||
/* FIXME: these stop the board when run a second time, we only use one CS? */
|
||||
/* DATA 4 MX6_MMDC_P0_MDSCR 0x0400803A */
|
||||
/* DATA 4 MX6_MMDC_P0_MDSCR 0x0000803B */
|
||||
/* DATA 4 MX6_MMDC_P0_MDSCR 0x00048039 */
|
||||
/* DATA 4 MX6_MMDC_P0_MDSCR 0x05208038 */
|
||||
/* MMDC0_MDSCR: ZQ calibration command sent to device on CS1 */
|
||||
/* DATA 4 MX6_MMDC_P0_MDSCR 0x04008048 */
|
||||
|
||||
|
||||
/* MMDC0_MDREF*/
|
||||
/* DDR_PHY_P0_MPODTCTRL*/
|
||||
DATA 4 0x021b0020 0x00005800
|
||||
DATA 4 0x021b0818 0x00011117
|
||||
DATA 4 MX6_MMDC_P0_MDREF 0x00005800
|
||||
/*DATA 4 MX6_MMDC_P0_MPODTCTRL 0x00011117*/
|
||||
DATA 4 MX6_MMDC_P0_MPODTCTRL 0x00022227
|
||||
|
||||
|
||||
|
||||
|
|
@ -240,7 +299,7 @@ DATA 4 0x021b0818 0x00011117
|
|||
/* MMDC0_MAPSR ADOPT power down enabled*/
|
||||
/* MMDC0_MDSCR: clear this register (especially the configuration bit as initialization is complete*/
|
||||
|
||||
DATA 4 0x021b0004 0x00025564
|
||||
DATA 4 0x021b0404 0x00011006
|
||||
DATA 4 0x021b001c 0x00000000
|
||||
DATA 4 MX6_MMDC_P0_MDPDC 0x00025564
|
||||
DATA 4 MX6_MMDC_P0_MAPSR 0x00011006
|
||||
DATA 4 MX6_MMDC_P0_MDSCR 0x00000000
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue