powerpc: ppc4xx: remove zeus support
This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Stefan Roese <sr@denx.de>utp
Masahiro Yamada
Tom Rini
parent
0e03059396
commit
eb5d1dc7a6
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@ -11,9 +11,6 @@ choice
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config TARGET_T3CORP
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bool "Support t3corp"
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config TARGET_ZEUS
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bool "Support zeus"
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config TARGET_ACADIA
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bool "Support acadia"
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@ -176,6 +173,5 @@ source "board/xes/xpedite1000/Kconfig"
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source "board/xilinx/ml507/Kconfig"
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source "board/xilinx/ppc405-generic/Kconfig"
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source "board/xilinx/ppc440-generic/Kconfig"
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source "board/zeus/Kconfig"
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endmenu
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@ -1805,21 +1805,6 @@ ppc405ep_init:
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bne _pci_66mhz
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#endif /* CONFIG_TAIHU */
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#if defined(CONFIG_ZEUS)
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mfdcr r4, CPC0_BOOT
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andi. r5, r4, CPC0_BOOT_SEP@l
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bne strap_1 /* serial eeprom present */
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lis r3,0x0000
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addi r3,r3,0x3030
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lis r4,0x8042
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addi r4,r4,0x223e
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b 1f
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strap_1:
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mfdcr r3, CPC0_PLLMR0
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mfdcr r4, CPC0_PLLMR1
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b 1f
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#endif
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addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
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ori r3,r3,PLLMR0_DEFAULT@l /* */
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addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
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@ -1,9 +0,0 @@
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if TARGET_ZEUS
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config SYS_BOARD
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default "zeus"
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config SYS_CONFIG_NAME
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default "zeus"
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endif
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@ -1,6 +0,0 @@
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ZEUS BOARD
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M: Stefan Roese <sr@denx.de>
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S: Maintained
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F: board/zeus/
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F: include/configs/zeus.h
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F: configs/zeus_defconfig
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2007
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# Stefan Roese, DENX Software Engineering, sr@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = zeus.o update.o
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@ -1,73 +0,0 @@
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Storage of the board specific values (ethaddr...)
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-------------------------------------------------
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The board specific environment variables that should be unique
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for each individual board, can be stored in the I2C EEPROM. This
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will be done from offset 0x80 with the length of 0x80 bytes. The
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following command can be used to store the values here:
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=> setdef de:20:6a:ed:e2:72 de:20:6a:ed:e2:73 AB0001
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ethaddr eth1addr serial#
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Now those 3 values are stored into the I2C EEPROM. A CRC is added
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to make sure that the values get not corrupted.
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SW-Reset Pushbutton handling:
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-----------------------------
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The SW-reset push button is connected to a GPIO input too. This
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way U-Boot can "see" how long the SW-reset was pressed, and a
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specific action can be taken. Two different actions are supported:
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a) Release after more than 5 seconds and less then 10 seconds:
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-> Run POST
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Please note, that the POST test will take a while (approx. 1 min
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on the 128MByte board). This is mainly due to the system memory
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test.
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b) Release after more than 10 seconds:
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-> Restore factory default settings
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The factory default values are restored. The default environment
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variables are restored (ipaddr, serverip...) and the board
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specific values (ethaddr, eth1addr and serial#) are restored
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to the environment from the I2C EEPROM. Also a bootline parameter
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is added to the Linux bootline to signal the Linux kernel upon
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the next startup, that the factory defaults should be restored.
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The command to check this sw-reset status and act accordingly is
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=> chkreset
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This command is added to the default "bootcmd", so that it is called
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automatically upon startup.
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Also, the 2 LED's are used to indicate the current status of this
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command (time passed since pushing the button). When the POST test
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will be run, the green LED will be switched off, and when the
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factory restore will be initiated, the reg LED will be switched off.
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Loggin of POST results:
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-----------------------
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The results of the POST tests are logged in a logbuffer located at the end
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of the onboard memory. It can be accessed with the U-Boot command "log":
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=> log show
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<4>POST memory PASSED
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<4>POST cache PASSED
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<4>POST cpu PASSED
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<4>POST uart PASSED
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<4>POST ethernet PASSED
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The DENX Linux kernel tree has support for this log buffer included. Exactly
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this buffer is used for logging of all kernel messages too. By enabling the
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compile time option "CONFIG_LOGBUFFER" this support is enabled. This way you
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can access the U-Boot log messages from Linux too.
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2007-08-10, Stefan Roese <sr@denx.de>
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@ -1,89 +0,0 @@
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/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/ppc4xx-gpio.h>
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#include <i2c.h>
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#if defined(CONFIG_ZEUS)
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u8 buf_zeus_ce[] = {
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/*00 01 02 03 04 05 06 07 */
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0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/*08 09 0a 0b 0c 0d 0e 0f */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/*10 11 12 13 14 15 16 17 */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/*18 19 1a 1b 1c 1d 1e 1f */
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0x00, 0xc0, 0x50, 0x12, 0x72, 0x3e, 0x00, 0x00 };
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u8 buf_zeus_pe[] = {
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/* CPU_CLOCK_DIV 1 = 00
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CPU_PLB_FREQ_DIV 3 = 10
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OPB_PLB_FREQ_DIV 2 = 01
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EBC_PLB_FREQ_DIV 2 = 00
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MAL_PLB_FREQ_DIV 1 = 00
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PCI_PLB_FRQ_DIV 3 = 10
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PLL_PLLOUTA = IS SET
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PLL_OPERATING = IS NOT SET
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PLL_FDB_MUL 10 = 1010
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PLL_FWD_DIV_A 3 = 101
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PLL_FWD_DIV_B 3 = 101
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TUNE = 0x2be */
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/*00 01 02 03 04 05 06 07 */
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0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/*08 09 0a 0b 0c 0d 0e 0f */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/*10 11 12 13 14 15 16 17 */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/*18 19 1a 1b 1c 1d 1e 1f */
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0x00, 0x60, 0x68, 0x2d, 0x42, 0xbe, 0x00, 0x00 };
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static int update_boot_eeprom(void)
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{
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u32 len = 0x20;
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u8 chip = CONFIG_SYS_I2C_EEPROM_ADDR;
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u8 *pbuf;
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u8 base;
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int i;
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if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_ZEUS_PE)) {
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pbuf = buf_zeus_pe;
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base = 0x40;
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} else {
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pbuf = buf_zeus_ce;
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base = 0x00;
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}
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for (i = 0; i < len; i++, base++) {
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if (i2c_write(chip, base, 1, &pbuf[i], 1) != 0) {
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printf("i2c_write fail\n");
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return 1;
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}
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udelay(11000);
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}
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return 0;
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}
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int do_update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char * const argv[])
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{
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return update_boot_eeprom();
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}
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U_BOOT_CMD (
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update_boot_eeprom, 1, 1, do_update_boot_eeprom,
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"update boot eeprom content",
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""
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);
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#endif
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@ -1,410 +0,0 @@
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/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <malloc.h>
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#include <environment.h>
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#include <logbuff.h>
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#include <post.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/ppc4xx-gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define REBOOT_MAGIC 0x07081967
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#define REBOOT_NOP 0x00000000
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#define REBOOT_DO_POST 0x00000001
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extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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ulong flash_get_size(ulong base, int banknum);
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void env_crc_update(void);
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static u32 start_time;
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int board_early_init_f(void)
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{
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr(UIC0ER, 0x00000000); /* disable all ints */
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mtdcr(UIC0CR, 0x00000000);
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mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */
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mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
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/*
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* Configure CPC0_PCI to enable PerWE as output
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*/
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mtdcr(CPC0_PCI, CPC0_PCI_SPE);
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return 0;
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}
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int misc_init_r(void)
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{
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u32 pbcr;
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int size_val = 0;
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u32 post_magic;
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u32 post_val;
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post_magic = in_be32((void *)CONFIG_SYS_POST_MAGIC);
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post_val = in_be32((void *)CONFIG_SYS_POST_VAL);
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if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) {
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/*
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* Set special bootline bootparameter to pass this POST boot
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* mode to Linux to reset the username/password
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*/
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setenv("addmisc", "setenv bootargs \\${bootargs} factory_reset=yes");
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/*
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* Normally don't run POST tests, only when enabled
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* via the sw-reset button. So disable further tests
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* upon next bootup here.
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*/
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out_be32((void *)CONFIG_SYS_POST_VAL, REBOOT_NOP);
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} else {
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/*
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* Only run POST when initiated via the sw-reset button mechanism
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*/
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post_word_store(0);
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}
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/*
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* Get current time
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*/
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start_time = get_timer(0);
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/*
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* FLASH stuff...
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*/
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/* Re-do sizing to get full correct info */
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/* adjust flash start and offset */
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mfebc(PB0CR, pbcr);
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switch (gd->bd->bi_flashsize) {
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case 1 << 20:
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size_val = 0;
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break;
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case 2 << 20:
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size_val = 1;
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break;
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case 4 << 20:
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size_val = 2;
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break;
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case 8 << 20:
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size_val = 3;
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break;
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case 16 << 20:
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size_val = 4;
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break;
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case 32 << 20:
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size_val = 5;
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break;
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case 64 << 20:
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size_val = 6;
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break;
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case 128 << 20:
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size_val = 7;
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break;
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}
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pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
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mtebc(PB0CR, pbcr);
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/*
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* Re-check to get correct base address
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*/
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flash_get_size(gd->bd->bi_flashstart, 0);
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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-CONFIG_SYS_MONITOR_LEN,
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0xffffffff,
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&flash_info[0]);
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/* Env protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR_REDUND,
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CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
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&flash_info[0]);
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return 0;
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}
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/*
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* Check Board Identity:
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*/
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int checkboard(void)
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{
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char buf[64];
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int i = getenv_f("serial#", buf, sizeof(buf));
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puts("Board: Zeus-");
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if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_ZEUS_PE))
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puts("PE");
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else
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puts("CE");
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puts(" of BulletEndPoint");
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if (i > 0) {
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puts(", serial# ");
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puts(buf);
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}
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putc('\n');
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/* both LED's off */
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gpio_write_bit(CONFIG_SYS_GPIO_LED_RED, 0);
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gpio_write_bit(CONFIG_SYS_GPIO_LED_GREEN, 0);
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udelay(10000);
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/* and on again */
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gpio_write_bit(CONFIG_SYS_GPIO_LED_RED, 1);
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gpio_write_bit(CONFIG_SYS_GPIO_LED_GREEN, 1);
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return (0);
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}
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static int default_env_var(char *buf, char *var)
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{
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char *ptr;
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char *val;
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/*
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* Find env variable
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*/
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ptr = strstr(buf + 4, var);
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if (ptr == NULL) {
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printf("ERROR: %s not found!\n", var);
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return -1;
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}
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ptr += strlen(var) + 1;
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/*
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* Now the ethaddr needs to be updated in the "normal"
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* environment storage -> redundant flash.
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*/
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val = ptr;
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setenv(var, val);
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printf("Updated %s from eeprom to %s!\n", var, val);
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return 0;
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}
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static int restore_default(void)
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{
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char *buf;
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char *buf_save;
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u32 crc;
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set_default_env("");
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gd->env_valid = 1;
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/*
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* Read board specific values from I2C EEPROM
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* and set env variables accordingly
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* -> ethaddr, eth1addr, serial#
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*/
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buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE);
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if (buf == NULL) {
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printf("ERROR: malloc() failed\n");
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return -1;
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}
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if (eeprom_read(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS,
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(u8 *)buf, FACTORY_RESET_ENV_SIZE)) {
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puts("\nError reading EEPROM!\n");
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} else {
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crc = crc32(0, (u8 *)(buf + 4), FACTORY_RESET_ENV_SIZE - 4);
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if (crc != *(u32 *)buf) {
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printf("ERROR: crc mismatch %08x %08x\n", crc, *(u32 *)buf);
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return -1;
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}
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default_env_var(buf, "ethaddr");
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buf += 8 + 18;
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default_env_var(buf, "eth1addr");
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buf += 9 + 18;
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default_env_var(buf, "serial#");
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}
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/*
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* Finally save updated env variables back to flash
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*/
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saveenv();
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free(buf_save);
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return 0;
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}
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int do_set_default(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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char *buf;
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char *buf_save;
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char str[32];
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u32 crc;
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char var[32];
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if (argc < 4) {
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puts("ERROR!\n");
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return -1;
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}
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||||
|
||||
buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE);
|
||||
memset(buf, 0, FACTORY_RESET_ENV_SIZE);
|
||||
|
||||
strcpy(var, "ethaddr");
|
||||
printf("Setting %s to %s\n", var, argv[1]);
|
||||
sprintf(str, "%s=%s", var, argv[1]);
|
||||
strcpy(buf + 4, str);
|
||||
buf += strlen(str) + 1;
|
||||
|
||||
strcpy(var, "eth1addr");
|
||||
printf("Setting %s to %s\n", var, argv[2]);
|
||||
sprintf(str, "%s=%s", var, argv[2]);
|
||||
strcpy(buf + 4, str);
|
||||
buf += strlen(str) + 1;
|
||||
|
||||
strcpy(var, "serial#");
|
||||
printf("Setting %s to %s\n", var, argv[3]);
|
||||
sprintf(str, "%s=%s", var, argv[3]);
|
||||
strcpy(buf + 4, str);
|
||||
|
||||
crc = crc32(0, (u8 *)(buf_save + 4), FACTORY_RESET_ENV_SIZE - 4);
|
||||
*(u32 *)buf_save = crc;
|
||||
|
||||
if (eeprom_write(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS,
|
||||
(u8 *)buf_save, FACTORY_RESET_ENV_SIZE)) {
|
||||
puts("\nError writing EEPROM!\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
free(buf_save);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
setdef, 4, 1, do_set_default,
|
||||
"write board-specific values to EEPROM (ethaddr...)",
|
||||
"ethaddr eth1addr serial#\n - write board-specific values to EEPROM"
|
||||
);
|
||||
|
||||
static inline int sw_reset_pressed(void)
|
||||
{
|
||||
return !(in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_SW_RESET));
|
||||
}
|
||||
|
||||
int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
int delta;
|
||||
int count = 0;
|
||||
int post = 0;
|
||||
int factory_reset = 0;
|
||||
|
||||
if (!sw_reset_pressed()) {
|
||||
printf("SW-Reset already high (Button released)\n");
|
||||
printf("-> No action taken!\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
printf("Waiting for SW-Reset button to be released.");
|
||||
|
||||
while (1) {
|
||||
delta = get_timer(start_time);
|
||||
if (!sw_reset_pressed())
|
||||
break;
|
||||
|
||||
if ((delta > CONFIG_SYS_TIME_POST) && !post) {
|
||||
printf("\nWhen released now, POST tests will be started.");
|
||||
gpio_write_bit(CONFIG_SYS_GPIO_LED_GREEN, 0);
|
||||
post = 1;
|
||||
}
|
||||
|
||||
if ((delta > CONFIG_SYS_TIME_FACTORY_RESET) && !factory_reset) {
|
||||
printf("\nWhen released now, factory default values"
|
||||
" will be restored.");
|
||||
gpio_write_bit(CONFIG_SYS_GPIO_LED_RED, 0);
|
||||
factory_reset = 1;
|
||||
}
|
||||
|
||||
udelay(1000);
|
||||
if (!(count++ % 1000))
|
||||
printf(".");
|
||||
}
|
||||
|
||||
|
||||
printf("\nSW-Reset Button released after %d milli-seconds!\n", delta);
|
||||
|
||||
if (delta > CONFIG_SYS_TIME_FACTORY_RESET) {
|
||||
printf("Starting factory reset value restoration...\n");
|
||||
|
||||
/*
|
||||
* Restore default setting
|
||||
*/
|
||||
restore_default();
|
||||
|
||||
/*
|
||||
* Reset the board for default to become valid
|
||||
*/
|
||||
do_reset(NULL, 0, 0, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (delta > CONFIG_SYS_TIME_POST) {
|
||||
printf("Starting POST configuration...\n");
|
||||
|
||||
/*
|
||||
* Enable POST upon next bootup
|
||||
*/
|
||||
out_be32((void *)CONFIG_SYS_POST_MAGIC, REBOOT_MAGIC);
|
||||
out_be32((void *)CONFIG_SYS_POST_VAL, REBOOT_DO_POST);
|
||||
post_bootmode_init();
|
||||
|
||||
/*
|
||||
* Reset the logbuffer for a clean start
|
||||
*/
|
||||
logbuff_reset();
|
||||
|
||||
do_reset(NULL, 0, 0, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD (
|
||||
chkreset, 1, 1, do_chkreset,
|
||||
"Check for status of SW-reset button and act accordingly",
|
||||
""
|
||||
);
|
||||
|
||||
#if defined(CONFIG_POST)
|
||||
/*
|
||||
* Returns 1 if keys pressed to start the power-on long-running tests
|
||||
* Called from board_init_f().
|
||||
*/
|
||||
int post_hotkeys_pressed(void)
|
||||
{
|
||||
u32 post_magic;
|
||||
u32 post_val;
|
||||
|
||||
post_magic = in_be32((void *)CONFIG_SYS_POST_MAGIC);
|
||||
post_val = in_be32((void *)CONFIG_SYS_POST_VAL);
|
||||
|
||||
if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST))
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_POST */
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_4xx=y
|
||||
CONFIG_TARGET_ZEUS=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
|
|
@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
|
|||
|
||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||
=================================================================================================
|
||||
zeus powerpc ppc4xx - - Stefan Roese <sr@denx.de>
|
||||
sbc405 powerpc ppc4xx - -
|
||||
pcs440ep powerpc ppc4xx - - Stefan Roese <sr@denx.de>
|
||||
p3p440 powerpc ppc4xx - - Stefan Roese <sr@denx.de>
|
||||
|
|
|
|||
|
|
@ -1,350 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/************************************************************************
|
||||
* zeus.h - configuration for Zeus board
|
||||
***********************************************************************/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_ZEUS 1 /* Board is Zeus */
|
||||
#define CONFIG_405EP 1 /* Specifc 405EP support*/
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
|
||||
|
||||
#define PLLMR0_DEFAULT PLLMR0_333_111_55_111
|
||||
#define PLLMR1_DEFAULT PLLMR1_333_111_55_111
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
|
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
|
||||
|
||||
#define CONFIG_PPC4xx_EMAC
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 0x01 /* PHY address */
|
||||
#define CONFIG_HAS_ETH1 1
|
||||
#define CONFIG_PHY1_ADDR 0x11 /* EMAC1 PHY address */
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
|
||||
#define CONFIG_PHY_RESET 1
|
||||
#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_DIAG
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_REGINFO
|
||||
|
||||
/* POST support */
|
||||
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
|
||||
CONFIG_SYS_POST_CPU | \
|
||||
CONFIG_SYS_POST_CACHE | \
|
||||
CONFIG_SYS_POST_UART | \
|
||||
CONFIG_SYS_POST_ETHER)
|
||||
|
||||
#define CONFIG_SYS_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */
|
||||
|
||||
/* Define here the base-addresses of the UARTs to test in POST */
|
||||
#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 }
|
||||
|
||||
#define CONFIG_LOGBUFFER
|
||||
#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
|
||||
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SDRAM
|
||||
*----------------------------------------------------------------------*/
|
||||
/*
|
||||
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
|
||||
*/
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
|
||||
#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
|
||||
|
||||
/* SDRAM timings used in datasheet */
|
||||
#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
|
||||
#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
|
||||
#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
|
||||
#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
|
||||
#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
|
||||
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
|
||||
#define CONFIG_SYS_BASE_BAUD 691200
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
#define CONFIG_LOOPW 1 /* enable loopw command */
|
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
|
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_PPC4XX
|
||||
#define CONFIG_SYS_I2C_PPC4XX_CH0
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
|
||||
|
||||
/* these are for the ST M24C02 2kbit serial i2c eeprom */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
|
||||
/* mask of address bits that overflow into the "EEPROM chip address" */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
|
||||
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 byte write page size */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
|
||||
/*
|
||||
* The layout of the I2C EEPROM, used for bootstrap setup and for board-
|
||||
* specific values, like ethaddr... that can be restored via the sw-reset
|
||||
* button
|
||||
*/
|
||||
#define FACTORY_RESET_I2C_EEPROM 0x50
|
||||
#define FACTORY_RESET_ENV_OFFS 0x80
|
||||
#define FACTORY_RESET_ENV_SIZE 0x80
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFF000000
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
|
||||
#define CONFIG_SYS_MONITOR_BASE (-CONFIG_SYS_MONITOR_LEN)
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
|
||||
#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in data cache)
|
||||
*/
|
||||
/* use on chip memory (OCM) for temperary stack until sdram is tested */
|
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1
|
||||
|
||||
/* On Chip Memory location */
|
||||
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
|
||||
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
/* reserve some memory for POST and BOOT limit info */
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 16)
|
||||
|
||||
/* extra data in OCM */
|
||||
#define CONFIG_SYS_POST_MAGIC \
|
||||
(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 8)
|
||||
#define CONFIG_SYS_POST_VAL \
|
||||
(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 12)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup
|
||||
*/
|
||||
|
||||
/* Memory Bank 0 (Flash 16M) initialization */
|
||||
#define CONFIG_SYS_EBC_PB0AP 0x05815600
|
||||
#define CONFIG_SYS_EBC_PB0CR 0xFF09A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for GPIO setup (PPC405EP specific)
|
||||
*
|
||||
* GPIO0[0] - External Bus Controller BLAST output
|
||||
* GPIO0[1-9] - Instruction trace outputs
|
||||
* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
|
||||
* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
|
||||
* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
|
||||
* GPIO0[24-27] - UART0 control signal inputs/outputs
|
||||
* GPIO0[28-29] - UART1 data signal input/output
|
||||
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
|
||||
*/
|
||||
#define CONFIG_SYS_GPIO0_OSRL 0x15555550 /* Chip selects */
|
||||
#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* UART_DTR-pin 27 alt out */
|
||||
#define CONFIG_SYS_GPIO0_ISR1L 0x10000041 /* Pin 2, 12 is input */
|
||||
#define CONFIG_SYS_GPIO0_ISR1H 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
|
||||
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
|
||||
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
|
||||
#define CONFIG_SYS_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */
|
||||
#define CONFIG_SYS_GPIO0_ODR 0x00000000
|
||||
|
||||
#define CONFIG_SYS_GPIO_SW_RESET 1
|
||||
#define CONFIG_SYS_GPIO_ZEUS_PE 12
|
||||
#define CONFIG_SYS_GPIO_LED_RED 22
|
||||
#define CONFIG_SYS_GPIO_LED_GREEN 23
|
||||
|
||||
/* Time in milli-seconds */
|
||||
#define CONFIG_SYS_TIME_POST 5000
|
||||
#define CONFIG_SYS_TIME_FACTORY_RESET 10000
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Pass open firmware flat tree
|
||||
*/
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
|
||||
/* ENVIRONMENT VARS */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo"
|
||||
#define CONFIG_IPADDR 192.168.1.10
|
||||
#define CONFIG_SERVERIP 192.168.1.100
|
||||
#define CONFIG_GATEWAYIP 192.168.1.100
|
||||
#if 0
|
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
||||
#else
|
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
|
||||
#endif
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"logversion=2\0" \
|
||||
"hostname=zeus\0" \
|
||||
"netdev=eth0\0" \
|
||||
"ethact=ppc_4xx_eth0\0" \
|
||||
"netmask=255.255.255.0\0" \
|
||||
"ramdisk_size=50000\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw" \
|
||||
" nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw" \
|
||||
" ramdisk_size=${ramdisk_size}\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0," \
|
||||
"${baudrate}\0" \
|
||||
"net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \
|
||||
"run nfsargs addip addtty;bootm\0" \
|
||||
"net_ram=tftp ${kernel_mem_addr} ${file_kernel};" \
|
||||
"tftp ${ramdisk_mem_addr} ${file_fs};" \
|
||||
"run ramargs addip addtty;" \
|
||||
"bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0" \
|
||||
"rootpath=/target_fs/zeus\0" \
|
||||
"kernel_fl_addr=ff000000\0" \
|
||||
"kernel_mem_addr=200000\0" \
|
||||
"ramdisk_fl_addr=ff300000\0" \
|
||||
"ramdisk_mem_addr=4000000\0" \
|
||||
"uboot_fl_addr=fffc0000\0" \
|
||||
"uboot_mem_addr=100000\0" \
|
||||
"file_uboot=/zeus/u-boot.bin\0" \
|
||||
"tftp_uboot=tftp 100000 ${file_uboot}\0" \
|
||||
"update_uboot=protect off fffc0000 ffffffff;" \
|
||||
"era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;" \
|
||||
"protect on fffc0000 ffffffff\0" \
|
||||
"upd_uboot=run tftp_uboot;run update_uboot\0" \
|
||||
"file_kernel=/zeus/uImage_ba\0" \
|
||||
"tftp_kernel=tftp 100000 ${file_kernel}\0" \
|
||||
"update_kernel=protect off ff000000 ff17ffff;" \
|
||||
"era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0" \
|
||||
"upd_kernel=run tftp_kernel;run update_kernel\0" \
|
||||
"file_fs=/zeus/rootfs_ba.img\0" \
|
||||
"tftp_fs=tftp 100000 ${file_fs}\0" \
|
||||
"update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
|
||||
"cp.b 100000 ff300000 580000\0" \
|
||||
"upd_fs=run tftp_fs;run update_fs\0" \
|
||||
"bootcmd=chkreset;run ramargs addip addtty addmisc;" \
|
||||
"bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \
|
||||
""
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue