board: update SPL code to match DCD, add usb failsafe boot mode
Martin T. H. Sandsmark
parent
09627d5f52
commit
fce825d4b9
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@ -1030,54 +1030,54 @@ int checkboard(void)
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#include <spl.h>
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#include <libfdt.h>
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const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_sdclk_0 = 0x00020030,
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.dram_sdclk_1 = 0x00020030,
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.dram_cas = 0x00020030,
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.dram_ras = 0x00020030,
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.dram_reset = 0x00020030,
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.dram_sdcke0 = 0x00003000,
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.dram_sdcke1 = 0x00003000,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = 0x00003030,
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.dram_sdodt1 = 0x00003030,
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const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_sdclk_0 = 0x00000030,
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.dram_cas = 0x00000030,
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.dram_ras = 0x00000030,
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.dram_reset = 0x00000030,
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.dram_sdba2 = 0x00000030,
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.dram_sdqs0 = 0x00000030,
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.dram_sdqs1 = 0x00000030,
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.dram_sdqs2 = 0x00000030,
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.dram_sdqs3 = 0x00000030,
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.dram_sdqs4 = 0x00000030,
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.dram_sdqs5 = 0x00000030,
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.dram_sdqs6 = 0x00000030,
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.dram_sdqs7 = 0x00000030,
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.dram_dqm0 = 0x00020030,
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.dram_dqm1 = 0x00020030,
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.dram_dqm2 = 0x00020030,
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.dram_dqm3 = 0x00020030,
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.dram_dqm4 = 0x00020030,
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.dram_dqm5 = 0x00020030,
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.dram_dqm6 = 0x00020030,
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.dram_dqm7 = 0x00020030,
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};
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const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = {
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.grp_ddr_type = 0x000C0000,
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.grp_ddrpke = 0x00000000,
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.grp_addds = 0x00000030,
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.grp_ctlds = 0x00000030,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = 0x00000030,
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.grp_b1ds = 0x00000030,
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.grp_b2ds = 0x00000030,
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.grp_b3ds = 0x00000030,
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.grp_addds = 0x00000030,
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.grp_ctlds = 0x00000030,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_ddrmode = 0x00020000,
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.grp_ddr_type = 0x00080000,
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};
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const struct mx6_mmdc_calibration mx6_mmcd_calib = {
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.p0_mpdgctrl0 = 0x20000000,
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.p0_mpdgctrl1 = 0x00000000,
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.p0_mprddlctl = 0x4241444a,
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.p0_mpwrdlctl = 0x3030312b,
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.mpzqlp2ctl = 0x1b4700c7,
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.p0_mpwldectrl0 = 0x002D0028,
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.p0_mpwldectrl1 = 0x00280028,
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.p0_mpdgctrl0 = 0x420C0204,
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.p0_mpdgctrl1 = 0x01700168,
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.p0_mprddlctl = 0x3E3E4446,
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.p0_mpwrdlctl = 0x38343830,
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};
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/* MT41K128M16JT-125 */
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@ -1094,6 +1094,25 @@ static struct mx6_ddr3_cfg mem_ddr = {
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.trasmin = 3500,
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};
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static struct mx6_ddr_sysinfo ddr_info = {
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/* width of data bus:0=16,1=32,2=64 */
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.dsize = 1,
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/* config for full 4GB range so that get_mem_size() works */
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.cs_density = 32, /* 32Gb per CS */
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/* single chip select */
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.ncs = 1,
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.cs1_mirror = 0,
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.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
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.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
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.walat = 1, /* Write additional latency */
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.ralat = 5, /* Read additional latency */
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.mif3_mode = 3, /* Command prediction working mode */
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.bi_on = 1, /* Bank interleaving enabled */
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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.ddr_type = DDR_TYPE_DDR3,
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};
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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@ -1109,30 +1128,27 @@ static void ccgr_init(void)
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writel(0x00260324, &ccm->cbcmr);
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}
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static void spl_dram_init(void)
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void board_boot_order(u32 *spl_boot_list)
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{
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struct mx6_ddr_sysinfo sysinfo = {
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/* width of data bus:0=16,1=32,2=64 */
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.dsize = 2,
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/* config for full 4GB range so that get_mem_size() works */
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.cs_density = 32, /* 32Gb per CS */
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/* single chip select */
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.ncs = 1,
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.cs1_mirror = 0,
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.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
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.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
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.walat = 1, /* Write additional latency */
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.ralat = 5, /* Read additional latency */
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.mif3_mode = 3, /* Command prediction working mode */
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.bi_on = 1, /* Bank interleaving enabled */
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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.ddr_type = DDR_TYPE_DDR3,
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};
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mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
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mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
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/* From SoC boot config pins */
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spl_boot_list[0] = spl_boot_device();
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/* Default location */
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spl_boot_list[1] = BOOT_DEVICE_MMC1;
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/* Fall back to FSL USB serial download mode */
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spl_boot_list[3] = BOOT_DEVICE_BOARD;
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}
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int spl_board_load_image(void)
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{
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debug("Jumping to HAB failsafe USB download mode...\n");
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hab_rvt_failsafe();
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return 0;
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}
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void board_init_f(ulong dummy)
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{
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/* setup AIPS and disable watchdog */
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@ -1140,20 +1156,15 @@ void board_init_f(ulong dummy)
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ccgr_init();
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/* iomux and setup of i2c */
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board_early_init_f();
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enable_uart_clk(1);
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setup_iomux_uart();
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/* setup GP timer */
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timer_init();
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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/* DDR initialization */
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spl_dram_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
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mx6_dram_cfg(&ddr_info, &mx6_mmcd_calib, &mem_ddr);
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/* load/boot image from boot device */
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board_init_r(NULL, 0);
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@ -15,6 +15,7 @@
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#ifdef CONFIG_SPL
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SPL_BOARD_LOAD_IMAGE
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#include "imx6_spl.h"
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#endif
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