2017-06-27 20:27:24 -06:00
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#include "config.h"
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#include "early.h"
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2017-04-06 19:11:36 -06:00
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#define NULL ((void*)0)
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// assign CAN numbering
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// old: CAN1 = 1 CAN2 = 0
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// panda: CAN1 = 0 CAN2 = 1 CAN3 = 4
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#ifdef PANDA
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int can_numbering[] = {0,1,4};
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#else
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int can_numbering[] = {1,0,-1};
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#endif
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2017-05-26 22:38:39 -06:00
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// can forwards FROM -> TO
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#define CAN_MAX 3
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int can_forwarding[] = {-1,-1,-1};
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2017-04-06 19:11:36 -06:00
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// *** end config ***
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#include "obj/gitversion.h"
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// debug safety check: is controls allowed?
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int controls_allowed = 0;
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int started = 0;
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int can_live = 0, pending_can_live = 0;
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// optional features
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int gas_interceptor_detected = 0;
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int started_signal_detected = 0;
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// detect high on UART
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// TODO: check for UART high
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int did_usb_enumerate = 0;
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2017-06-12 02:05:24 -06:00
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// Declare puts to supress warning
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int puts ( const char * str );
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2017-04-06 19:11:36 -06:00
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// ********************* instantiate queues *********************
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typedef struct {
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2017-05-16 22:33:28 -06:00
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uint32_t w_ptr;
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uint32_t r_ptr;
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uint32_t fifo_size;
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CAN_FIFOMailBox_TypeDef *elems;
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2017-04-06 19:11:36 -06:00
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} can_ring;
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2017-05-16 22:33:28 -06:00
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#define can_buffer(x, size) \
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CAN_FIFOMailBox_TypeDef elems_##x[size]; \
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can_ring can_##x = { .w_ptr = 0, .r_ptr = 0, .fifo_size = size, .elems = (CAN_FIFOMailBox_TypeDef *)&elems_##x };
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can_buffer(rx_q, 0x1000)
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can_buffer(tx1_q, 0x100)
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can_buffer(tx2_q, 0x100)
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can_buffer(tx3_q, 0x100)
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2017-04-06 19:11:36 -06:00
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// ********************* interrupt safe queue *********************
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2017-06-12 01:53:18 -06:00
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int pop(can_ring *q, CAN_FIFOMailBox_TypeDef *elem) {
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2017-04-06 19:11:36 -06:00
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if (q->w_ptr != q->r_ptr) {
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*elem = q->elems[q->r_ptr];
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2017-05-16 22:33:28 -06:00
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if ((q->r_ptr + 1) == q->fifo_size) q->r_ptr = 0;
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else q->r_ptr += 1;
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2017-04-06 19:11:36 -06:00
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return 1;
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}
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return 0;
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}
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2017-06-12 01:53:18 -06:00
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int push(can_ring *q, CAN_FIFOMailBox_TypeDef *elem) {
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2017-05-16 22:33:28 -06:00
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uint32_t next_w_ptr;
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if ((q->w_ptr + 1) == q->fifo_size) next_w_ptr = 0;
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else next_w_ptr = q->w_ptr + 1;
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2017-04-06 19:11:36 -06:00
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if (next_w_ptr != q->r_ptr) {
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q->elems[q->w_ptr] = *elem;
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q->w_ptr = next_w_ptr;
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return 1;
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}
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2017-05-16 22:33:28 -06:00
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puts("push failed!\n");
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2017-04-06 19:11:36 -06:00
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return 0;
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}
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// ***************************** serial port queues *****************************
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2017-05-16 22:33:28 -06:00
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#define FIFO_SIZE 0x100
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2017-04-06 19:11:36 -06:00
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typedef struct uart_ring {
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uint8_t w_ptr_tx;
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uint8_t r_ptr_tx;
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uint8_t elems_tx[FIFO_SIZE];
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uint8_t w_ptr_rx;
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uint8_t r_ptr_rx;
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uint8_t elems_rx[FIFO_SIZE];
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USART_TypeDef *uart;
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void (*callback)(struct uart_ring*);
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} uart_ring;
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2017-06-12 01:53:18 -06:00
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int getc(uart_ring *q, char *elem);
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int putc(uart_ring *q, char elem);
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2017-04-06 19:11:36 -06:00
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// esp = USART1
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uart_ring esp_ring = { .w_ptr_tx = 0, .r_ptr_tx = 0,
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.w_ptr_rx = 0, .r_ptr_rx = 0,
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.uart = USART1 };
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// lin1, K-LINE = UART5
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// lin2, L-LINE = USART3
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uart_ring lin1_ring = { .w_ptr_tx = 0, .r_ptr_tx = 0,
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.w_ptr_rx = 0, .r_ptr_rx = 0,
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.uart = UART5 };
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uart_ring lin2_ring = { .w_ptr_tx = 0, .r_ptr_tx = 0,
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.w_ptr_rx = 0, .r_ptr_rx = 0,
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.uart = USART3 };
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// debug = USART2
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void debug_ring_callback(uart_ring *ring);
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uart_ring debug_ring = { .w_ptr_tx = 0, .r_ptr_tx = 0,
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.w_ptr_rx = 0, .r_ptr_rx = 0,
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.uart = USART2,
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.callback = debug_ring_callback};
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uart_ring *get_ring_by_number(int a) {
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switch(a) {
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case 0:
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return &debug_ring;
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case 1:
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return &esp_ring;
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case 2:
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return &lin1_ring;
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case 3:
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return &lin2_ring;
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default:
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return NULL;
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}
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}
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2017-04-25 20:36:01 -06:00
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void accord_framing_callback(uart_ring *q) {
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uint8_t r_ptr_rx_tmp = q->r_ptr_rx;
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int sof1 = -1;
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int sof2 = -1;
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int i;
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2017-05-01 23:59:10 -06:00
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char junk;
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2017-04-25 21:23:05 -06:00
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int jlen = 0;
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int plen = 0;
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2017-04-25 20:36:01 -06:00
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while (q->w_ptr_rx != r_ptr_rx_tmp) {
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if ((q->elems_rx[r_ptr_rx_tmp] & 0x80) == 0) {
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if (sof1 == -1) {
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sof1 = r_ptr_rx_tmp;
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} else {
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sof2 = r_ptr_rx_tmp;
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break;
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}
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}
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2017-04-25 21:23:05 -06:00
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if (sof1 != -1) {
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plen++;
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} else {
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jlen++;
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}
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2017-04-25 20:36:01 -06:00
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r_ptr_rx_tmp++;
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}
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2017-06-12 01:53:18 -06:00
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2017-04-25 20:36:01 -06:00
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// drop until SOF1
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if (sof1 != -1) {
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2017-04-25 21:23:05 -06:00
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for (i = 0; i < jlen; i++) getc(q, &junk);
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2017-04-25 20:36:01 -06:00
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}
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if (sof2 != -1) {
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2017-04-25 21:23:05 -06:00
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//puth(sof1); puts(" "); puth(sof2); puts("\n");
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if (plen > 8) {
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2017-04-25 20:36:01 -06:00
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// drop oversized packet
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2017-04-25 21:23:05 -06:00
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for (i = 0; i < plen; i++) getc(q, &junk);
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2017-04-25 20:36:01 -06:00
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} else {
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// packet received
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CAN_FIFOMailBox_TypeDef to_push;
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to_push.RIR = 0;
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2017-04-25 21:23:05 -06:00
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to_push.RDTR = plen;
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2017-04-25 20:36:01 -06:00
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to_push.RDLR = 0;
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to_push.RDHR = 0;
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// 8 is K-line, 9 is L-line
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if (q->uart == UART5) {
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to_push.RDTR |= 8 << 4;
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} else if (q->uart == USART3) {
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to_push.RDTR |= 9 << 4;
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}
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// get data from queue
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2017-04-25 21:23:05 -06:00
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for (i = 0; i < plen; i++) {
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2017-05-01 23:59:10 -06:00
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getc(q, &(((char*)(&to_push.RDLR))[i]));
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2017-04-25 20:36:01 -06:00
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}
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push(&can_rx_q, &to_push);
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}
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}
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}
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2017-04-06 19:11:36 -06:00
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void debug_ring_callback(uart_ring *ring) {
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char rcv;
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while (getc(ring, &rcv)) {
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putc(ring, rcv);
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// jump to DFU flash
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if (rcv == 'z') {
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enter_bootloader_mode = ENTER_BOOTLOADER_MAGIC;
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NVIC_SystemReset();
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}
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2017-04-17 19:17:34 -06:00
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if (rcv == 'x') {
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// normal reset
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NVIC_SystemReset();
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}
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2017-04-06 19:11:36 -06:00
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}
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}
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// ***************************** serial port *****************************
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void uart_ring_process(uart_ring *q) {
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// TODO: check if external serial is connected
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int sr = q->uart->SR;
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if (q->w_ptr_tx != q->r_ptr_tx) {
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if (sr & USART_SR_TXE) {
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q->uart->DR = q->elems_tx[q->r_ptr_tx];
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q->r_ptr_tx += 1;
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} else {
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// push on interrupt later
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q->uart->CR1 |= USART_CR1_TXEIE;
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}
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} else {
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// nothing to send
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q->uart->CR1 &= ~USART_CR1_TXEIE;
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}
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if (sr & USART_SR_RXNE) {
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uint8_t c = q->uart->DR; // TODO: can drop packets
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uint8_t next_w_ptr = q->w_ptr_rx + 1;
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if (next_w_ptr != q->r_ptr_rx) {
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q->elems_rx[q->w_ptr_rx] = c;
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q->w_ptr_rx = next_w_ptr;
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if (q->callback) q->callback(q);
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}
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}
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}
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// interrupt boilerplate
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void USART1_IRQHandler(void) {
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NVIC_DisableIRQ(USART1_IRQn);
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uart_ring_process(&esp_ring);
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NVIC_EnableIRQ(USART1_IRQn);
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}
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void USART2_IRQHandler(void) {
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NVIC_DisableIRQ(USART2_IRQn);
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uart_ring_process(&debug_ring);
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NVIC_EnableIRQ(USART2_IRQn);
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}
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void USART3_IRQHandler(void) {
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NVIC_DisableIRQ(USART3_IRQn);
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uart_ring_process(&lin2_ring);
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NVIC_EnableIRQ(USART3_IRQn);
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}
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void UART5_IRQHandler(void) {
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NVIC_DisableIRQ(UART5_IRQn);
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uart_ring_process(&lin1_ring);
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NVIC_EnableIRQ(UART5_IRQn);
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}
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2017-06-12 01:53:18 -06:00
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int getc(uart_ring *q, char *elem) {
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2017-04-06 19:11:36 -06:00
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if (q->w_ptr_rx != q->r_ptr_rx) {
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*elem = q->elems_rx[q->r_ptr_rx];
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q->r_ptr_rx += 1;
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return 1;
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}
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return 0;
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}
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2017-06-12 01:53:18 -06:00
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int injectc(uart_ring *q, char elem) {
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2017-04-06 19:11:36 -06:00
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uint8_t next_w_ptr = q->w_ptr_rx + 1;
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int ret = 0;
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if (next_w_ptr != q->r_ptr_rx) {
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q->elems_rx[q->w_ptr_rx] = elem;
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q->w_ptr_rx = next_w_ptr;
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ret = 1;
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}
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return ret;
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}
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2017-06-12 01:53:18 -06:00
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int putc(uart_ring *q, char elem) {
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2017-04-06 19:11:36 -06:00
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uint8_t next_w_ptr = q->w_ptr_tx + 1;
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int ret = 0;
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if (next_w_ptr != q->r_ptr_tx) {
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q->elems_tx[q->w_ptr_tx] = elem;
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q->w_ptr_tx = next_w_ptr;
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ret = 1;
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}
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uart_ring_process(q);
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return ret;
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}
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// ********************* includes *********************
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#include "libc.h"
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2017-04-17 14:57:34 -06:00
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#include "gpio.h"
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#include "uart.h"
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2017-04-06 19:11:36 -06:00
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#include "adc.h"
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#include "timer.h"
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#include "usb.h"
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#include "can.h"
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#include "spi.h"
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void safety_rx_hook(CAN_FIFOMailBox_TypeDef *to_push);
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2017-05-01 23:46:12 -06:00
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int safety_tx_hook(CAN_FIFOMailBox_TypeDef *to_send, int hardwired);
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int safety_tx_lin_hook(int lin_num, uint8_t *data, int len, int hardwired);
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2017-05-01 21:22:19 -06:00
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#ifdef PANDA_SAFETY
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#include "panda_safety.h"
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#else
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2017-04-06 19:11:36 -06:00
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#include "honda_safety.h"
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2017-05-01 21:22:19 -06:00
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#endif
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2017-04-06 19:11:36 -06:00
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// ***************************** CAN *****************************
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void process_can(CAN_TypeDef *CAN, can_ring *can_q, int can_number) {
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#ifdef DEBUG
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puts("process CAN TX\n");
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#endif
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// add successfully transmitted message to my fifo
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if ((CAN->TSR & CAN_TSR_TXOK0) == CAN_TSR_TXOK0) {
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CAN_FIFOMailBox_TypeDef to_push;
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|
|
to_push.RIR = CAN->sTxMailBox[0].TIR;
|
|
|
|
to_push.RDTR = (CAN->sTxMailBox[0].TDTR & 0xFFFF000F) | ((can_number+2) << 4);
|
|
|
|
to_push.RDLR = CAN->sTxMailBox[0].TDLR;
|
|
|
|
to_push.RDHR = CAN->sTxMailBox[0].TDHR;
|
|
|
|
push(&can_rx_q, &to_push);
|
|
|
|
}
|
|
|
|
|
|
|
|
// check for empty mailbox
|
|
|
|
CAN_FIFOMailBox_TypeDef to_send;
|
|
|
|
if ((CAN->TSR & CAN_TSR_TME0) == CAN_TSR_TME0) {
|
|
|
|
if (pop(can_q, &to_send)) {
|
|
|
|
// only send if we have received a packet
|
|
|
|
CAN->sTxMailBox[0].TDLR = to_send.RDLR;
|
|
|
|
CAN->sTxMailBox[0].TDHR = to_send.RDHR;
|
|
|
|
CAN->sTxMailBox[0].TDTR = to_send.RDTR;
|
|
|
|
CAN->sTxMailBox[0].TIR = to_send.RIR;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// clear interrupt
|
|
|
|
CAN->TSR |= CAN_TSR_RQCP0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// send more, possible for these to not trigger?
|
|
|
|
|
|
|
|
|
|
|
|
void CAN1_TX_IRQHandler() {
|
|
|
|
process_can(CAN1, &can_tx1_q, can_numbering[0]);
|
|
|
|
}
|
|
|
|
|
|
|
|
void CAN2_TX_IRQHandler() {
|
|
|
|
process_can(CAN2, &can_tx2_q, can_numbering[1]);
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CAN3
|
|
|
|
void CAN3_TX_IRQHandler() {
|
|
|
|
process_can(CAN3, &can_tx3_q, can_numbering[2]);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2017-05-26 22:38:39 -06:00
|
|
|
void send_can(CAN_FIFOMailBox_TypeDef *to_push, int flags);
|
|
|
|
|
2017-04-06 19:11:36 -06:00
|
|
|
// CAN receive handlers
|
|
|
|
// blink blue when we are receiving CAN messages
|
2017-05-26 22:38:39 -06:00
|
|
|
void can_rx(CAN_TypeDef *CAN, int can_index) {
|
|
|
|
int can_number = can_numbering[can_index];
|
2017-04-06 19:11:36 -06:00
|
|
|
while (CAN->RF0R & CAN_RF0R_FMP0) {
|
|
|
|
// can is live
|
|
|
|
pending_can_live = 1;
|
|
|
|
|
|
|
|
// add to my fifo
|
|
|
|
CAN_FIFOMailBox_TypeDef to_push;
|
|
|
|
to_push.RIR = CAN->sFIFOMailBox[0].RIR;
|
2017-05-26 22:38:39 -06:00
|
|
|
to_push.RDTR = CAN->sFIFOMailBox[0].RDTR;
|
2017-04-06 19:11:36 -06:00
|
|
|
to_push.RDLR = CAN->sFIFOMailBox[0].RDLR;
|
|
|
|
to_push.RDHR = CAN->sFIFOMailBox[0].RDHR;
|
|
|
|
|
2017-05-26 22:38:39 -06:00
|
|
|
// forwarding (panda only)
|
|
|
|
#ifdef PANDA
|
|
|
|
if (can_forwarding[can_index] != -1 && can_numbering[can_forwarding[can_index]] != -1) {
|
|
|
|
CAN_FIFOMailBox_TypeDef to_send;
|
|
|
|
to_send.RIR = to_push.RIR | 1; // TXRQ
|
|
|
|
to_send.RDTR = to_push.RDTR;
|
|
|
|
to_send.RDLR = to_push.RDLR;
|
|
|
|
to_send.RDHR = to_push.RDHR;
|
|
|
|
send_can(&to_send, can_numbering[can_forwarding[can_index]]);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
// modify RDTR for our API
|
|
|
|
to_push.RDTR = (to_push.RDTR & 0xFFFF000F) | (can_number << 4);
|
|
|
|
|
2017-04-06 19:11:36 -06:00
|
|
|
safety_rx_hook(&to_push);
|
|
|
|
|
2017-05-16 11:33:50 -06:00
|
|
|
#ifdef PANDA
|
|
|
|
set_led(LED_GREEN, 1);
|
|
|
|
#endif
|
2017-04-06 19:11:36 -06:00
|
|
|
push(&can_rx_q, &to_push);
|
|
|
|
|
|
|
|
// next
|
|
|
|
CAN->RF0R |= CAN_RF0R_RFOM0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void CAN1_RX0_IRQHandler() {
|
|
|
|
//puts("CANRX1");
|
|
|
|
//delay(10000);
|
2017-05-26 22:38:39 -06:00
|
|
|
can_rx(CAN1, 0);
|
2017-04-06 19:11:36 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
void CAN2_RX0_IRQHandler() {
|
|
|
|
//puts("CANRX0");
|
|
|
|
//delay(10000);
|
2017-05-26 22:38:39 -06:00
|
|
|
can_rx(CAN2, 1);
|
2017-04-06 19:11:36 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CAN3
|
|
|
|
void CAN3_RX0_IRQHandler() {
|
|
|
|
//puts("CANRX0");
|
|
|
|
//delay(10000);
|
2017-05-26 22:38:39 -06:00
|
|
|
can_rx(CAN3, 2);
|
2017-04-06 19:11:36 -06:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
void CAN1_SCE_IRQHandler() {
|
|
|
|
//puts("CAN1_SCE\n");
|
|
|
|
can_sce(CAN1);
|
|
|
|
}
|
|
|
|
|
|
|
|
void CAN2_SCE_IRQHandler() {
|
|
|
|
//puts("CAN2_SCE\n");
|
|
|
|
can_sce(CAN2);
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CAN3
|
|
|
|
void CAN3_SCE_IRQHandler() {
|
|
|
|
//puts("CAN3_SCE\n");
|
|
|
|
can_sce(CAN3);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
|
|
// ***************************** USB port *****************************
|
|
|
|
|
|
|
|
int get_health_pkt(void *dat) {
|
|
|
|
struct __attribute__((packed)) {
|
|
|
|
uint32_t voltage;
|
|
|
|
uint32_t current;
|
|
|
|
uint8_t started;
|
|
|
|
uint8_t controls_allowed;
|
|
|
|
uint8_t gas_interceptor_detected;
|
|
|
|
uint8_t started_signal_detected;
|
|
|
|
uint8_t started_alt;
|
|
|
|
} *health = dat;
|
|
|
|
health->voltage = adc_get(ADCCHAN_VOLTAGE);
|
|
|
|
#ifdef ENABLE_CURRENT_SENSOR
|
|
|
|
health->current = adc_get(ADCCHAN_CURRENT);
|
|
|
|
#else
|
|
|
|
health->current = 0;
|
|
|
|
#endif
|
|
|
|
health->started = started;
|
|
|
|
|
|
|
|
#ifdef PANDA
|
|
|
|
health->started_alt = (GPIOA->IDR & (1 << 1)) == 0;
|
|
|
|
#else
|
|
|
|
health->started_alt = 0;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
health->controls_allowed = controls_allowed;
|
|
|
|
|
|
|
|
health->gas_interceptor_detected = gas_interceptor_detected;
|
|
|
|
health->started_signal_detected = started_signal_detected;
|
|
|
|
return sizeof(*health);
|
|
|
|
}
|
|
|
|
|
|
|
|
void set_fan_speed(int fan_speed) {
|
|
|
|
TIM3->CCR3 = fan_speed;
|
|
|
|
}
|
|
|
|
|
2017-05-01 23:46:12 -06:00
|
|
|
int usb_cb_ep1_in(uint8_t *usbdata, int len, int hardwired) {
|
2017-04-18 08:34:56 -06:00
|
|
|
CAN_FIFOMailBox_TypeDef *reply = (CAN_FIFOMailBox_TypeDef *)usbdata;;
|
2017-04-06 19:11:36 -06:00
|
|
|
|
|
|
|
int ilen = 0;
|
|
|
|
while (ilen < min(len/0x10, 4) && pop(&can_rx_q, &reply[ilen])) ilen++;
|
|
|
|
|
2017-04-17 19:17:34 -06:00
|
|
|
return ilen*0x10;
|
2017-04-06 19:11:36 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
// send on serial, first byte to select
|
2017-05-01 23:46:12 -06:00
|
|
|
void usb_cb_ep2_out(uint8_t *usbdata, int len, int hardwired) {
|
2017-04-06 19:11:36 -06:00
|
|
|
int i;
|
|
|
|
if (len == 0) return;
|
|
|
|
uart_ring *ur = get_ring_by_number(usbdata[0]);
|
|
|
|
if (!ur) return;
|
2017-05-01 23:46:12 -06:00
|
|
|
if ((usbdata[0] < 2) || safety_tx_lin_hook(usbdata[0]-2, usbdata+1, len-1, hardwired)) {
|
2017-05-01 21:22:19 -06:00
|
|
|
for (i = 1; i < len; i++) while (!putc(ur, usbdata[i]));
|
|
|
|
}
|
2017-04-06 19:11:36 -06:00
|
|
|
}
|
|
|
|
|
2017-05-26 22:38:39 -06:00
|
|
|
void send_can(CAN_FIFOMailBox_TypeDef *to_push, int flags) {
|
|
|
|
int i;
|
|
|
|
CAN_TypeDef *CAN;
|
|
|
|
can_ring *can_q;
|
|
|
|
if (flags == can_numbering[0]) {
|
|
|
|
CAN = CAN1;
|
|
|
|
can_q = &can_tx1_q;
|
|
|
|
} else if (flags == can_numbering[1]) {
|
|
|
|
CAN = CAN2;
|
|
|
|
can_q = &can_tx2_q;
|
|
|
|
#ifdef CAN3
|
|
|
|
} else if (flags == can_numbering[2]) {
|
|
|
|
CAN = CAN3;
|
|
|
|
can_q = &can_tx3_q;
|
|
|
|
#endif
|
|
|
|
} else if (flags == 8 || flags == 9) {
|
|
|
|
// fake LIN as CAN
|
|
|
|
uart_ring *lin_ring = (flags == 8) ? &lin1_ring : &lin2_ring;
|
|
|
|
for (i = 0; i < min(8, to_push->RDTR & 0xF); i++) {
|
|
|
|
putc(lin_ring, ((uint8_t*)&to_push->RDLR)[i]);
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
} else {
|
|
|
|
// no crash
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// add CAN packet to send queue
|
|
|
|
// bus number isn't passed through
|
|
|
|
to_push->RDTR &= 0xF;
|
|
|
|
push(can_q, to_push);
|
|
|
|
|
|
|
|
// flags = can_number
|
|
|
|
process_can(CAN, can_q, flags);
|
|
|
|
}
|
|
|
|
|
2017-04-06 19:11:36 -06:00
|
|
|
// send on CAN
|
2017-05-01 23:46:12 -06:00
|
|
|
void usb_cb_ep3_out(uint8_t *usbdata, int len, int hardwired) {
|
2017-04-06 19:11:36 -06:00
|
|
|
int dpkt = 0;
|
|
|
|
for (dpkt = 0; dpkt < len; dpkt += 0x10) {
|
|
|
|
uint32_t *tf = (uint32_t*)(&usbdata[dpkt]);
|
|
|
|
|
2017-04-28 10:56:01 -06:00
|
|
|
// make a copy
|
2017-04-06 19:11:36 -06:00
|
|
|
CAN_FIFOMailBox_TypeDef to_push;
|
|
|
|
to_push.RDHR = tf[3];
|
|
|
|
to_push.RDLR = tf[2];
|
2017-04-28 10:56:01 -06:00
|
|
|
to_push.RDTR = tf[1];
|
2017-04-06 19:11:36 -06:00
|
|
|
to_push.RIR = tf[0];
|
|
|
|
|
2017-04-28 10:56:01 -06:00
|
|
|
int flags = (to_push.RDTR >> 4) & 0xF;
|
2017-05-01 23:46:12 -06:00
|
|
|
if (safety_tx_hook(&to_push, hardwired)) {
|
2017-05-26 22:38:39 -06:00
|
|
|
send_can(&to_push, flags);
|
2017-04-28 10:56:01 -06:00
|
|
|
}
|
2017-04-06 19:11:36 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void usb_cb_enumeration_complete() {
|
|
|
|
// power down the ESP
|
|
|
|
// this doesn't work and makes the board unflashable
|
|
|
|
// because the ESP spews shit on serial on startup
|
|
|
|
//GPIOC->ODR &= ~(1 << 14);
|
|
|
|
did_usb_enumerate = 1;
|
|
|
|
}
|
|
|
|
|
2017-05-01 23:46:12 -06:00
|
|
|
int usb_cb_control_msg(USB_Setup_TypeDef *setup, uint8_t *resp, int hardwired) {
|
2017-04-06 19:11:36 -06:00
|
|
|
int resp_len = 0;
|
|
|
|
uart_ring *ur = NULL;
|
|
|
|
int i;
|
2017-04-17 19:17:34 -06:00
|
|
|
switch (setup->b.bRequest) {
|
2017-04-28 17:56:40 -06:00
|
|
|
case 0xd0:
|
|
|
|
// fetch serial number
|
|
|
|
#ifdef PANDA
|
2017-05-01 23:59:10 -06:00
|
|
|
// addresses are OTP
|
2017-04-28 18:49:55 -06:00
|
|
|
if (setup->b.wValue.w == 1) {
|
2017-05-01 23:59:10 -06:00
|
|
|
memcpy(resp, (void *)0x1fff79c0, 0x10);
|
2017-04-28 18:49:55 -06:00
|
|
|
resp_len = 0x10;
|
|
|
|
} else {
|
2017-05-01 23:59:10 -06:00
|
|
|
memcpy(resp, (void *)0x1fff79e0, 0x20);
|
2017-04-28 18:49:55 -06:00
|
|
|
resp_len = 0x20;
|
|
|
|
}
|
2017-04-28 17:56:40 -06:00
|
|
|
#endif
|
|
|
|
break;
|
2017-04-06 19:11:36 -06:00
|
|
|
case 0xd1:
|
2017-04-28 10:45:58 -06:00
|
|
|
if (hardwired) {
|
|
|
|
enter_bootloader_mode = ENTER_BOOTLOADER_MAGIC;
|
|
|
|
NVIC_SystemReset();
|
|
|
|
}
|
2017-04-06 19:11:36 -06:00
|
|
|
break;
|
|
|
|
case 0xd2:
|
|
|
|
resp_len = get_health_pkt(resp);
|
|
|
|
break;
|
|
|
|
case 0xd3:
|
2017-04-17 19:17:34 -06:00
|
|
|
set_fan_speed(setup->b.wValue.w);
|
2017-04-06 19:11:36 -06:00
|
|
|
break;
|
|
|
|
case 0xd6: // GET_VERSION
|
2017-04-17 19:17:34 -06:00
|
|
|
// assert(sizeof(gitversion) <= MAX_RESP_LEN);
|
|
|
|
memcpy(resp, gitversion, sizeof(gitversion));
|
|
|
|
resp_len = sizeof(gitversion);
|
2017-04-06 19:11:36 -06:00
|
|
|
break;
|
|
|
|
case 0xd8: // RESET
|
|
|
|
NVIC_SystemReset();
|
|
|
|
break;
|
2017-04-26 13:38:33 -06:00
|
|
|
case 0xd9: // ESP SET POWER
|
|
|
|
if (setup->b.wValue.w == 1) {
|
|
|
|
// on
|
|
|
|
GPIOC->ODR |= (1 << 14);
|
|
|
|
} else {
|
|
|
|
// off
|
|
|
|
GPIOC->ODR &= ~(1 << 14);
|
|
|
|
}
|
|
|
|
break;
|
2017-04-06 19:11:36 -06:00
|
|
|
case 0xda: // ESP RESET
|
|
|
|
// pull low for ESP boot mode
|
2017-04-17 19:17:34 -06:00
|
|
|
if (setup->b.wValue.w == 1) {
|
2017-04-06 19:11:36 -06:00
|
|
|
GPIOC->ODR &= ~(1 << 5);
|
|
|
|
}
|
|
|
|
|
|
|
|
// do ESP reset
|
|
|
|
GPIOC->ODR &= ~(1 << 14);
|
|
|
|
delay(1000000);
|
|
|
|
GPIOC->ODR |= (1 << 14);
|
|
|
|
delay(1000000);
|
|
|
|
|
|
|
|
// reset done, no more boot mode
|
|
|
|
// TODO: ESP doesn't seem to listen here
|
2017-04-17 19:17:34 -06:00
|
|
|
if (setup->b.wValue.w == 1) {
|
2017-04-06 19:11:36 -06:00
|
|
|
GPIOC->ODR |= (1 << 5);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 0xdb: // toggle GMLAN
|
2017-06-09 15:11:37 -06:00
|
|
|
if (setup->b.wIndex.w == 3) {
|
|
|
|
set_can_mode(2, 0);
|
|
|
|
set_can_mode(3, setup->b.wValue.w);
|
|
|
|
} else {
|
|
|
|
set_can_mode(3, 0);
|
|
|
|
set_can_mode(2, setup->b.wValue.w);
|
|
|
|
}
|
2017-04-06 19:11:36 -06:00
|
|
|
break;
|
2017-05-02 00:40:49 -06:00
|
|
|
case 0xdc: // set controls allowed
|
|
|
|
controls_allowed = setup->b.wValue.w == 0x1337;
|
2017-05-29 22:33:05 -06:00
|
|
|
// take CAN out of SILM, careful with speed!
|
|
|
|
can_init(CAN1, 0);
|
|
|
|
can_init(CAN2, 0);
|
|
|
|
#ifdef CAN3
|
|
|
|
can_init(CAN3, 0);
|
|
|
|
#endif
|
2017-05-02 00:40:49 -06:00
|
|
|
break;
|
2017-05-26 22:38:39 -06:00
|
|
|
case 0xdd: // enable can forwarding
|
|
|
|
if (setup->b.wValue.w != 0 && setup->b.wValue.w <= CAN_MAX) {
|
|
|
|
// 0 sets it to -1
|
|
|
|
if (setup->b.wIndex.w <= CAN_MAX) {
|
|
|
|
can_forwarding[setup->b.wValue.w-1] = setup->b.wIndex.w-1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
2017-04-06 19:11:36 -06:00
|
|
|
case 0xe0: // uart read
|
2017-04-17 19:17:34 -06:00
|
|
|
ur = get_ring_by_number(setup->b.wValue.w);
|
2017-04-06 19:11:36 -06:00
|
|
|
if (!ur) break;
|
2017-04-17 19:17:34 -06:00
|
|
|
// read
|
2017-05-01 23:59:10 -06:00
|
|
|
while (resp_len < min(setup->b.wLength.w, MAX_RESP_LEN) && getc(ur, (char*)&resp[resp_len])) {
|
2017-04-17 19:17:34 -06:00
|
|
|
++resp_len;
|
2017-04-06 19:11:36 -06:00
|
|
|
}
|
2017-04-18 02:12:04 -06:00
|
|
|
break;
|
2017-04-06 19:11:36 -06:00
|
|
|
case 0xe1: // uart set baud rate
|
2017-04-17 19:17:34 -06:00
|
|
|
ur = get_ring_by_number(setup->b.wValue.w);
|
2017-04-25 19:06:44 -06:00
|
|
|
if (!ur) break;
|
2017-04-17 19:17:34 -06:00
|
|
|
uart_set_baud(ur->uart, setup->b.wIndex.w);
|
2017-04-06 19:11:36 -06:00
|
|
|
break;
|
2017-04-25 16:16:23 -06:00
|
|
|
case 0xe2: // uart set parity
|
|
|
|
ur = get_ring_by_number(setup->b.wValue.w);
|
2017-04-25 19:06:44 -06:00
|
|
|
if (!ur) break;
|
2017-04-25 16:16:23 -06:00
|
|
|
switch (setup->b.wIndex.w) {
|
|
|
|
case 0:
|
2017-04-26 19:39:26 -06:00
|
|
|
// disable parity, 8-bit
|
|
|
|
ur->uart->CR1 &= ~(USART_CR1_PCE | USART_CR1_M);
|
2017-04-25 16:16:23 -06:00
|
|
|
break;
|
|
|
|
case 1:
|
2017-04-26 19:39:26 -06:00
|
|
|
// even parity, 9-bit
|
2017-04-25 16:16:23 -06:00
|
|
|
ur->uart->CR1 &= ~USART_CR1_PS;
|
2017-04-26 19:39:26 -06:00
|
|
|
ur->uart->CR1 |= USART_CR1_PCE | USART_CR1_M;
|
2017-04-25 16:16:23 -06:00
|
|
|
break;
|
|
|
|
case 2:
|
2017-04-26 19:39:26 -06:00
|
|
|
// odd parity, 9-bit
|
2017-04-25 16:16:23 -06:00
|
|
|
ur->uart->CR1 |= USART_CR1_PS;
|
2017-04-26 19:39:26 -06:00
|
|
|
ur->uart->CR1 |= USART_CR1_PCE | USART_CR1_M;
|
2017-04-25 16:16:23 -06:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
2017-04-25 20:36:01 -06:00
|
|
|
case 0xe3: // uart install accord framing callback
|
|
|
|
ur = get_ring_by_number(setup->b.wValue.w);
|
|
|
|
if (!ur) break;
|
2017-04-25 21:23:05 -06:00
|
|
|
if (setup->b.wIndex.w == 1) {
|
|
|
|
ur->callback = accord_framing_callback;
|
|
|
|
} else {
|
|
|
|
ur->callback = NULL;
|
|
|
|
}
|
2017-04-25 20:36:01 -06:00
|
|
|
break;
|
2017-05-30 00:03:11 -06:00
|
|
|
case 0xe4: // uart set baud rate extended
|
|
|
|
ur = get_ring_by_number(setup->b.wValue.w);
|
|
|
|
if (!ur) break;
|
|
|
|
uart_set_baud(ur->uart, (int)setup->b.wIndex.w*300);
|
|
|
|
break;
|
2017-04-06 19:11:36 -06:00
|
|
|
case 0xf0: // k-line wValue pulse on uart2
|
2017-04-17 19:17:34 -06:00
|
|
|
if (setup->b.wValue.w == 1) {
|
2017-04-06 19:11:36 -06:00
|
|
|
GPIOC->ODR &= ~(1 << 10);
|
|
|
|
GPIOC->MODER &= ~GPIO_MODER_MODER10_1;
|
|
|
|
GPIOC->MODER |= GPIO_MODER_MODER10_0;
|
|
|
|
} else {
|
|
|
|
GPIOC->ODR &= ~(1 << 12);
|
|
|
|
GPIOC->MODER &= ~GPIO_MODER_MODER12_1;
|
|
|
|
GPIOC->MODER |= GPIO_MODER_MODER12_0;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < 80; i++) {
|
|
|
|
delay(8000);
|
2017-04-17 19:17:34 -06:00
|
|
|
if (setup->b.wValue.w == 1) {
|
2017-04-06 19:11:36 -06:00
|
|
|
GPIOC->ODR |= (1 << 10);
|
|
|
|
GPIOC->ODR &= ~(1 << 10);
|
|
|
|
} else {
|
|
|
|
GPIOC->ODR |= (1 << 12);
|
|
|
|
GPIOC->ODR &= ~(1 << 12);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-04-17 19:17:34 -06:00
|
|
|
if (setup->b.wValue.w == 1) {
|
2017-04-06 19:11:36 -06:00
|
|
|
GPIOC->MODER &= ~GPIO_MODER_MODER10_0;
|
|
|
|
GPIOC->MODER |= GPIO_MODER_MODER10_1;
|
|
|
|
} else {
|
|
|
|
GPIOC->MODER &= ~GPIO_MODER_MODER12_0;
|
|
|
|
GPIOC->MODER |= GPIO_MODER_MODER12_1;
|
|
|
|
}
|
|
|
|
|
|
|
|
delay(140 * 9000);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
puts("NO HANDLER ");
|
2017-04-17 19:17:34 -06:00
|
|
|
puth(setup->b.bRequest);
|
2017-04-06 19:11:36 -06:00
|
|
|
puts("\n");
|
|
|
|
break;
|
|
|
|
}
|
2017-04-17 19:17:34 -06:00
|
|
|
return resp_len;
|
2017-04-06 19:11:36 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void OTG_FS_IRQHandler(void) {
|
|
|
|
NVIC_DisableIRQ(OTG_FS_IRQn);
|
|
|
|
//__disable_irq();
|
|
|
|
usb_irqhandler();
|
|
|
|
//__enable_irq();
|
|
|
|
NVIC_EnableIRQ(OTG_FS_IRQn);
|
|
|
|
}
|
|
|
|
|
|
|
|
void ADC_IRQHandler(void) {
|
|
|
|
puts("ADC_IRQ\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef ENABLE_SPI
|
|
|
|
|
2017-04-18 02:12:04 -06:00
|
|
|
#define SPI_BUF_SIZE 256
|
2017-04-06 19:11:36 -06:00
|
|
|
uint8_t spi_buf[SPI_BUF_SIZE];
|
|
|
|
int spi_buf_count = 0;
|
2017-04-18 02:12:04 -06:00
|
|
|
int spi_total_count = 0;
|
2017-04-18 08:34:56 -06:00
|
|
|
uint8_t spi_tx_buf[0x44];
|
2017-04-18 02:12:04 -06:00
|
|
|
|
|
|
|
void handle_spi(uint8_t *data, int len) {
|
2017-04-18 08:34:56 -06:00
|
|
|
memset(spi_tx_buf, 0xaa, 0x44);
|
|
|
|
// data[0] = endpoint
|
|
|
|
// data[2] = length
|
|
|
|
// data[4:] = data
|
|
|
|
int *resp_len = (int*)spi_tx_buf;
|
|
|
|
*resp_len = 0;
|
|
|
|
switch (data[0]) {
|
|
|
|
case 0:
|
|
|
|
// control transfer
|
2017-05-01 23:46:12 -06:00
|
|
|
*resp_len = usb_cb_control_msg((USB_Setup_TypeDef *)(data+4), spi_tx_buf+4, 0);
|
2017-04-18 08:34:56 -06:00
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
// ep 1, read
|
2017-05-01 23:46:12 -06:00
|
|
|
*resp_len = usb_cb_ep1_in(spi_tx_buf+4, 0x40, 0);
|
2017-04-18 08:34:56 -06:00
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
// ep 2, send serial
|
2017-05-01 23:46:12 -06:00
|
|
|
usb_cb_ep2_out(data+4, data[2], 0);
|
2017-04-18 08:34:56 -06:00
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
// ep 3, send CAN
|
2017-05-01 23:46:12 -06:00
|
|
|
usb_cb_ep3_out(data+4, data[2], 0);
|
2017-04-18 08:34:56 -06:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
spi_tx_dma(spi_tx_buf, 0x44);
|
2017-04-06 19:11:36 -06:00
|
|
|
|
2017-05-03 16:54:47 -06:00
|
|
|
// signal data is ready by driving low
|
|
|
|
// esp must be configured as input by this point
|
|
|
|
GPIOB->MODER &= ~(GPIO_MODER_MODER0);
|
|
|
|
GPIOB->MODER |= GPIO_MODER_MODER0_0;
|
|
|
|
GPIOB->ODR &= ~(GPIO_ODR_ODR_0);
|
|
|
|
}
|
2017-04-06 19:11:36 -06:00
|
|
|
|
2017-04-18 02:12:04 -06:00
|
|
|
// SPI RX
|
|
|
|
void DMA2_Stream2_IRQHandler(void) {
|
|
|
|
// ack
|
|
|
|
DMA2->LIFCR = DMA_LIFCR_CTCIF2;
|
|
|
|
handle_spi(spi_buf, 0x14);
|
|
|
|
}
|
|
|
|
|
|
|
|
// SPI TX
|
2017-04-06 19:11:36 -06:00
|
|
|
void DMA2_Stream3_IRQHandler(void) {
|
|
|
|
// ack
|
|
|
|
DMA2->LIFCR = DMA_LIFCR_CTCIF3;
|
|
|
|
|
2017-05-03 16:54:47 -06:00
|
|
|
// reset handshake back to pull up
|
|
|
|
GPIOB->MODER &= ~(GPIO_MODER_MODER0);
|
|
|
|
GPIOB->PUPDR |= GPIO_PUPDR_PUPDR0_0;
|
2017-04-06 19:11:36 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
void EXTI4_IRQHandler(void) {
|
|
|
|
int pr = EXTI->PR;
|
|
|
|
// SPI CS rising
|
|
|
|
if (pr & (1 << 4)) {
|
2017-04-18 02:12:04 -06:00
|
|
|
spi_total_count = 0;
|
|
|
|
spi_rx_dma(spi_buf, 0x14);
|
2017-04-18 08:34:56 -06:00
|
|
|
//puts("exti4\n");
|
2017-04-06 19:11:36 -06:00
|
|
|
}
|
|
|
|
EXTI->PR = pr;
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
// ***************************** main code *****************************
|
|
|
|
|
|
|
|
void __initialize_hardware_early() {
|
|
|
|
early();
|
|
|
|
}
|
|
|
|
|
|
|
|
int main() {
|
|
|
|
// init devices
|
|
|
|
clock_init();
|
2017-04-17 14:57:34 -06:00
|
|
|
periph_init();
|
|
|
|
|
2017-04-06 19:11:36 -06:00
|
|
|
detect();
|
|
|
|
gpio_init();
|
|
|
|
|
|
|
|
// enable main uart
|
|
|
|
uart_init(USART2, 115200);
|
|
|
|
|
|
|
|
// enable ESP uart
|
|
|
|
uart_init(USART1, 115200);
|
|
|
|
|
|
|
|
// enable LIN
|
|
|
|
uart_init(UART5, 10400);
|
|
|
|
UART5->CR2 |= USART_CR2_LINEN;
|
|
|
|
uart_init(USART3, 10400);
|
|
|
|
USART3->CR2 |= USART_CR2_LINEN;
|
|
|
|
|
|
|
|
/*puts("EXTERNAL");
|
|
|
|
puth(has_external_debug_serial);
|
|
|
|
puts("\n");*/
|
|
|
|
|
|
|
|
// enable USB
|
|
|
|
usb_init();
|
|
|
|
|
2017-05-29 22:33:05 -06:00
|
|
|
// default to silent mode to prevent issues with Ford
|
2017-05-30 10:46:21 -06:00
|
|
|
#ifdef PANDA_SAFETY
|
2017-05-29 22:33:05 -06:00
|
|
|
can_init(CAN1, 1);
|
|
|
|
can_init(CAN2, 1);
|
2017-05-30 10:46:21 -06:00
|
|
|
#ifdef CAN3
|
|
|
|
can_init(CAN3, 1);
|
|
|
|
#endif
|
|
|
|
#else
|
|
|
|
can_init(CAN1, 0);
|
|
|
|
can_init(CAN2, 0);
|
|
|
|
#ifdef CAN3
|
|
|
|
can_init(CAN3, 0);
|
|
|
|
#endif
|
2017-04-06 19:11:36 -06:00
|
|
|
#endif
|
2017-05-30 10:46:21 -06:00
|
|
|
|
2017-04-06 19:11:36 -06:00
|
|
|
adc_init();
|
|
|
|
|
|
|
|
#ifdef ENABLE_SPI
|
|
|
|
spi_init();
|
|
|
|
#endif
|
|
|
|
|
|
|
|
// timer for fan PWM
|
|
|
|
TIM3->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1;
|
|
|
|
TIM3->CCER = TIM_CCER_CC3E;
|
|
|
|
|
|
|
|
// max value of the timer
|
|
|
|
// 64 makes it above the audible range
|
|
|
|
//TIM3->ARR = 64;
|
|
|
|
|
|
|
|
// 10 prescale makes it below the audible range
|
|
|
|
timer_init(TIM3, 10);
|
|
|
|
puth(DBGMCU->IDCODE);
|
|
|
|
|
|
|
|
// set PWM
|
|
|
|
set_fan_speed(65535);
|
|
|
|
|
|
|
|
|
|
|
|
puts("**** INTERRUPTS ON ****\n");
|
|
|
|
__disable_irq();
|
|
|
|
|
|
|
|
// 4 uarts!
|
|
|
|
NVIC_EnableIRQ(USART1_IRQn);
|
|
|
|
NVIC_EnableIRQ(USART2_IRQn);
|
|
|
|
NVIC_EnableIRQ(USART3_IRQn);
|
|
|
|
NVIC_EnableIRQ(UART5_IRQn);
|
|
|
|
|
|
|
|
NVIC_EnableIRQ(OTG_FS_IRQn);
|
|
|
|
NVIC_EnableIRQ(ADC_IRQn);
|
|
|
|
// CAN has so many interrupts!
|
|
|
|
|
|
|
|
NVIC_EnableIRQ(CAN1_TX_IRQn);
|
|
|
|
NVIC_EnableIRQ(CAN1_RX0_IRQn);
|
|
|
|
NVIC_EnableIRQ(CAN1_SCE_IRQn);
|
|
|
|
|
|
|
|
NVIC_EnableIRQ(CAN2_TX_IRQn);
|
|
|
|
NVIC_EnableIRQ(CAN2_RX0_IRQn);
|
|
|
|
NVIC_EnableIRQ(CAN2_SCE_IRQn);
|
|
|
|
|
|
|
|
#ifdef CAN3
|
|
|
|
NVIC_EnableIRQ(CAN3_TX_IRQn);
|
|
|
|
NVIC_EnableIRQ(CAN3_RX0_IRQn);
|
|
|
|
NVIC_EnableIRQ(CAN3_SCE_IRQn);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef ENABLE_SPI
|
2017-04-18 02:12:04 -06:00
|
|
|
NVIC_EnableIRQ(DMA2_Stream2_IRQn);
|
2017-04-06 19:11:36 -06:00
|
|
|
NVIC_EnableIRQ(DMA2_Stream3_IRQn);
|
2017-04-18 02:12:04 -06:00
|
|
|
//NVIC_EnableIRQ(SPI1_IRQn);
|
2017-04-06 19:11:36 -06:00
|
|
|
|
|
|
|
// setup interrupt on falling edge of SPI enable (on PA4)
|
|
|
|
SYSCFG->EXTICR[2] = SYSCFG_EXTICR2_EXTI4_PA;
|
|
|
|
EXTI->IMR = (1 << 4);
|
|
|
|
EXTI->FTSR = (1 << 4);
|
|
|
|
NVIC_EnableIRQ(EXTI4_IRQn);
|
|
|
|
#endif
|
|
|
|
__enable_irq();
|
|
|
|
|
2017-04-27 21:32:16 -06:00
|
|
|
puts("OPTCR: "); puth(FLASH->OPTCR); puts("\n");
|
|
|
|
|
2017-04-06 19:11:36 -06:00
|
|
|
// LED should keep on blinking all the time
|
|
|
|
uint64_t cnt;
|
|
|
|
for (cnt=0;;cnt++) {
|
|
|
|
can_live = pending_can_live;
|
|
|
|
|
|
|
|
// reset this every 16th pass
|
|
|
|
if ((cnt&0xF) == 0) pending_can_live = 0;
|
|
|
|
|
|
|
|
/*#ifdef DEBUG
|
|
|
|
puts("** blink ");
|
|
|
|
puth(can_rx_q.r_ptr); puts(" "); puth(can_rx_q.w_ptr); puts(" ");
|
|
|
|
puth(can_tx1_q.r_ptr); puts(" "); puth(can_tx1_q.w_ptr); puts(" ");
|
|
|
|
puth(can_tx2_q.r_ptr); puts(" "); puth(can_tx2_q.w_ptr); puts("\n");
|
|
|
|
#endif*/
|
|
|
|
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/*puts("voltage: "); puth(adc_get(ADCCHAN_VOLTAGE)); puts(" ");
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puts("current: "); puth(adc_get(ADCCHAN_CURRENT)); puts("\n");*/
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2017-05-16 11:33:50 -06:00
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// set LED to be controls allowed, blue on panda, green on legacy
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#ifdef PANDA
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set_led(LED_BLUE, controls_allowed);
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#else
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set_led(LED_GREEN, controls_allowed);
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#endif
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2017-04-06 19:11:36 -06:00
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// blink the red LED
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set_led(LED_RED, 0);
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delay(2000000);
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set_led(LED_RED, 1);
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delay(2000000);
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2017-05-16 11:33:50 -06:00
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// turn off the green LED, turned on by CAN
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#ifdef PANDA
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set_led(LED_GREEN, 0);
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#endif
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2017-04-06 19:11:36 -06:00
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#ifdef ENABLE_SPI
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2017-04-18 02:12:04 -06:00
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/*if (spi_buf_count > 0) {
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2017-04-06 19:11:36 -06:00
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hexdump(spi_buf, spi_buf_count);
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spi_buf_count = 0;
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2017-04-18 02:12:04 -06:00
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}*/
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2017-04-06 19:11:36 -06:00
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#endif
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// started logic
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#ifdef PANDA
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int started_signal = (GPIOB->IDR & (1 << 12)) == 0;
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#else
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int started_signal = (GPIOC->IDR & (1 << 13)) != 0;
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#endif
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if (started_signal) { started_signal_detected = 1; }
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if (started_signal || (!started_signal_detected && can_live)) {
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started = 1;
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// turn on fan at half speed
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set_fan_speed(32768);
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} else {
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started = 0;
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// turn off fan
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set_fan_speed(0);
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}
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}
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return 0;
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}
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