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remove whitespace (#255)

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dekerr 2019-07-19 22:35:50 -04:00 committed by rbiasini
parent e49d0dbbd6
commit 45d0d286f4
21 changed files with 5229 additions and 5229 deletions
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408
board/inc/stm32f205xx.h
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@ -4,8 +4,8 @@
* @author MCD Application Team
* @version V2.1.2
* @date 29-June-2016
* @brief CMSIS STM32F205xx Device Peripheral Access Layer Header File.
* This file contains :
* @brief CMSIS STM32F205xx Device Peripheral Access Layer Header File.
* This file contains :
* - Data structures and the address mapping for all peripherals
* - Peripherals registers declarations and bits definition
* - Macros to access peripheral’s registers hardware
@ -47,21 +47,21 @@
/** @addtogroup stm32f205xx
* @{
*/
#ifndef __STM32F205xx_H
#define __STM32F205xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/
#define __CM3_REV 0x0200U /*!< Core revision r0p1 */
#define __MPU_PRESENT 1U /*!< STM32F2XX provides an MPU */
@ -71,14 +71,14 @@
/**
* @}
*/
/** @addtogroup Peripheral_interrupt_number_definition
* @{
*/
/**
* @brief STM32F2XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
* @brief STM32F2XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
{
@ -126,7 +126,7 @@ typedef enum
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
@ -134,7 +134,7 @@ typedef enum
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
@ -181,16 +181,16 @@ typedef enum
/** @addtogroup Peripheral_registers_structures
* @{
*/
*/
/**
* @brief Analog to Digital Converter
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
__IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
__IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
@ -220,8 +220,8 @@ typedef struct
} ADC_Common_TypeDef;
/**
* @brief Controller Area Network TxMailBox
/**
* @brief Controller Area Network TxMailBox
*/
typedef struct
@ -232,10 +232,10 @@ typedef struct
__IO uint32_t TDHR; /*!< CAN mailbox data high register */
} CAN_TxMailBox_TypeDef;
/**
* @brief Controller Area Network FIFOMailBox
/**
* @brief Controller Area Network FIFOMailBox
*/
typedef struct
{
__IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
@ -244,20 +244,20 @@ typedef struct
__IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
} CAN_FIFOMailBox_TypeDef;
/**
* @brief Controller Area Network FilterRegister
/**
* @brief Controller Area Network FilterRegister
*/
typedef struct
{
__IO uint32_t FR1; /*!< CAN Filter bank register 1 */
__IO uint32_t FR2; /*!< CAN Filter bank register 1 */
} CAN_FilterRegister_TypeDef;
/**
* @brief Controller Area Network
/**
* @brief Controller Area Network
*/
typedef struct
{
__IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
@ -280,12 +280,12 @@ typedef struct
__IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
uint32_t RESERVED4; /*!< Reserved, 0x218 */
__IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
} CAN_TypeDef;
/**
* @brief CRC calculation unit
/**
* @brief CRC calculation unit
*/
typedef struct
@ -297,7 +297,7 @@ typedef struct
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
} CRC_TypeDef;
/**
/**
* @brief Digital to Analog Converter
*/
@ -319,7 +319,7 @@ typedef struct
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
} DAC_TypeDef;
/**
/**
* @brief Debug MCU
*/
@ -332,7 +332,7 @@ typedef struct
}DBGMCU_TypeDef;
/**
/**
* @brief DMA Controller
*/
@ -355,7 +355,7 @@ typedef struct
} DMA_TypeDef;
/**
/**
* @brief External Interrupt/Event Controller
*/
@ -369,7 +369,7 @@ typedef struct
__IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
} EXTI_TypeDef;
/**
/**
* @brief FLASH Registers
*/
@ -384,28 +384,28 @@ typedef struct
} FLASH_TypeDef;
/**
/**
* @brief Flexible Static Memory Controller
*/
typedef struct
{
__IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
} FSMC_Bank1_TypeDef;
__IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
} FSMC_Bank1_TypeDef;
/**
/**
* @brief Flexible Static Memory Controller Bank1E
*/
typedef struct
{
__IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
} FSMC_Bank1E_TypeDef;
/**
/**
* @brief Flexible Static Memory Controller Bank2
*/
typedef struct
{
__IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
@ -424,10 +424,10 @@ typedef struct
__IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
} FSMC_Bank2_3_TypeDef;
/**
/**
* @brief Flexible Static Memory Controller Bank4
*/
typedef struct
{
__IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
@ -435,10 +435,10 @@ typedef struct
__IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
__IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
__IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
} FSMC_Bank4_TypeDef;
} FSMC_Bank4_TypeDef;
/**
/**
* @brief General Purpose I/O
*/
@ -455,20 +455,20 @@ typedef struct
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;
/**
/**
* @brief System configuration controller
*/
typedef struct
{
__IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
__IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
__IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
} SYSCFG_TypeDef;
/**
/**
* @brief Inter-integrated Circuit Interface
*/
@ -485,7 +485,7 @@ typedef struct
__IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
} I2C_TypeDef;
/**
/**
* @brief Independent WATCHDOG
*/
@ -497,7 +497,7 @@ typedef struct
__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
} IWDG_TypeDef;
/**
/**
* @brief Power Control
*/
@ -507,7 +507,7 @@ typedef struct
__IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
} PWR_TypeDef;
/**
/**
* @brief Reset and Clock Control
*/
@ -546,7 +546,7 @@ typedef struct
} RCC_TypeDef;
/**
/**
* @brief Real-Time Clock
*/
@ -595,7 +595,7 @@ typedef struct
} RTC_TypeDef;
/**
/**
* @brief SD host Interface
*/
@ -623,7 +623,7 @@ typedef struct
__IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
} SDIO_TypeDef;
/**
/**
* @brief Serial Peripheral Interface
*/
@ -640,7 +640,7 @@ typedef struct
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
} SPI_TypeDef;
/**
/**
* @brief TIM
*/
@ -669,10 +669,10 @@ typedef struct
__IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
} TIM_TypeDef;
/**
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
__IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
@ -684,7 +684,7 @@ typedef struct
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
} USART_TypeDef;
/**
/**
* @brief Window WATCHDOG
*/
@ -696,11 +696,11 @@ typedef struct
} WWDG_TypeDef;
/**
/**
* @brief RNG
*/
typedef struct
typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
@ -708,8 +708,8 @@ typedef struct
} RNG_TypeDef;
/**
/**
* @brief __USB_OTG_Core_register
*/
typedef struct
@ -737,10 +737,10 @@ USB_OTG_GlobalTypeDef;
/**
/**
* @brief __device_Registers
*/
typedef struct
typedef struct
{
__IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
__IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
@ -757,19 +757,19 @@ typedef struct
__IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
__IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
__IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
__IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
__IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
__IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
__IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
__IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
}
USB_OTG_DeviceTypeDef;
/**
/**
* @brief __IN_Endpoint-Specific_Register
*/
typedef struct
typedef struct
{
__IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
@ -783,10 +783,10 @@ typedef struct
USB_OTG_INEndpointTypeDef;
/**
/**
* @brief __OUT_Endpoint-Specific_Registers
*/
typedef struct
typedef struct
{
__IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
@ -799,10 +799,10 @@ typedef struct
USB_OTG_OUTEndpointTypeDef;
/**
/**
* @brief __Host_Mode_Register_Structures
*/
typedef struct
typedef struct
{
__IO uint32_t HCFG; /* Host Configuration Register 400h*/
__IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
@ -815,7 +815,7 @@ typedef struct
USB_OTG_HostTypeDef;
/**
/**
* @brief __Host_Channel_Specific_Registers
*/
typedef struct
@ -830,8 +830,8 @@ typedef struct
}
USB_OTG_HostChannelTypeDef;
/**
/**
* @brief Peripheral_memory_map
*/
#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
@ -965,10 +965,10 @@ USB_OTG_HostChannelTypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_declaration
* @{
*/
*/
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
@ -1003,7 +1003,7 @@ USB_OTG_HostChannelTypeDef;
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
@ -1038,7 +1038,7 @@ USB_OTG_HostChannelTypeDef;
#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
#define RNG ((RNG_TypeDef *) RNG_BASE)
#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
@ -1057,11 +1057,11 @@ USB_OTG_HostChannelTypeDef;
/** @addtogroup Exported_constants
* @{
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/******************************************************************************/
/* Peripheral Registers_Bits_Definition */
/******************************************************************************/
@ -1104,7 +1104,7 @@ USB_OTG_HostChannelTypeDef;
#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
/******************* Bit definition for ADC_CR2 register ********************/
#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
@ -1337,7 +1337,7 @@ USB_OTG_HostChannelTypeDef;
#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
/******************* Bit definition for ADC_JSQR register *******************/
#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
@ -1407,22 +1407,22 @@ USB_OTG_HostChannelTypeDef;
#define ADC_CSR_DOVR3 ADC_CSR_OVR3
/******************* Bit definition for ADC_CCR register ********************/
#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
@ -1603,7 +1603,7 @@ USB_OTG_HostChannelTypeDef;
#define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
#define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
/******************* Bit definition for CAN_TDT2R register ******************/
/******************* Bit definition for CAN_TDT2R register ******************/
#define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
#define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
#define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
@ -2925,7 +2925,7 @@ USB_OTG_HostChannelTypeDef;
#define DMA_SxNDT_14 0x00004000U
#define DMA_SxNDT_15 0x00008000U
/******************** Bits definition for DMA_SxFCR register ****************/
/******************** Bits definition for DMA_SxFCR register ****************/
#define DMA_SxFCR_FEIE 0x00000080U
#define DMA_SxFCR_FS 0x00000038U
#define DMA_SxFCR_FS_0 0x00000008U
@ -2936,7 +2936,7 @@ USB_OTG_HostChannelTypeDef;
#define DMA_SxFCR_FTH_0 0x00000001U
#define DMA_SxFCR_FTH_1 0x00000002U
/******************** Bits definition for DMA_LISR register *****************/
/******************** Bits definition for DMA_LISR register *****************/
#define DMA_LISR_TCIF3 0x08000000U
#define DMA_LISR_HTIF3 0x04000000U
#define DMA_LISR_TEIF3 0x02000000U
@ -2958,7 +2958,7 @@ USB_OTG_HostChannelTypeDef;
#define DMA_LISR_DMEIF0 0x00000004U
#define DMA_LISR_FEIF0 0x00000001U
/******************** Bits definition for DMA_HISR register *****************/
/******************** Bits definition for DMA_HISR register *****************/
#define DMA_HISR_TCIF7 0x08000000U
#define DMA_HISR_HTIF7 0x04000000U
#define DMA_HISR_TEIF7 0x02000000U
@ -2980,7 +2980,7 @@ USB_OTG_HostChannelTypeDef;
#define DMA_HISR_DMEIF4 0x00000004U
#define DMA_HISR_FEIF4 0x00000001U
/******************** Bits definition for DMA_LIFCR register ****************/
/******************** Bits definition for DMA_LIFCR register ****************/
#define DMA_LIFCR_CTCIF3 0x08000000U
#define DMA_LIFCR_CHTIF3 0x04000000U
#define DMA_LIFCR_CTEIF3 0x02000000U
@ -3002,7 +3002,7 @@ USB_OTG_HostChannelTypeDef;
#define DMA_LIFCR_CDMEIF0 0x00000004U
#define DMA_LIFCR_CFEIF0 0x00000001U
/******************** Bits definition for DMA_HIFCR register ****************/
/******************** Bits definition for DMA_HIFCR register ****************/
#define DMA_HIFCR_CTCIF7 0x08000000U
#define DMA_HIFCR_CHTIF7 0x04000000U
#define DMA_HIFCR_CTEIF7 0x02000000U
@ -5921,80 +5921,80 @@ USB_OTG_HostChannelTypeDef;
/****************** Bit definition for SPI_I2SPR register *******************/
#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
/******************************************************************************/
/* */
/* SYSCFG */
/* */
/******************************************************************************/
/****************** Bit definition for SYSCFG_MEMRMP register ***************/
#define SYSCFG_MEMRMP_MEM_MODE 0x00000003U /*!<SYSCFG_Memory Remap Config */
#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
#define SYSCFG_EXTICR1_EXTI0 0x0000000FU /*!<EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1 0x000000F0U /*!<EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2 0x00000F00U /*!<EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3 0x0000F000U /*!<EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
#define SYSCFG_EXTICR1_EXTI0_PA 0x00000000U /*!<PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB 0x00000001U /*!<PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC 0x00000002U /*!<PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD 0x00000003U /*!<PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE 0x00000004U /*!<PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF 0x00000005U /*!<PF[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PG 0x00000006U /*!<PG[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PH 0x00000007U /*!<PH[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PI 0x00000008U /*!<PI[0] pin */
/**
* @brief EXTI1 configuration
*/
#define SYSCFG_EXTICR1_EXTI1_PA 0x00000000U /*!<PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB 0x00000010U /*!<PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC 0x00000020U /*!<PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD 0x00000030U /*!<PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE 0x00000040U /*!<PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF 0x00000050) /*!<PF[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PG 0x00000060U /*!<PG[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PH 0x00000070U /*!<PH[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PI 0x00000080U /*!<PI[1] pin */
/**
* @brief EXTI2 configuration
*/
#define SYSCFG_EXTICR1_EXTI2_PA 0x00000000U /*!<PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB 0x00000100U /*!<PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC 0x00000200U /*!<PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD 0x00000300U /*!<PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE 0x00000400U /*!<PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF 0x00000500) /*!<PF[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PG 0x00000600) /*!<PG[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PH 0x00000700U /*!<PH[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PI 0x00000800U /*!<PI[2] pin */
/**
* @brief EXTI3 configuration
*/
#define SYSCFG_EXTICR1_EXTI3_PA 0x00000000U /*!<PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB 0x00001000U /*!<PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC 0x00002000U /*!<PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD 0x00003000U /*!<PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE 0x00004000U /*!<PE[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF 0x00005000) /*!<PF[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PG 0x00006000U /*!<PG[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PH 0x00007000U /*!<PH[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PI 0x00008000U /*!<PI[3] pin */
#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
/******************************************************************************/
/* */
/* SYSCFG */
/* */
/******************************************************************************/
/****************** Bit definition for SYSCFG_MEMRMP register ***************/
#define SYSCFG_MEMRMP_MEM_MODE 0x00000003U /*!<SYSCFG_Memory Remap Config */
#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
#define SYSCFG_EXTICR1_EXTI0 0x0000000FU /*!<EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1 0x000000F0U /*!<EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2 0x00000F00U /*!<EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3 0x0000F000U /*!<EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
#define SYSCFG_EXTICR1_EXTI0_PA 0x00000000U /*!<PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB 0x00000001U /*!<PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC 0x00000002U /*!<PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD 0x00000003U /*!<PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE 0x00000004U /*!<PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF 0x00000005U /*!<PF[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PG 0x00000006U /*!<PG[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PH 0x00000007U /*!<PH[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PI 0x00000008U /*!<PI[0] pin */
/**
* @brief EXTI1 configuration
*/
#define SYSCFG_EXTICR1_EXTI1_PA 0x00000000U /*!<PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB 0x00000010U /*!<PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC 0x00000020U /*!<PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD 0x00000030U /*!<PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE 0x00000040U /*!<PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF 0x00000050) /*!<PF[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PG 0x00000060U /*!<PG[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PH 0x00000070U /*!<PH[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PI 0x00000080U /*!<PI[1] pin */
/**
* @brief EXTI2 configuration
*/
#define SYSCFG_EXTICR1_EXTI2_PA 0x00000000U /*!<PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB 0x00000100U /*!<PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC 0x00000200U /*!<PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD 0x00000300U /*!<PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE 0x00000400U /*!<PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF 0x00000500) /*!<PF[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PG 0x00000600) /*!<PG[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PH 0x00000700U /*!<PH[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PI 0x00000800U /*!<PI[2] pin */
/**
* @brief EXTI3 configuration
*/
#define SYSCFG_EXTICR1_EXTI3_PA 0x00000000U /*!<PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB 0x00001000U /*!<PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC 0x00002000U /*!<PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD 0x00003000U /*!<PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE 0x00004000U /*!<PE[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF 0x00005000) /*!<PF[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PG 0x00006000U /*!<PG[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PH 0x00007000U /*!<PH[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PI 0x00008000U /*!<PI[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
#define SYSCFG_EXTICR2_EXTI4 0x0000000FU /*!<EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5 0x000000F0U /*!<EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6 0x00000F00U /*!<EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7 0x0000F000U /*!<EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
/**
* @brief EXTI4 configuration
*/
#define SYSCFG_EXTICR2_EXTI4_PA 0x00000000U /*!<PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB 0x00000001U /*!<PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC 0x00000002U /*!<PC[4] pin */
@ -6004,9 +6004,9 @@ USB_OTG_HostChannelTypeDef;
#define SYSCFG_EXTICR2_EXTI4_PG 0x00000006U /*!<PG[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PH 0x00000007U /*!<PH[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PI 0x00000008U /*!<PI[4] pin */
/**
* @brief EXTI5 configuration
*/
/**
* @brief EXTI5 configuration
*/
#define SYSCFG_EXTICR2_EXTI5_PA 0x00000000U /*!<PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB 0x00000010U /*!<PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC 0x00000020U /*!<PC[5] pin */
@ -6016,9 +6016,9 @@ USB_OTG_HostChannelTypeDef;
#define SYSCFG_EXTICR2_EXTI5_PG 0x00000060U /*!<PG[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PH 0x00000070U /*!<PH[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PI 0x00000080U /*!<PI[5] pin */
/**
* @brief EXTI6 configuration
*/
/**
* @brief EXTI6 configuration
*/
#define SYSCFG_EXTICR2_EXTI6_PA 0x00000000U /*!<PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB 0x00000100U /*!<PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC 0x00000200U /*!<PC[6] pin */
@ -6028,9 +6028,9 @@ USB_OTG_HostChannelTypeDef;
#define SYSCFG_EXTICR2_EXTI6_PG 0x00000600) /*!<PG[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PH 0x00000700U /*!<PH[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PI 0x00000800U /*!<PI[6] pin */
/**
* @brief EXTI7 configuration
*/
/**
* @brief EXTI7 configuration
*/
#define SYSCFG_EXTICR2_EXTI7_PA 0x00000000U /*!<PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB 0x00001000U /*!<PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC 0x00002000U /*!<PC[7] pin */
@ -6046,10 +6046,10 @@ USB_OTG_HostChannelTypeDef;
#define SYSCFG_EXTICR3_EXTI9 0x000000F0U /*!<EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10 0x00000F00U /*!<EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11 0x0000F000U /*!<EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
/**
* @brief EXTI8 configuration
*/
#define SYSCFG_EXTICR3_EXTI8_PA 0x00000000U /*!<PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB 0x00000001U /*!<PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC 0x00000002U /*!<PC[8] pin */
@ -6059,9 +6059,9 @@ USB_OTG_HostChannelTypeDef;
#define SYSCFG_EXTICR3_EXTI8_PG 0x00000006U /*!<PG[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PH 0x00000007U /*!<PH[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PI 0x00000008U /*!<PI[8] pin */
/**
* @brief EXTI9 configuration
*/
/**
* @brief EXTI9 configuration
*/
#define SYSCFG_EXTICR3_EXTI9_PA 0x00000000U /*!<PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB 0x00000010U /*!<PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC 0x00000020U /*!<PC[9] pin */
@ -6071,9 +6071,9 @@ USB_OTG_HostChannelTypeDef;
#define SYSCFG_EXTICR3_EXTI9_PG 0x00000060U /*!<PG[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PH 0x00000070U /*!<PH[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PI 0x00000080U /*!<PI[9] pin */
/**
* @brief EXTI10 configuration
*/
/**
* @brief EXTI10 configuration
*/
#define SYSCFG_EXTICR3_EXTI10_PA 0x00000000U /*!<PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB 0x00000100U /*!<PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC 0x00000200U /*!<PC[10] pin */
@ -6083,9 +6083,9 @@ USB_OTG_HostChannelTypeDef;
#define SYSCFG_EXTICR3_EXTI10_PG 0x00000600) /*!<PG[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PH 0x00000700U /*!<PH[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PI 0x00000800U /*!<PI[10] pin */
/**
* @brief EXTI11 configuration
*/
/**
* @brief EXTI11 configuration
*/
#define SYSCFG_EXTICR3_EXTI11_PA 0x00000000U /*!<PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB 0x00001000U /*!<PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC 0x00002000U /*!<PC[11] pin */
@ -6101,9 +6101,9 @@ USB_OTG_HostChannelTypeDef;
#define SYSCFG_EXTICR4_EXTI13 0x000000F0U /*!<EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14 0x00000F00U /*!<EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15 0x0000F000U /*!<EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
/**
* @brief EXTI12 configuration
*/
#define SYSCFG_EXTICR4_EXTI12_PA 0x00000000U /*!<PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB 0x00000001U /*!<PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC 0x00000002U /*!<PC[12] pin */
@ -6112,9 +6112,9 @@ USB_OTG_HostChannelTypeDef;
#define SYSCFG_EXTICR4_EXTI12_PF 0x00000005U /*!<PF[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PG 0x00000006U /*!<PG[12] pin */
#define SYSCFG_EXTICR3_EXTI12_PH 0x00000007U /*!<PH[12] pin */
/**
* @brief EXTI13 configuration
*/
/**
* @brief EXTI13 configuration
*/
#define SYSCFG_EXTICR4_EXTI13_PA 0x00000000U /*!<PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB 0x00000010U /*!<PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC 0x00000020U /*!<PC[13] pin */
@ -6123,9 +6123,9 @@ USB_OTG_HostChannelTypeDef;
#define SYSCFG_EXTICR4_EXTI13_PF 0x00000050) /*!<PF[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PG 0x00000060U /*!<PG[13] pin */
#define SYSCFG_EXTICR3_EXTI13_PH 0x00000070U /*!<PH[13] pin */
/**
* @brief EXTI14 configuration
*/
/**
* @brief EXTI14 configuration
*/
#define SYSCFG_EXTICR4_EXTI14_PA 0x00000000U /*!<PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB 0x00000100U /*!<PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC 0x00000200U /*!<PC[14] pin */
@ -6134,9 +6134,9 @@ USB_OTG_HostChannelTypeDef;
#define SYSCFG_EXTICR4_EXTI14_PF 0x00000500) /*!<PF[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PG 0x00000600) /*!<PG[14] pin */
#define SYSCFG_EXTICR3_EXTI14_PH 0x00000700U /*!<PH[14] pin */
/**
* @brief EXTI15 configuration
*/
/**
* @brief EXTI15 configuration
*/
#define SYSCFG_EXTICR4_EXTI15_PA 0x00000000U /*!<PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB 0x00001000U /*!<PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC 0x00002000U /*!<PC[15] pin */
@ -6146,7 +6146,7 @@ USB_OTG_HostChannelTypeDef;
#define SYSCFG_EXTICR4_EXTI15_PG 0x00006000U /*!<PG[15] pin */
#define SYSCFG_EXTICR3_EXTI15_PH 0x00007000U /*!<PH[15] pin */
/****************** Bit definition for SYSCFG_CMPCR register ****************/
/****************** Bit definition for SYSCFG_CMPCR register ****************/
#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
@ -7294,7 +7294,7 @@ USB_OTG_HostChannelTypeDef;
/**
* @}
*/
*/
/**
* @}
@ -7303,7 +7303,7 @@ USB_OTG_HostChannelTypeDef;
/** @addtogroup Exported_macros
* @{
*/
/******************************* ADC Instances ********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
((INSTANCE) == ADC2) || \
@ -7312,7 +7312,7 @@ USB_OTG_HostChannelTypeDef;
/******************************* CAN Instances ********************************/
#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
((INSTANCE) == CAN2))
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
@ -7463,7 +7463,7 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
((INSTANCE) == TIM8))
/******************** TIM Instances : DMA burst feature ***********************/
#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
@ -7614,7 +7614,7 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == USART6))
((INSTANCE) == USART6))
/*********************** PCD Instances ****************************************/
#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
@ -7646,7 +7646,7 @@ USB_OTG_HostChannelTypeDef;
/**
* @}
*/
*/
/**
* @}

46
board/inc/stm32f2xx.h
View File

@ -4,17 +4,17 @@
* @author MCD Application Team
* @version V2.1.2
* @date 29-June-2016
* @brief CMSIS STM32F2xx Device Peripheral Access Layer Header File.
* @brief CMSIS STM32F2xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F2xx device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* rather than drivers API), this option is controlled by
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
*
******************************************************************************
* @attention
*
@ -52,14 +52,14 @@
/** @addtogroup stm32f2xx
* @{
*/
#ifndef __STM32F2xx_H
#define __STM32F2xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
@ -70,9 +70,9 @@
#if !defined (STM32F2)
#define STM32F2
#endif /* STM32F2 */
/* Uncomment the line below according to the target STM32 device used in your
application
application
*/
#if !defined (STM32F205xx) && !defined (STM32F215xx) && !defined (STM32F207xx) && !defined (STM32F217xx)
@ -83,17 +83,17 @@
/* #define STM32F207xx */ /*!< STM32F207VG, STM32F207ZG, STM32F207IG, STM32F207VF, STM32F207ZF, STM32F207IF,
STM32F207VE, STM32F207ZE, STM32F207IE, STM32F207VC, STM32F207ZC and STM32F207IC Devices */
/* #define STM32F217xx */ /*!< STM32F217VG, STM32F217ZG, STM32F217IG, STM32F217VE, STM32F217ZE and STM32F217IE Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */
@ -136,23 +136,23 @@
/** @addtogroup Exported_types
* @{
*/
typedef enum
*/
typedef enum
{
RESET = 0,
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
typedef enum
{
DISABLE = 0,
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
typedef enum
{
ERROR = 0,
ERROR = 0,
SUCCESS = !ERROR
} ErrorStatus;
@ -178,13 +178,13 @@ typedef enum
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
*/
#if defined (USE_HAL_DRIVER)
#include "stm32f2xx_hal.h"
#endif /* USE_HAL_DRIVER */
@ -202,7 +202,7 @@ typedef enum
/**
* @}
*/

46
board/inc/stm32f2xx_hal_def.h
View File

@ -4,8 +4,8 @@
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
@ -51,10 +51,10 @@
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL Status structures definition
*/
typedef enum
/**
* @brief HAL Status structures definition
*/
typedef enum
{
HAL_OK = 0x00U,
HAL_ERROR = 0x01U,
@ -62,13 +62,13 @@ typedef enum
HAL_TIMEOUT = 0x03U
} HAL_StatusTypeDef;
/**
* @brief HAL Lock structures definition
/**
* @brief HAL Lock structures definition
*/
typedef enum
typedef enum
{
HAL_UNLOCKED = 0x00U,
HAL_LOCKED = 0x01U
HAL_LOCKED = 0x01U
} HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/
@ -84,14 +84,14 @@ typedef enum
} while(0)
#define UNUSED(x) ((void)(x))
/** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
* @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field.
* Otherwise, "State" field may have any random value and the first time the function
* Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling
@ -133,34 +133,34 @@ typedef enum
#endif /* __packed */
#endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined (__GNUC__) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4)
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
/**
/**
* @brief __NOINLINE definition
*/
*/
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
/* ARM & GNUCompiler
----------------
/* ARM & GNUCompiler
----------------
*/
#define __NOINLINE __attribute__ ( (noinline) )

118
board/inc/stm32f2xx_hal_gpio_ex.h
View File

@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F2xx_HAL_GPIO_EX_H
@ -52,7 +52,7 @@
/** @defgroup GPIOEx GPIOEx
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
@ -60,117 +60,117 @@
/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_Alternate_function_selection GPIO Alternate function selection
*/
/** @defgroup GPIO_Alternate_function_selection GPIO Alternate function selection
* @{
*/
/**
* @brief AF 0 selection
*/
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
/**
* @brief AF 1 selection
*/
#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
/**
* @brief AF 2 selection
*/
/**
* @brief AF 2 selection
*/
#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
/**
* @brief AF 3 selection
*/
#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */
#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */
#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */
#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */
/**
* @brief AF 4 selection
*/
/**
* @brief AF 4 selection
*/
#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
/**
* @brief AF 5 selection
*/
#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
/**
* @brief AF 6 selection
*/
/**
* @brief AF 6 selection
*/
#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
/**
* @brief AF 7 selection
*/
/**
* @brief AF 7 selection
*/
#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
/**
* @brief AF 8 selection
*/
/**
* @brief AF 8 selection
*/
#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */
#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */
#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
/**
* @brief AF 9 selection
*/
#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */
#define GPIO_AF9_CAN2 ((uint8_t)0x09U) /* CAN2 Alternate Function mapping */
#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */
#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */
#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */
/**
* @brief AF 10 selection
*/
/**
* @brief AF 10 selection
*/
#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */
#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */
/**
* @brief AF 11 selection
*/
/**
* @brief AF 11 selection
*/
#if defined(STM32F207xx) || defined(STM32F217xx)
#define GPIO_AF11_ETH ((uint8_t)0x0BU) /* ETHERNET Alternate Function mapping */
#endif /* STM32F207xx || STM32F217xx */
/**
* @brief AF 12 selection
*/
/**
* @brief AF 12 selection
*/
#define GPIO_AF12_FSMC ((uint8_t)0xCU) /* FSMC Alternate Function mapping */
#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */
#define GPIO_AF12_SDIO ((uint8_t)0xCU) /* SDIO Alternate Function mapping */
/**
* @brief AF 13 selection
*/
/**
* @brief AF 13 selection
*/
#if defined(STM32F207xx) || defined(STM32F217xx)
#define GPIO_AF13_DCMI ((uint8_t)0x0DU) /* DCMI Alternate Function mapping */
#endif /* STM32F207xx || STM32F217xx */
/**
* @brief AF 15 selection
*/
/**
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
/**
* @}
*/
*/
/**
* @}
@ -184,7 +184,7 @@
* @}
*/
/* Exported functions --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
* @{
*/
@ -224,9 +224,9 @@
/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
* @{
*/
*/
#if defined(STM32F207xx) || defined(STM32F217xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
@ -264,10 +264,10 @@
((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO) || \
((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT))
#endif /* STM32F207xx || STM32F217xx */
/**
* @}
*/
*/
/**
* @}
@ -284,12 +284,12 @@
/**
* @}
*/
*/
/**
* @}
*/
*/
#ifdef __cplusplus
}
#endif

8568
board/inc/stm32f413xx.h
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52
board/inc/stm32f4xx.h
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@ -5,16 +5,16 @@
* @version V2.6.0
* @date 04-November-2016
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F4xx device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* rather than drivers API), this option is controlled by
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
*
******************************************************************************
* @attention
*
@ -52,18 +52,18 @@
/** @addtogroup stm32f4xx
* @{
*/
#ifndef __STM32F4xx_H
#define __STM32F4xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief STM32 Family
*/
@ -72,7 +72,7 @@
#endif /* STM32F4 */
/* Uncomment the line below according to the target STM32 device used in your
application
application
*/
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
@ -86,9 +86,9 @@
/* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
/* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
/* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
/* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
/* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
STM32F439NI, STM32F429IG and STM32F429II Devices */
/* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
/* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
@ -96,11 +96,11 @@
/* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
/* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
/* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
/* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
/* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
and STM32F446ZE Devices */
/* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
/* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
/* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
/* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
and STM32F479NG Devices */
/* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
/* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
@ -110,15 +110,15 @@
STM32F413RG, STM32F413VG and STM32F413ZG Devices */
/* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */
@ -199,23 +199,23 @@
/** @addtogroup Exported_types
* @{
*/
typedef enum
*/
typedef enum
{
RESET = 0U,
RESET = 0U,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
typedef enum
{
DISABLE = 0U,
DISABLE = 0U,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
typedef enum
{
ERROR = 0U,
ERROR = 0U,
SUCCESS = !ERROR
} ErrorStatus;
@ -241,7 +241,7 @@ typedef enum
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
@ -264,7 +264,7 @@ typedef enum
/**
* @}
*/

58
board/inc/stm32f4xx_hal_def.h
View File

@ -4,8 +4,8 @@
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
@ -51,10 +51,10 @@
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL Status structures definition
*/
typedef enum
/**
* @brief HAL Status structures definition
*/
typedef enum
{
HAL_OK = 0x00U,
HAL_ERROR = 0x01U,
@ -62,13 +62,13 @@ typedef enum
HAL_TIMEOUT = 0x03U
} HAL_StatusTypeDef;
/**
* @brief HAL Lock structures definition
/**
* @brief HAL Lock structures definition
*/
typedef enum
typedef enum
{
HAL_UNLOCKED = 0x00U,
HAL_LOCKED = 0x01U
HAL_LOCKED = 0x01U
} HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/
@ -87,11 +87,11 @@ typedef enum
/** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
* @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field.
* Otherwise, "State" field may have any random value and the first time the function
* Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling
@ -139,61 +139,61 @@ typedef enum
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4)
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
/**
/**
* @brief __RAM_FUNC definition
*/
*/
#if defined ( __CC_ARM )
/* ARM Compiler
------------
RAM functions are defined using the toolchain options.
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
dialog.
dialog.
*/
#define __RAM_FUNC HAL_StatusTypeDef
#define __RAM_FUNC HAL_StatusTypeDef
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
RAM functions are defined using a specific toolchain keyword "__ramfunc".
RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/
#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
#elif defined ( __GNUC__ )
/* GNU Compiler
------------
RAM functions are defined using a specific toolchain attribute
RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
*/
#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc")))
#endif
/**
/**
* @brief __NOINLINE definition
*/
*/
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
/* ARM & GNUCompiler
----------------
/* ARM & GNUCompiler
----------------
*/
#define __NOINLINE __attribute__ ( (noinline) )

976
board/inc/stm32f4xx_hal_gpio_ex.h
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20
board/inc/system_stm32f2xx.h
View File

@ -4,7 +4,7 @@
* @author MCD Application Team
* @version V2.1.2
* @date 29-June-2016
* @brief CMSIS Cortex-M3 Device System Source File for STM32F2xx devices.
* @brief CMSIS Cortex-M3 Device System Source File for STM32F2xx devices.
******************************************************************************
* @attention
*
@ -32,8 +32,8 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
@ -41,8 +41,8 @@
/** @addtogroup stm32f2xx_system
* @{
*/
*/
/**
* @brief Define to prevent recursive inclusion
*/
@ -51,7 +51,7 @@
#ifdef __cplusplus
extern "C" {
#endif
#endif
/** @addtogroup STM32F2xx_System_Includes
* @{
@ -68,7 +68,7 @@
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
@ -99,7 +99,7 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Cloc
/** @addtogroup STM32F2xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
@ -115,8 +115,8 @@ extern void SystemCoreClockUpdate(void);
/**
* @}
*/
/**
* @}
*/
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

22
board/inc/system_stm32f4xx.h
View File

@ -4,8 +4,8 @@
* @author MCD Application Team
* @version V2.6.0
* @date 04-November-2016
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
@ -32,8 +32,8 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
@ -41,8 +41,8 @@
/** @addtogroup stm32f4xx_system
* @{
*/
*/
/**
* @brief Define to prevent recursive inclusion
*/
@ -51,7 +51,7 @@
#ifdef __cplusplus
extern "C" {
#endif
#endif
/** @addtogroup STM32F4xx_System_Includes
* @{
@ -68,7 +68,7 @@
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
@ -101,7 +101,7 @@ extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/** @addtogroup STM32F4xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
@ -117,8 +117,8 @@ extern void SystemCoreClockUpdate(void);
/**
* @}
*/
/**
* @}
*/
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

40
board/startup_stm32f205xx.s
View File

@ -4,7 +4,7 @@
* @author MCD Application Team
* @version V2.1.2
* @date 29-June-2016
* @brief STM32F205xx Devices vector table for Atollic TrueSTUDIO toolchain.
* @brief STM32F205xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
@ -42,7 +42,7 @@
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.thumb
@ -50,10 +50,10 @@
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
@ -67,7 +67,7 @@ defined in linker script */
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* supplied main() routine is called.
* @param None
* @retval : None
*/
@ -75,7 +75,7 @@ defined in linker script */
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
bl __initialize_hardware_early
@ -88,7 +88,7 @@ CopyDataInit:
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
@ -101,7 +101,7 @@ LoopCopyDataInit:
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
@ -113,15 +113,15 @@ LoopFillZerobss:
/*bl __libc_init_array*/
/* Call the application's entry point.*/
bl main
bx lr
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
@ -133,14 +133,14 @@ Infinite_Loop:
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
@ -159,7 +159,7 @@ g_pfnVectors:
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detection */
@ -248,7 +248,7 @@ g_pfnVectors:
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
@ -302,7 +302,7 @@ g_pfnVectors:
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
@ -320,7 +320,7 @@ g_pfnVectors:
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
@ -432,7 +432,7 @@ g_pfnVectors:
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler

58
board/startup_stm32f413xx.s
View File

@ -4,7 +4,7 @@
* @author MCD Application Team
* @version V2.6.0
* @date 04-November-2016
* @brief STM32F413xx Devices vector table for GCC based toolchains.
* @brief STM32F413xx Devices vector table for GCC based toolchains.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
@ -42,7 +42,7 @@
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
@ -51,7 +51,7 @@
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
@ -68,7 +68,7 @@ defined in linker script */
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* supplied main() routine is called.
* @param None
* @retval : None
*/
@ -76,7 +76,7 @@ defined in linker script */
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
bl __initialize_hardware_early
@ -89,7 +89,7 @@ CopyDataInit:
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
@ -102,7 +102,7 @@ LoopCopyDataInit:
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
@ -114,15 +114,15 @@ LoopFillZerobss:
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl main
bx lr
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
@ -134,12 +134,12 @@ Infinite_Loop:
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
@ -261,11 +261,11 @@ g_pfnVectors:
.word DFSDM2_FLT1_IRQHandler /* DFSDM2 Filter1 */
.word DFSDM2_FLT2_IRQHandler /* DFSDM2 Filter2 */
.word DFSDM2_FLT3_IRQHandler /* DFSDM2 Filter3 */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
@ -277,7 +277,7 @@ g_pfnVectors:
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
@ -321,7 +321,7 @@ g_pfnVectors:
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
@ -439,9 +439,9 @@ g_pfnVectors:
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FSMC_IRQHandler
.thumb_set FSMC_IRQHandler,Default_Handler
.thumb_set FSMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
@ -451,12 +451,12 @@ g_pfnVectors:
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
@ -517,7 +517,7 @@ g_pfnVectors:
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak CAN3_TX_IRQHandler
.thumb_set CAN3_TX_IRQHandler,Default_Handler
@ -528,26 +528,26 @@ g_pfnVectors:
.thumb_set CAN3_RX1_IRQHandler,Default_Handler
.weak CAN3_SCE_IRQHandler
.thumb_set CAN3_SCE_IRQHandler,Default_Handler
.thumb_set CAN3_SCE_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
@ -555,7 +555,7 @@ g_pfnVectors:
.thumb_set UART9_IRQHandler,Default_Handler
.weak UART10_IRQHandler
.thumb_set UART10_IRQHandler,Default_Handler
.thumb_set UART10_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
@ -565,7 +565,7 @@ g_pfnVectors:
.weak FMPI2C1_ER_IRQHandler
.thumb_set FMPI2C1_ER_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler

10
boardesp/webserver.c
View File

@ -84,7 +84,7 @@ int ICACHE_FLASH_ATTR usb_cmd(int ep, int len, int request,
return recv[0];
}
void ICACHE_FLASH_ATTR st_flash() {
if (st_firmware != NULL) {
@ -212,14 +212,14 @@ static void ICACHE_FLASH_ATTR web_rx_cb(void *arg, char *data, uint16_t len) {
} else {
ets_strcat(resp, "\nin INSECURE mode...<a href=\"/secure\">secure it</a>");
}
ets_strcat(resp,"\nSet USB Mode:"
"<button onclick=\"var xhr = new XMLHttpRequest(); xhr.open('GET', 'set_property?usb_mode=0'); xhr.send()\" type='button'>Client</button>"
"<button onclick=\"var xhr = new XMLHttpRequest(); xhr.open('GET', 'set_property?usb_mode=1'); xhr.send()\" type='button'>CDP</button>"
"<button onclick=\"var xhr = new XMLHttpRequest(); xhr.open('GET', 'set_property?usb_mode=2'); xhr.send()\" type='button'>DCP</button>\n");
ets_strcat(resp, pagefooter);
espconn_send_string(&web_conn, resp);
espconn_disconnect(conn);
} else if (memcmp(data, "GET /secure", 11) == 0 && !wifi_secure_mode) {
@ -235,7 +235,7 @@ static void ICACHE_FLASH_ATTR web_rx_cb(void *arg, char *data, uint16_t len) {
os_sprintf(resp, "%sUSB Mode set to %02x\n\n", OK_header, mode_value);
espconn_send_string(&web_conn, resp);
espconn_disconnect(conn);
}
}
} else if (memcmp(data, "PUT /stupdate ", 14) == 0 && wifi_secure_mode) {
os_printf("init st firmware\n");
char *cl = strstr(data, "Content-Length: ");
@ -251,7 +251,7 @@ static void ICACHE_FLASH_ATTR web_rx_cb(void *arg, char *data, uint16_t len) {
memset(st_firmware, 0, real_content_length);
state = RECEIVING_ST_FIRMWARE;
}
} else if (((memcmp(data, "PUT /espupdate1 ", 16) == 0) ||
(memcmp(data, "PUT /espupdate2 ", 16) == 0)) && wifi_secure_mode) {
// 0x1000 = user1.bin

2
crypto/sha.c
View File

@ -130,7 +130,7 @@ const uint8_t* SHA_final(SHA_CTX* ctx) {
/* Hack - right shift operator with non const argument requires
* libgcc.a which is missing in EON
* thus expanding for loop from
* thus expanding for loop from
for (i = 0; i < 8; ++i) {
uint8_t tmp = (uint8_t) (cnt >> ((7 - i) * 8));

2
drivers/windows/pandaJ2534DLL/PandaJ2534Device.cpp
View File

@ -93,7 +93,7 @@ DWORD PandaJ2534Device::can_process_thread() {
if (count == 0) {
continue;
}
for (int i = 0; i < count; i++) {
auto msg_in = msg_recv[i];
J2534Frame msg_out(msg_in);

2
drivers/windows/pandaJ2534DLL/resource.h
View File

@ -3,7 +3,7 @@
// Used by pandaJ2534DLL.rc
// Next default values for new objects
//
//
#ifdef APSTUDIO_INVOKED
#ifndef APSTUDIO_READONLY_SYMBOLS
#define _APS_NEXT_RESOURCE_VALUE 101

4
examples/can_unique.md
View File

@ -10,8 +10,8 @@ First record a few minutes of background CAN messages with all the doors closed
./can_logger.py
mv output.csv background.csv
```
Then run can_logger.py for a few seconds while performing the action you're interested, such as opening and then closing the
front-left door and save it as door-fl-1.csv
Then run can_logger.py for a few seconds while performing the action you're interested, such as opening and then closing the
front-left door and save it as door-fl-1.csv
Repeat the process and save it as door-f1-2.csv to have an easy way to confirm any suspicions.
Now we'll use can_unique.py to look for unique bits:

6
examples/get_panda_password.py
View File

@ -2,11 +2,11 @@
from panda import Panda
def get_panda_password():
try:
print("Trying to connect to Panda over USB...")
p = Panda()
except AssertionError:
print("USB connection failed")
sys.exit(0)
@ -15,6 +15,6 @@ def get_panda_password():
#print('[%s]' % ', '.join(map(str, wifi)))
print("SSID: " + wifi[0])
print("Password: " + wifi[1])
if __name__ == "__main__":
get_panda_password()

16
examples/tesla_tester.py
View File

@ -4,14 +4,14 @@ import binascii
from panda import Panda
def tesla_tester():
try:
print("Trying to connect to Panda over USB...")
p = Panda()
except AssertionError:
print("USB connection failed. Trying WiFi...")
try:
p = Panda("WIFI")
except:
@ -21,12 +21,12 @@ def tesla_tester():
body_bus_speed = 125 # Tesla Body busses (B, BF) are 125kbps, rest are 500kbps
body_bus_num = 1 # My TDC to OBD adapter has PT on bus0 BDY on bus1 and CH on bus2
p.set_can_speed_kbps(body_bus_num, body_bus_speed)
# Now set the panda from its default of SAFETY_NOOUTPUT (read only) to SAFETY_ALLOUTPUT
# Careful, as this will let us send any CAN messages we want (which could be very bad!)
print("Setting Panda to output mode...")
p.set_safety_mode(Panda.SAFETY_ALLOUTPUT)
# BDY 0x248 is the MCU_commands message, which includes folding mirrors, opening the trunk, frunk, setting the cars lock state and more. For our test, we will edit the 3rd byte, which is MCU_lockRequest. 0x01 will lock, 0x02 will unlock:
print("Unlocking Tesla...")
p.can_send(0x248, "\x00\x00\x02\x00\x00\x00\x00\x00", body_bus_num)
@ -34,13 +34,13 @@ def tesla_tester():
#Or, we can set the first byte, MCU_frontHoodCommand + MCU_liftgateSwitch, to 0x01 to pop the frunk, or 0x04 to open/close the trunk (0x05 should open both)
print("Opening Frunk...")
p.can_send(0x248, "\x01\x00\x00\x00\x00\x00\x00\x00", body_bus_num)
#Back to safety...
print("Disabling output on Panda...")
p.set_safety_mode(Panda.SAFETY_NOOUTPUT)
print("Reading VIN from 0x568. This is painfully slow and can take up to 3 minutes (1 minute per message; 3 messages needed for full VIN)...")
vin = {}
while True:
#Read the VIN

2
python/flash_release.py
View File

@ -89,7 +89,7 @@ def flash_release(path=None, st_serial=None):
# done!
status("6. Success!")
if __name__ == "__main__":
flash_release(*sys.argv[1:])

2
python/isotp.py
View File

@ -29,7 +29,7 @@ def recv(panda, cnt, addr, nbus):
def isotp_recv_subaddr(panda, addr, bus, sendaddr, subaddr):
msg = recv(panda, 1, addr, bus)[0]
# TODO: handle other subaddr also communicating
# TODO: handle other subaddr also communicating
assert ord(msg[0]) == subaddr
if ord(msg[1])&0xf0 == 0x10: