WIP: attempt to fix bug in smartdsu timeout
parent
d527579b41
commit
e59134fec0
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@ -233,7 +233,6 @@ bool send = 0;
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//------------- BUS 1 - PTCAN ------------//
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#define ACC_CTRL 0xF10
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#define ACC_CTRL_OP 0x343
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bool enable_acc = 0;
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bool op_ctrl_mode = 0;
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int acc_cmd = 0;
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@ -284,9 +283,11 @@ void CAN1_RX0_IRQ_Handler(void) {
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}
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}
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break;
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case ACC_CTRL_OP: // hack to allow the firmware to support stock OP
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case DSU_ACC_CONTROL: // hack to allow the firmware to support stock OP
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to_fwd.RIR &= 0xFFFFFFFE; // do not fwd
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op_ctrl_mode = 1;
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// reset timer for op_ctrl_mode
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TIM2->CNT = 0;
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break;
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case ACC_CTRL:
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// send this EXACTLY how ACC_CONTROL is sent
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@ -532,6 +533,12 @@ void TIM3_IRQ_Handler(void) {
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}
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TIM3->SR = 0;
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// check TIM2 for op_ctrl_mode timer
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uint32_t op_ts = TIM2->CNT;
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if (op_ts > 100000){
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op_ctrl_mode = 0;
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}
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#ifdef DEBUG_CTRL
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puts("enable_acc: ");
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puth2(enable_acc);
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