306 lines
12 KiB
C
306 lines
12 KiB
C
#ifndef TMC2130_BASICS_REG_H
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#define TMC2130_BASICS_REG_H
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#if ARDUINO >= 100
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#include "Arduino.h"
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#else
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#include "WProgram.h"
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#endif
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#include <SPI.h>
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// SPI
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#define FB_TMC_SPI_CLOCK_DIVIDER SPI_CLOCK_DIV8
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#define FB_TMC_SPI_DATA_MODE SPI_MODE3
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#define FB_TMC_SPI_BIT_ORDER MSBFIRST
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// RW
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#define FB_TMC_READ (0x00)
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#define FB_TMC_WRITE (0x80)
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// SPISTATUS MASKS
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#define FB_TMC_SPISTATUS_RESET_MASK (0x01)
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#define FB_TMC_SPISTATUS_ERROR_MASK (0x02)
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#define FB_TMC_SPISTATUS_STALLGUARD_MASK (0x04)
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#define FB_TMC_SPISTATUS_STANDSTILL_MASK (0x08)
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// REGISTERS
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#define FB_TMC_REG_GCONF (0x00) // RW // 17 // Global configuration flags
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#define FB_TMC_REG_GSTAT (0x01) // RC // 3 // Global status flags
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#define FB_TMC_REG_IOIN (0x04) // R // 8+8 // Reads the state of all input pins available
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#define FB_TMC_REG_IHOLD_IRUN (0x10) // W // 5+5+4 // Driver current control
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#define FB_TMC_REG_TPOWERDOWN (0x11) // W // 8 // sets delay time after stand still (stst) to motor current power down (0-4 seconds) 0_((2^8)-1) * 2^18 tclk
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#define FB_TMC_REG_TSTEP (0x12) // R // 20 // Actual measured time between two 1/256 microsteps derived from the step input frequency in units of 1/fCLK. Measured value is (2^20)-1 in case of overflow or stand still
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#define FB_TMC_REG_TPWMTHRS (0x13) // W // 20 // Upper velocity threshold for stealthChop voltage PWM mode
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#define FB_TMC_REG_TCOOLTHRS (0x14) // W // 20 // Lower threshold velocity for switching on smart energy coolStep and stallGuard feature (unsigned)
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#define FB_TMC_REG_THIGH (0x15) // W // 20 // Velocity dependend switching into different chopper mode and fullstepping to maximize torque (unsigned)
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#define FB_TMC_REG_XDIRECT (0x2D) // RW // 32 // specifies motor coil currents and polarity directly programmed via SPI. Use signed, two's complement numbers. In this mode, the current is scaled by IHOLD. Velocity based current regulation of voltage PWM is not available in this mode. +- 255 for both coils
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#define FB_TMC_REG_VDCMIN (0x33) // W // 23 // automatic commutation dcStep becomes enabled by the external signal DCEN. VDCMIN is used as the minimum step velocity when the motor is heavily loaded. Hint: Also set DCCTRL parameters in order to operate dcStep
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#define FB_TMC_REG_MSLUT0 (0x60) // W // 32 // Each bit gives the difference between entry x and entry x+1 when combined with the corresponding MSLUTSEL W bits. Differential coding for the first quarter of a wave. Start values for CUR_A and CUR_B are stored for MSCNT position 0 in START_SIN and START_SIN90.
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#define FB_TMC_REG_MSLUT1 (0x61) // W // 32 //
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#define FB_TMC_REG_MSLUT2 (0x62) // W // 32 //
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#define FB_TMC_REG_MSLUT3 (0x63) // W // 32 //
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#define FB_TMC_REG_MSLUT4 (0x64) // W // 32 //
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#define FB_TMC_REG_MSLUT5 (0x65) // W // 32 //
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#define FB_TMC_REG_MSLUT6 (0x66) // W // 32 //
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#define FB_TMC_REG_MSLUT7 (0x67) // W // 32 //
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#define FB_TMC_REG_MSLUTSEL (0x68) // W // 32 // defines four segments within each quarter MSLUT wave. Four 2 bit entries determine the meaning of a 0 and a 1 bit in the corresponding segment of MSLUT
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#define FB_TMC_REG_MSLUTSTART (0x69) // W // 8+8 //
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#define FB_TMC_REG_MSCNT (0x6A) // R // 10 //
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#define FB_TMC_REG_MSCURACT (0x6B) // R // 9+9 //
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#define FB_TMC_REG_CHOPCONF (0x6C) // RW // 32 //
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#define FB_TMC_REG_COOLCONF (0x6D) // W // 25 //
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#define FB_TMC_REG_DCCTRL (0x6E) // W // 24 //
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#define FB_TMC_REG_DRV_STATUS (0x6F) // R // 22 //
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#define FB_TMC_REG_PWMCONF (0x70) // W // 8 //
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#define FB_TMC_REG_PWM_SCALE (0x71) // R // 8 //
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#define FB_TMC_REG_ENCM_CTRL (0x72) // W // 2 //
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#define FB_TMC_REG_LOST_STEPS (0x73) // R // 20 //
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// GCONF OFFSETS
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// for shifting incoming values to the right register position
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#define FB_TMC_GCONF_I_SCALE_ANALOG (0) // 0: Internal, 1: AIN
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#define FB_TMC_GCONF_INTERNAL_RSENSE (1) // 0: Normal, 1: Internal
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#define FB_TMC_GCONF_EN_PWM_MODE (2) // 0: Disable, 1: Enable
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#define FB_TMC_GCONF_ENC_COMMUTATION (3) // 0: Disable, 1: Enable
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#define FB_TMC_GCONF_SHAFT (4) // 0: Normal, 1: Invert
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#define FB_TMC_GCONF_DIAG0_ERROR (5) // 0: Disable, 1: Enable
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#define FB_TMC_GCONF_DIAG0_OTPW (6) // 0: Disable, 1: Enable
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#define FB_TMC_GCONF_DIAG0_STALL (7) // 0: Disable, 1: Enable
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#define FB_TMC_GCONF_DIAG1_STALL (8) // 0: Disable, 1: Enable
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#define FB_TMC_GCONF_DIAG1_INDEX (9) // 0: Disable, 1: Enable
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#define FB_TMC_GCONF_DIAG1_ONSTATE (10) // 0: Disable, 1: Enable
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#define FB_TMC_GCONF_DIAG1_STEPS_SKIPPED (11) // 0: Disable, 1: Enable
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#define FB_TMC_GCONF_DIAG0_INT_PUSHPULL (12) // 0: Open Collector, 1: Push Pull
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#define FB_TMC_GCONF_DIAG1_INT_PUSHPULL (13) // 0: Open Collector, 1: Push Pull
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#define FB_TMC_GCONF_SMALL_HYSTERESIS (14) // 0: 1/16, 1: 1/32
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#define FB_TMC_GCONF_STOP_ENABLE (15) // 0: Normal, 1: Emergency Stop
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#define FB_TMC_GCONF_DIRECT_MODE (16) // 0: Normal, 1: XDIRECT
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#define FB_TMC_GCONF_TEST_MODE (17) // 0: Normal, 1: Enable, Don't use!
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// GCONF MASKS
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// not required, all 1 bit
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// IHOLD_IRUN OFFSETS
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// for shifting incoming values to the right register position
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#define FB_TMC_IHOLD (0)
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#define FB_TMC_IRUN (8)
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#define FB_TMC_IHOLDDELAY (16)
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// IHOLD IRUN MASKS
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#define FB_TMC_IHOLD_MASK (0b11111UL)
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#define FB_TMC_IRUN_MASK (0b11111UL)
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#define FB_TMC_IHOLDDELAY_MASK (0b1111UL)
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// TPOWERDOWN
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// no offsets required
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#define FB_TMC_TPOWERDOWN_MASK (0b11111111UL)
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// TSTEP
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// no offsets required
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#define FB_TMC_TSTEP_MASK (0b11111111111111111111UL)
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// TPWMTHRS
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// no offsets required
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#define FB_TMC_TPWMTHRS_MASK (0b11111111111111111111UL)
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// TCOOLTHRS
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#define FB_TMC_TCOOLTHRS_MASK (0b11111111111111111111UL)
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// THIGH
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// no offsets required
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#define FB_TMC_THIGH_MASK (0b11111111111111111111UL)
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// XDIRECT OFFSETS
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// for shifting incoming values to the right register position
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#define FB_TMC_XDIRECT_COIL_A (0)
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#define FB_TMC_XDIRECT_COIL_B (16)
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// XDIRECT MASKS
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// mask the bits from the values we want to set
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#define FB_TMC_XDIRECT_MASK (0xFFFFFFFFUL)
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#define FB_TMC_XDIRECT_COIL_A_MASK (0xFFFFUL)
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#define FB_TMC_XDIRECT_COIL_B_MASK (0xFFFFUL)
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// no offsets required
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// needs no mask
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// VDCMIN
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// no offsets required
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#define FB_TMC_VDCMIN_MASK (0b11111111111111111111111UL)
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// MSLUT
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// no offsets required
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// needs no mask
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// MSLUTSEL
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// no offsets required
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// needs no mask
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// MSLUTSTART OFFSETS
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#define FB_TMC_MSLUTSTART_START_SIN (0)
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#define FB_TMC_MSLUTSTART_START_SIN90 (8)
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// MSLUTSTART MASKS
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#define FB_TMC_MSLUTSTART_MASK (0xFFFFUL)
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#define FB_TMC_MSLUTSTART_START_SIN_MASK (0xFF)
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#define FB_TMC_MSLUTSTART_START_SIN90_MASK (0xFF)
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// MSCNT
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// no offsets required
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#define FB_TMC_MSCNT_MASK (0b1111111111)
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// MSCURACT
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// no offsets required
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#define FB_TMC_MSCURACT_MASK (0b111111111111111111UL)
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// CHOPCONF MASKS
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// mask the bits from the values we want to set
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const uint32_t FB_TMC_CHOPCONF_MASKS[] = {
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0b1111UL, // 0 TOFF
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0b111UL, // 1
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0b11UL, // 2
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0b1UL, // 3
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0b111UL, // 4 HYSTERESIS_START
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0b11UL, // 5
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0b1UL, // 6
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0b0001UL, // 7 HYSTERESIS_LOW
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0b001UL, // 8
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0b01UL, // 9
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0b1UL, // 10
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0b1UL, // 11 FAST_DECAY_TIMING
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0b1UL, // 12 FAST_DECAY_MODE
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0b1UL, // 13 RANDOM_TOFF
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0b1UL, // 14 CHOPPER_MODE
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0b11UL, // 15 TBL
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0b1UL, // 16
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0b1UL, // 17 SENSE_CURRENT_SCALING
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0b1UL, // 18 HIGH_VELOCITY_STEPS
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0b1UL, // 19 HIGH_VELOCITY_CHOPPER
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0b1111UL, // 20 SYNC_PWM
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0b111UL, // 21
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0b11UL, // 22
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0b1UL, // 23
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0b1111UL, // 24 MRES
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0b111UL, // 25
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0b11UL, // 26
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0b1UL, // 27
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0b1UL, // 28 INTERPOLATE
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0b1UL, // 29 DOUBLE_EDGE_PULSES
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0b1UL, // 30 SHORT_PROTECTION
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0b1UL // 31
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};
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// CHOPCONF OFFSETS
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// for shifting incoming values to the right register position
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#define FB_TMC_CHOPCONF_DISS2G (30)
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#define FB_TMC_CHOPCONF_DEDGE (29)
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#define FB_TMC_CHOPCONF_INTPOL (28)
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#define FB_TMC_CHOPCONF_MRES (24)
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#define FB_TMC_CHOPCONF_SYNC (20)
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#define FB_TMC_CHOPCONF_VHIGHCHM (19)
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#define FB_TMC_CHOPCONF_VHIGHFS (18)
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#define FB_TMC_CHOPCONF_VSENSE (17)
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#define FB_TMC_CHOPCONF_TBL (15)
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#define FB_TMC_CHOPCONF_CHM (14)
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#define FB_TMC_CHOPCONF_RNDTF (13)
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#define FB_TMC_CHOPCONF_DISFDCC (12)
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#define FB_TMC_CHOPCONF_FD (11)
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#define FB_TMC_CHOPCONF_HEND (7)
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#define FB_TMC_CHOPCONF_HSTRT (4)
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#define FB_TMC_CHOPCONF_TOFF (0)
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// COOLCONF BIT OFFSETS
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// for shifting incoming values to the right register position
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#define FB_TMC_COOLCONF_SFILT (24)
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#define FB_TMC_COOLCONF_SGT (16)
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#define FB_TMC_COOLCONF_SEIMIN (15)
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#define FB_TMC_COOLCONF_SEDN (13)
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#define FB_TMC_COOLCONF_SEMAX (8)
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#define FB_TMC_COOLCONF_SEUP (5)
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#define FB_TMC_COOLCONF_SEMIN (0)
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// COOLCONF MASKS
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// mask the bits from the values we want to set
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const int FB_TMC_COOLCONF_MASKS[] = {
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0b1111UL, // 0 FB_TMC_COOLCONF_SEMIN
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0b111UL, // 1
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0b11UL, // 2
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0b1UL, // 3
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0b0UL, // 4
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0b11UL, // 5 FB_TMC_COOLCONF_SEUP
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0b1UL, // 6
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0b0UL, // 7
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0b1111UL, // 8 FB_TMC_COOLCONF_SEMAX
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0b111UL, // 9
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0b11UL, // 10
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0b1UL, // 11
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0b0UL, // 12
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0b11UL, // 13 FB_TMC_COOLCONF_SEDN
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0b1UL, // 14
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0b1UL, // 15 FB_TMC_COOLCONF_SEIMIN
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0b1111111UL, // 16 FB_TMC_COOLCONF_SGT
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0b111111UL, // 17
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0b11111UL, // 18
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0b1111UL, // 19
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0b111UL, // 20
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0b11UL, // 21
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0b1UL, // 22
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0b0UL, // 23
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0b1UL, // 24 FB_TMC_COOLCONF_SFILT
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};
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// DCCTRL OFFSETS
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// for shifting incoming values to the right register position
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#define FB_TMC_DCCTRL_DC_TIME (0)
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#define FB_TMC_DCCTRL_DC_SG (16)
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// DCCTRL MASKS
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// mask the bits from the values we want to set
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#define FB_TMC_DCCTRL_MASK (0b1111111111UL)
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#define FB_TMC_DCCTRL_DC_TIME_MASK (0b11111111UL)
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#define FB_TMC_DCCTRL_DC_SG_MASK (0b111111110000001111111111UL)
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// PWMCONF OFFSETS
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// for shifting incoming values to the right register position
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#define FB_TMC_PWMCONF_FREEWHEEL (20)
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#define FB_TMC_PWMCONF_PWM_SYMMETRIC (19)
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#define FB_TMC_PWMCONF_PWM_AUTOSCALE (18)
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#define FB_TMC_PWMCONF_PWM_FREQ (16)
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#define FB_TMC_PWMCONF_PWM_GRAD (8)
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#define FB_TMC_PWMCONF_PWM_AMPL (0)
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// PWMCONF MASKS
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// mask the bits from the values we want to set
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const int FB_TMC_PWMCONF_MASKS[] = {
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0b11111111UL, // 0 FB_TMC_PWMCONF_PWM_AMPL
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0b1111111UL, // 1
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0b111111UL, // 2
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0b11111UL, // 3
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0b1111UL, // 4
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0b111UL, // 5
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0b11UL, // 6
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0b1UL, // 7
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0b11111111UL, // 8 FB_TMC_PWMCONF_PWM_GRAD
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0b1111111UL, // 9
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0b111111UL, // 10
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0b11111UL, // 11
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0b1111UL, // 12
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0b111UL, // 13
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0b11UL, // 14
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0b1UL, // 15
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0b11UL, // 16 FB_TMC_PWMCONF_PWM_FREQ
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0b1UL, // 17
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0b1UL, // 18 FB_TMC_PWMCONF_PWM_AUTOSCALE
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0b1UL, // 19 FB_TMC_PWMCONF_PWM_SYMMETRIC
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0b11UL, // 20 FB_TMC_PWMCONF_FREEWHEEL
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0b1UL, // 21
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};
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// ENCM_CTRL MASK
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// mask the bits from the values we want to set
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#define FB_TMC_ENCM_CTRL_MASK (0b11);
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#endif // TMC2130_BASICS_REG_H
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