parent
5c3f3e44bc
commit
a9b7f3bdd8
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@ -26,7 +26,7 @@ extern ExitHandler do_exit;
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const size_t FRAME_WIDTH = 1928;
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const size_t FRAME_WIDTH = 1928;
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const size_t FRAME_HEIGHT = 1208;
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const size_t FRAME_HEIGHT = 1208;
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const size_t FRAME_STRIDE = 2416; // for 10 bit output
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const size_t FRAME_STRIDE = 2896; // for 12 bit output. 1928 * 12 / 8 + 4 (alignment)
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const int MIPI_SETTLE_CNT = 33; // Calculated by camera_freqs.py
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const int MIPI_SETTLE_CNT = 33; // Calculated by camera_freqs.py
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@ -471,10 +471,10 @@ void CameraState::config_isp(int io_mem_handle, int fence, int request_id, int b
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.h_init = 0x0,
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.h_init = 0x0,
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.v_init = 0x0,
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.v_init = 0x0,
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};
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};
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io_cfg[0].format = CAM_FORMAT_MIPI_RAW_10; // CAM_FORMAT_UBWC_TP10 for YUV
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io_cfg[0].format = CAM_FORMAT_MIPI_RAW_12; // CAM_FORMAT_UBWC_TP10 for YUV
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io_cfg[0].color_space = CAM_COLOR_SPACE_BASE; // CAM_COLOR_SPACE_BT601_FULL for YUV
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io_cfg[0].color_space = CAM_COLOR_SPACE_BASE; // CAM_COLOR_SPACE_BT601_FULL for YUV
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io_cfg[0].color_pattern = 0x5; // 0x0 for YUV
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io_cfg[0].color_pattern = 0x5; // 0x0 for YUV
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io_cfg[0].bpp = 0xa;
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io_cfg[0].bpp = 0xc;
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io_cfg[0].resource_type = CAM_ISP_IFE_OUT_RES_RDI_0; // CAM_ISP_IFE_OUT_RES_FULL for YUV
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io_cfg[0].resource_type = CAM_ISP_IFE_OUT_RES_RDI_0; // CAM_ISP_IFE_OUT_RES_FULL for YUV
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io_cfg[0].fence = fence;
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io_cfg[0].fence = fence;
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io_cfg[0].direction = CAM_BUF_OUTPUT;
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io_cfg[0].direction = CAM_BUF_OUTPUT;
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@ -615,9 +615,8 @@ void CameraState::camera_open() {
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.lane_cfg = 0x3210,
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.lane_cfg = 0x3210,
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.vc = 0x0,
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.vc = 0x0,
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// .dt = 0x2C; //CSI_RAW12
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.dt = 0x2C, // CSI_RAW12
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.dt = 0x2B, //CSI_RAW10
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.format = CAM_FORMAT_MIPI_RAW_12,
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.format = CAM_FORMAT_MIPI_RAW_10,
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.test_pattern = 0x2, // 0x3?
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.test_pattern = 0x2, // 0x3?
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.usage_type = 0x0,
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.usage_type = 0x0,
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@ -643,7 +642,7 @@ void CameraState::camera_open() {
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.num_out_res = 0x1,
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.num_out_res = 0x1,
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.data[0] = (struct cam_isp_out_port_info){
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.data[0] = (struct cam_isp_out_port_info){
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.res_type = CAM_ISP_IFE_OUT_RES_RDI_0,
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.res_type = CAM_ISP_IFE_OUT_RES_RDI_0,
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.format = CAM_FORMAT_MIPI_RAW_10,
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.format = CAM_FORMAT_MIPI_RAW_12,
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.width = FRAME_WIDTH,
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.width = FRAME_WIDTH,
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.height = FRAME_HEIGHT,
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.height = FRAME_HEIGHT,
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.comp_grp_id = 0x0, .split_point = 0x0, .secure_mode = 0x0,
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.comp_grp_id = 0x0, .split_point = 0x0, .secure_mode = 0x0,
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@ -40,12 +40,12 @@ half3 color_correct(half3 rgb) {
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}
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}
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half val_from_10(const uchar * source, int gx, int gy) {
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half val_from_10(const uchar * source, int gx, int gy) {
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// parse 10bit
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// parse 12bit
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int start = gy * FRAME_STRIDE + (5 * (gx / 4));
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int start = gy * FRAME_STRIDE + (3 * (gx / 2));
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int offset = gx % 4;
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int offset = gx % 2;
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uint major = (uint)source[start + offset] << 2;
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uint major = (uint)source[start + offset] << 4;
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uint minor = (source[start + 4] >> (2 * offset)) & 3;
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uint minor = (source[start + 2] >> (4 * offset)) & 0xf;
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half pv = (half)(major + minor);
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half pv = (half)((major + minor)/4);
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// normalize
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// normalize
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pv = max(0.0h, pv - black_level);
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pv = max(0.0h, pv - black_level);
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@ -9,7 +9,7 @@ struct i2c_random_wr_payload init_array_ar0231[] = {
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{0x302C, 0x0001}, // VT_SYS_CLK_DIV
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{0x302C, 0x0001}, // VT_SYS_CLK_DIV
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{0x302E, 0x0002}, // PRE_PLL_CLK_DIV
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{0x302E, 0x0002}, // PRE_PLL_CLK_DIV
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{0x3030, 0x0032}, // PLL_MULTIPLIER
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{0x3030, 0x0032}, // PLL_MULTIPLIER
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{0x3036, 0x000A}, // OP_WORD_CLK_DIV
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{0x3036, 0x000C}, // OP_WORD_CLK_DIV
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{0x3038, 0x0001}, // OP_SYS_CLK_DIV
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{0x3038, 0x0001}, // OP_SYS_CLK_DIV
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// FORMAT
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// FORMAT
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@ -46,11 +46,11 @@ struct i2c_random_wr_payload init_array_ar0231[] = {
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// Readout Settings
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// Readout Settings
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{0x31AE, 0x0204}, // SERIAL_FORMAT, 4-lane MIPI
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{0x31AE, 0x0204}, // SERIAL_FORMAT, 4-lane MIPI
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{0x31AC, 0x0C0A}, // DATA_FORMAT_BITS, 12 -> 10
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{0x31AC, 0x0C0C}, // DATA_FORMAT_BITS, 12 -> 12
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{0x3342, 0x122B}, // MIPI_F1_PDT_EDT
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{0x3342, 0x122C}, // MIPI_F1_PDT_EDT
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{0x3346, 0x122B}, // MIPI_F2_PDT_EDT
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{0x3346, 0x122C}, // MIPI_F2_PDT_EDT
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{0x334A, 0x122B}, // MIPI_F3_PDT_EDT
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{0x334A, 0x122C}, // MIPI_F3_PDT_EDT
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{0x334E, 0x122B}, // MIPI_F4_PDT_EDT
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{0x334E, 0x122C}, // MIPI_F4_PDT_EDT
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{0x3344, 0x0011}, // MIPI_F1_VDT_VC
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{0x3344, 0x0011}, // MIPI_F1_VDT_VC
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{0x3348, 0x0111}, // MIPI_F2_VDT_VC
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{0x3348, 0x0111}, // MIPI_F2_VDT_VC
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{0x334C, 0x0211}, // MIPI_F3_VDT_VC
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{0x334C, 0x0211}, // MIPI_F3_VDT_VC
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