204 lines
7.2 KiB
C
204 lines
7.2 KiB
C
#define FDCAN_MESSAGE_RAM_SIZE 0x2800UL
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#define FDCAN_START_ADDRESS 0x4000AC00UL
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#define FDCAN_OFFSET 3412UL // bytes for each FDCAN module
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#define FDCAN_OFFSET_W 853UL // words for each FDCAN module
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#define FDCAN_END_ADDRESS 0x4000D3FCUL // Message RAM has a width of 4 Bytes
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// With this settings we can go up to 5Mbit/s
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#define CAN_SYNC_JW 1U // 1 to 4
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#define CAN_PHASE_SEG1 6U // =(PROP_SEG + PHASE_SEG1) , 1 to 16
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#define CAN_PHASE_SEG2 1U // 1 to 8
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#define CAN_PCLK 80000U // Sourced from PLL1Q
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#define CAN_QUANTA (1U + CAN_PHASE_SEG1 + CAN_PHASE_SEG2)
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// Valid speeds in kbps and their prescalers:
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// 10=1000, 20=500, 50=200, 83.333=120, 100=100, 125=80, 250=40, 500=20, 1000=10, 2000=5, 5000=2
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#define can_speed_to_prescaler(x) (CAN_PCLK / CAN_QUANTA * 10U / (x))
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// RX FIFO 0
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#define FDCAN_RX_FIFO_0_EL_CNT 24UL
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#define FDCAN_RX_FIFO_0_HEAD_SIZE 8UL // bytes
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#define FDCAN_RX_FIFO_0_DATA_SIZE 64UL // bytes
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#define FDCAN_RX_FIFO_0_EL_SIZE (FDCAN_RX_FIFO_0_HEAD_SIZE + FDCAN_RX_FIFO_0_DATA_SIZE)
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#define FDCAN_RX_FIFO_0_EL_W_SIZE (FDCAN_RX_FIFO_0_EL_SIZE / 4UL)
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#define FDCAN_RX_FIFO_0_OFFSET 0UL
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// TX FIFO
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#define FDCAN_TX_FIFO_EL_CNT 16UL
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#define FDCAN_TX_FIFO_HEAD_SIZE 8UL // bytes
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#define FDCAN_TX_FIFO_DATA_SIZE 64UL // bytes
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#define FDCAN_TX_FIFO_EL_SIZE (FDCAN_TX_FIFO_HEAD_SIZE + FDCAN_TX_FIFO_DATA_SIZE)
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#define FDCAN_TX_FIFO_EL_W_SIZE (FDCAN_TX_FIFO_EL_SIZE / 4UL)
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#define FDCAN_TX_FIFO_OFFSET (FDCAN_RX_FIFO_0_OFFSET + (FDCAN_RX_FIFO_0_EL_CNT * FDCAN_RX_FIFO_0_EL_W_SIZE))
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#define CAN_NAME_FROM_CANIF(CAN_DEV) (((CAN_DEV)==FDCAN1) ? "FDCAN1" : (((CAN_DEV) == FDCAN2) ? "FDCAN2" : "FDCAN3"))
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#define CAN_NUM_FROM_CANIF(CAN_DEV) (((CAN_DEV)==FDCAN1) ? 0UL : (((CAN_DEV) == FDCAN2) ? 1UL : 2UL))
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void puts(const char *a);
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bool fdcan_request_init(FDCAN_GlobalTypeDef *CANx) {
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bool ret = true;
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// Exit from sleep mode
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CANx->CCCR &= ~(FDCAN_CCCR_CSR);
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while ((CANx->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA);
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// Request init
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uint32_t timeout_counter = 0U;
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CANx->CCCR |= FDCAN_CCCR_INIT;
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while ((CANx->CCCR & FDCAN_CCCR_INIT) == 0) {
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// Delay for about 1ms
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delay(10000);
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timeout_counter++;
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if (timeout_counter >= CAN_INIT_TIMEOUT_MS){
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ret = false;
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break;
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}
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}
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return ret;
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}
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bool fdcan_exit_init(FDCAN_GlobalTypeDef *CANx) {
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bool ret = true;
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CANx->CCCR &= ~(FDCAN_CCCR_INIT);
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uint32_t timeout_counter = 0U;
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while ((CANx->CCCR & FDCAN_CCCR_INIT) != 0) {
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// Delay for about 1ms
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delay(10000);
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timeout_counter++;
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if (timeout_counter >= CAN_INIT_TIMEOUT_MS) {
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ret = false;
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break;
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}
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}
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return ret;
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}
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bool llcan_set_speed(FDCAN_GlobalTypeDef *CANx, uint32_t speed, uint32_t data_speed, bool loopback, bool silent) {
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bool ret = fdcan_request_init(CANx);
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if (ret) {
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// Enable config change
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CANx->CCCR |= FDCAN_CCCR_CCE;
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//Reset operation mode to Normal
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CANx->CCCR &= ~(FDCAN_CCCR_TEST);
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CANx->TEST &= ~(FDCAN_TEST_LBCK);
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CANx->CCCR &= ~(FDCAN_CCCR_MON);
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CANx->CCCR &= ~(FDCAN_CCCR_ASM);
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// Set the nominal bit timing register
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CANx->NBTP = ((CAN_SYNC_JW-1U)<<FDCAN_NBTP_NSJW_Pos) | ((CAN_PHASE_SEG1-1U)<<FDCAN_NBTP_NTSEG1_Pos) | ((CAN_PHASE_SEG2-1U)<<FDCAN_NBTP_NTSEG2_Pos) | ((can_speed_to_prescaler(speed)-1U)<<FDCAN_NBTP_NBRP_Pos);
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// Set the data bit timing register
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CANx->DBTP = ((CAN_SYNC_JW-1U)<<FDCAN_DBTP_DSJW_Pos) | ((CAN_PHASE_SEG1-1U)<<FDCAN_DBTP_DTSEG1_Pos) | ((CAN_PHASE_SEG2-1U)<<FDCAN_DBTP_DTSEG2_Pos) | ((can_speed_to_prescaler(data_speed)-1U)<<FDCAN_DBTP_DBRP_Pos);
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// Silent loopback is known as internal loopback in the docs
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if (loopback) {
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CANx->CCCR |= FDCAN_CCCR_TEST;
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CANx->TEST |= FDCAN_TEST_LBCK;
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CANx->CCCR |= FDCAN_CCCR_MON;
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}
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// Silent is known as bus monitoring in the docs
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if (silent) {
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CANx->CCCR |= FDCAN_CCCR_MON;
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}
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ret = fdcan_exit_init(CANx);
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if (!ret) {
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puts(CAN_NAME_FROM_CANIF(CANx)); puts(" set_speed timed out! (2)\n");
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}
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} else {
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puts(CAN_NAME_FROM_CANIF(CANx)); puts(" set_speed timed out! (1)\n");
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}
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return ret;
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}
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bool llcan_init(FDCAN_GlobalTypeDef *CANx) {
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uint32_t can_number = CAN_NUM_FROM_CANIF(CANx);
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bool ret = fdcan_request_init(CANx);
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if (ret) {
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// Enable config change
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CANx->CCCR |= FDCAN_CCCR_CCE;
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// Enable automatic retransmission
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CANx->CCCR &= ~(FDCAN_CCCR_DAR);
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// Enable transmission pause feature
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CANx->CCCR |= FDCAN_CCCR_TXP;
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// Disable protocol exception handling
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CANx->CCCR |= FDCAN_CCCR_PXHD;
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// FD with BRS
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CANx->CCCR |= (FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE);
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// Set TX mode to FIFO
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CANx->TXBC &= ~(FDCAN_TXBC_TFQM);
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// Configure TX element data size
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CANx->TXESC |= 0x7U << FDCAN_TXESC_TBDS_Pos; // 64 bytes
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//Configure RX FIFO0 element data size
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CANx->RXESC |= 0x7U << FDCAN_RXESC_F0DS_Pos;
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// Disable filtering, accept all valid frames received
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CANx->XIDFC &= ~(FDCAN_XIDFC_LSE); // No extended filters
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CANx->SIDFC &= ~(FDCAN_SIDFC_LSS); // No standard filters
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CANx->GFC &= ~(FDCAN_GFC_RRFE); // Accept extended remote frames
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CANx->GFC &= ~(FDCAN_GFC_RRFS); // Accept standard remote frames
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CANx->GFC &= ~(FDCAN_GFC_ANFE); // Accept extended frames to FIFO 0
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CANx->GFC &= ~(FDCAN_GFC_ANFS); // Accept standard frames to FIFO 0
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uint32_t RxFIFO0SA = FDCAN_START_ADDRESS + (can_number * FDCAN_OFFSET);
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uint32_t TxFIFOSA = RxFIFO0SA + (FDCAN_RX_FIFO_0_EL_CNT * FDCAN_RX_FIFO_0_EL_SIZE);
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// RX FIFO 0
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CANx->RXF0C |= (FDCAN_RX_FIFO_0_OFFSET + (can_number * FDCAN_OFFSET_W)) << FDCAN_RXF0C_F0SA_Pos;
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CANx->RXF0C |= FDCAN_RX_FIFO_0_EL_CNT << FDCAN_RXF0C_F0S_Pos;
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// RX FIFO 0 switch to non-blocking (overwrite) mode
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CANx->RXF0C |= FDCAN_RXF0C_F0OM;
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// TX FIFO (mode set earlier)
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CANx->TXBC |= (FDCAN_TX_FIFO_OFFSET + (can_number * FDCAN_OFFSET_W)) << FDCAN_TXBC_TBSA_Pos;
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CANx->TXBC |= FDCAN_TX_FIFO_EL_CNT << FDCAN_TXBC_TFQS_Pos;
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// Flush allocated RAM
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uint32_t EndAddress = TxFIFOSA + (FDCAN_TX_FIFO_EL_CNT * FDCAN_TX_FIFO_EL_SIZE);
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for (uint32_t RAMcounter = RxFIFO0SA; RAMcounter < EndAddress; RAMcounter += 4U) {
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*(uint32_t *)(RAMcounter) = 0x00000000;
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}
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// Enable both interrupts for each module
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CANx->ILE = (FDCAN_ILE_EINT0 | FDCAN_ILE_EINT1);
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CANx->IE &= 0x0U; // Reset all interrupts
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// Messages for INT0
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CANx->IE |= FDCAN_IE_RF0NE; // Rx FIFO 0 new message
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// Messages for INT1 (Only TFE works??)
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CANx->ILS |= FDCAN_ILS_TFEL;
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CANx->IE |= FDCAN_IE_TFEE; // Tx FIFO empty
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ret = fdcan_exit_init(CANx);
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if(!ret) {
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puts(CAN_NAME_FROM_CANIF(CANx)); puts(" llcan_init timed out (2)!\n");
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}
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if (CANx == FDCAN1) {
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NVIC_EnableIRQ(FDCAN1_IT0_IRQn);
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NVIC_EnableIRQ(FDCAN1_IT1_IRQn);
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} else if (CANx == FDCAN2) {
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NVIC_EnableIRQ(FDCAN2_IT0_IRQn);
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NVIC_EnableIRQ(FDCAN2_IT1_IRQn);
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} else if (CANx == FDCAN3) {
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NVIC_EnableIRQ(FDCAN3_IT0_IRQn);
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NVIC_EnableIRQ(FDCAN3_IT1_IRQn);
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} else {
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puts("Invalid CAN: initialization failed\n");
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}
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} else {
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puts(CAN_NAME_FROM_CANIF(CANx)); puts(" llcan_init timed out (1)!\n");
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}
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return ret;
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}
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void llcan_clear_send(FDCAN_GlobalTypeDef *CANx) {
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// From H7 datasheet: Transmit cancellation is not intended for Tx FIFO operation.
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UNUSED(CANx);
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}
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