670 lines
15 KiB
Plaintext
670 lines
15 KiB
Plaintext
{
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"board": {
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"design_settings": {
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"defaults": {
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"board_outline_line_width": 0.19999999999999998,
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"copper_line_width": 0.19999999999999998,
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"copper_text_italic": false,
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"copper_text_size_h": 0.8999999999999999,
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"copper_text_size_v": 0.8999999999999999,
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"copper_text_thickness": 0.3,
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"copper_text_upright": false,
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"courtyard_line_width": 0.049999999999999996,
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"dimension_precision": 4,
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"dimension_units": 3,
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"dimensions": {
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"arrow_length": 1270000,
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"extension_offset": 500000,
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"keep_text_aligned": true,
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"suppress_zeroes": false,
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"text_position": 0,
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"units_format": 1
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},
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"fab_line_width": 0.09999999999999999,
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"fab_text_italic": false,
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"fab_text_size_h": 1.0,
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"fab_text_size_v": 1.0,
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"fab_text_thickness": 0.15,
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"fab_text_upright": false,
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"other_line_width": 0.09999999999999999,
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"other_text_italic": false,
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"other_text_size_h": 1.0,
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"other_text_size_v": 1.0,
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"other_text_thickness": 0.15,
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"other_text_upright": false,
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"pads": {
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"drill": 1.8,
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"height": 2.7,
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"width": 2.7
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},
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"silk_line_width": 0.15,
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"silk_text_italic": false,
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"silk_text_size_h": 0.8999999999999999,
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"silk_text_size_v": 0.8999999999999999,
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"silk_text_thickness": 0.127,
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"silk_text_upright": false,
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"zones": {
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"45_degree_only": true,
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"min_clearance": 0.16499999999999998
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}
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},
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"diff_pair_dimensions": [],
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"drc_exclusions": [],
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"meta": {
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"filename": "board_design_settings.json",
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"version": 2
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},
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"rule_severities": {
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"annular_width": "error",
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"clearance": "error",
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"copper_edge_clearance": "error",
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"courtyards_overlap": "error",
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"diff_pair_gap_out_of_range": "error",
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"diff_pair_uncoupled_length_too_long": "error",
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"drill_out_of_range": "error",
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"duplicate_footprints": "warning",
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"extra_footprint": "warning",
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"footprint_type_mismatch": "error",
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"hole_clearance": "error",
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"hole_near_hole": "error",
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"invalid_outline": "error",
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"item_on_disabled_layer": "error",
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"items_not_allowed": "error",
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"length_out_of_range": "error",
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"malformed_courtyard": "error",
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"microvia_drill_out_of_range": "error",
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"missing_courtyard": "ignore",
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"missing_footprint": "warning",
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"net_conflict": "warning",
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"npth_inside_courtyard": "ignore",
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"padstack": "error",
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"pth_inside_courtyard": "ignore",
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"shorting_items": "error",
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"silk_over_copper": "warning",
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"silk_overlap": "warning",
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"skew_out_of_range": "error",
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"through_hole_pad_without_hole": "error",
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"too_many_vias": "error",
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"track_dangling": "warning",
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"track_width": "error",
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"tracks_crossing": "error",
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"unconnected_items": "error",
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"unresolved_variable": "error",
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"via_dangling": "warning",
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"zone_has_empty_net": "error",
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"zones_intersect": "error"
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},
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"rules": {
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"allow_blind_buried_vias": false,
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"allow_microvias": false,
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"max_error": 0.005,
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"min_clearance": 0.0,
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"min_copper_edge_clearance": 0.075,
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"min_hole_clearance": 0.25,
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"min_hole_to_hole": 0.25,
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"min_microvia_diameter": 0.39999999999999997,
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"min_microvia_drill": 0.19999999999999998,
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"min_silk_clearance": 0.0,
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"min_through_hole_diameter": 0.19999999999999998,
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"min_track_width": 0.127,
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"min_via_annular_width": 0.049999999999999996,
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"min_via_diameter": 0.39999999999999997,
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"use_height_for_length_calcs": true
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},
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"track_widths": [
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0.0,
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0.127,
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0.13,
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0.15,
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0.165,
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0.2,
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0.25,
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0.4,
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0.5
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],
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"via_dimensions": [
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{
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"diameter": 0.0,
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"drill": 0.0
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},
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{
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"diameter": 0.4,
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"drill": 0.2
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},
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{
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"diameter": 0.5,
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"drill": 0.25
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}
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],
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"zones_allow_external_fillets": false,
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"zones_use_no_outline": true
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},
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"layer_presets": []
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},
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"boards": [],
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"cvpcb": {
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"equivalence_files": []
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},
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"erc": {
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"erc_exclusions": [],
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"meta": {
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"version": 0
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},
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"pin_map": [
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[
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],
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"rule_severities": {
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"bus_definition_conflict": "error",
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"bus_entry_needed": "error",
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"bus_label_syntax": "error",
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"bus_to_bus_conflict": "error",
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"bus_to_net_conflict": "error",
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"different_unit_footprint": "error",
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"different_unit_net": "error",
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"duplicate_reference": "error",
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"duplicate_sheet_names": "error",
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"extra_units": "error",
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"global_label_dangling": "warning",
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"hier_label_mismatch": "error",
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"label_dangling": "error",
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"lib_symbol_issues": "warning",
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"multiple_net_names": "warning",
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"net_not_bus_member": "warning",
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"no_connect_connected": "warning",
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"no_connect_dangling": "warning",
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"pin_not_connected": "error",
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"pin_not_driven": "error",
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"pin_to_pin": "warning",
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"power_pin_not_driven": "error",
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"similar_labels": "warning",
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"unannotated": "error",
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"unit_value_mismatch": "error",
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"unresolved_variable": "error",
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"wire_dangling": "error"
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}
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},
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"libraries": {
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"pinned_footprint_libs": [],
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"pinned_symbol_libs": []
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},
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"meta": {
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"filename": "Scopefun_v2.kicad_pro",
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"version": 1
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},
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"net_settings": {
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"classes": [
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{
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"bus_width": 12.0,
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"clearance": 0.12699,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.4,
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"microvia_drill": 0.2,
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"name": "Default",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.2,
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"via_diameter": 0.5,
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"via_drill": 0.25,
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"wire_width": 6.0
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},
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{
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"bus_width": 12.0,
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"clearance": 0.12699,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.4,
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"microvia_drill": 0.2,
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"name": "Power",
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"nets": [
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"+1.48V",
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"+1V0",
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"+1V2",
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"+1V5",
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"+1V8",
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"+1V8_VA",
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"+2.88V",
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"+3.3V_PD",
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"+3V3",
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"+3V3_VA",
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"+VCC_DIG",
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"+VCC_USB",
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"+VCC_USB_P",
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"-2.88V",
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"-5V",
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"-Va",
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"GND",
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"Va"
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],
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.5,
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"via_diameter": 0.5,
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"via_drill": 0.25,
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"wire_width": 6.0
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},
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{
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"bus_width": 12.0,
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"clearance": 0.12699,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.4,
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"microvia_drill": 0.2,
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"name": "Small_VIA",
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"nets": [
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"/ADC/CH1+",
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"/ADC/CH1-",
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"/ADC/CH2+",
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"/ADC/CH2-",
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"/ADC/CLK_OUT+",
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"/ADC/CLK_OUT-",
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"/ADC/IN+",
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"/ADC/IN-",
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"/ADC/OUT1+",
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"/ADC/OUT1-",
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"/ADC/OUT2+",
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"/ADC/OUT2-",
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"/DDR3 SDRAM/DDR3_A0_",
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"/DDR3 SDRAM/DDR3_A10_",
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"/DDR3 SDRAM/DDR3_A11_",
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"/DDR3 SDRAM/DDR3_A12_",
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"/DDR3 SDRAM/DDR3_A1_",
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"/DDR3 SDRAM/DDR3_A2_",
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"/DDR3 SDRAM/DDR3_A3_",
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"/DDR3 SDRAM/DDR3_A4_",
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"/DDR3 SDRAM/DDR3_A5_",
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"/DDR3 SDRAM/DDR3_A6_",
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"/DDR3 SDRAM/DDR3_A7_",
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"/DDR3 SDRAM/DDR3_A8_",
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"/DDR3 SDRAM/DDR3_A9_",
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"/DDR3 SDRAM/DDR3_BA0_",
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"/DDR3 SDRAM/DDR3_BA1_",
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"/DDR3 SDRAM/DDR3_BA2_",
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"/DDR3 SDRAM/DDR3_CAS#_",
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"/DDR3 SDRAM/DDR3_CKE_",
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"/DDR3 SDRAM/DDR3_ODT_",
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"/DDR3 SDRAM/DDR3_RAS#_",
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"/DDR3 SDRAM/DDR3_WE#_",
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"/DDR3 SDRAM/VFREF",
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"/GAIN, OFFSET/AN_TRIG",
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"/USB FX3/TX+",
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"/USB FX3/TX-",
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"AN_TRIG_N",
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"AN_TRIG_P",
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"CH1_ADC_CLK_IN+",
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"CH1_ADC_CLK_IN-",
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"CH2_ADC_CLK_IN+",
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"CH2_ADC_CLK_IN-",
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"CLK_ADC_N",
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"CLK_ADC_P",
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"D+",
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"D-",
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"DDR3_A0",
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"DDR3_A1",
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"DDR3_A10",
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"DDR3_A11",
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"DDR3_A12",
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"DDR3_A2",
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"DDR3_A3",
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"DDR3_A4",
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"DDR3_A5",
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"DDR3_A6",
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"DDR3_A7",
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"DDR3_A8",
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"DDR3_A9",
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"DDR3_BA0",
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"DDR3_BA1",
|
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"DDR3_BA2",
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"DDR3_CAS#",
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"DDR3_CKE",
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"DDR3_CK_N",
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"DDR3_CK_P",
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"DDR3_DQ0",
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"DDR3_DQ1",
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"DDR3_DQ10",
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"DDR3_DQ11",
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"DDR3_DQ12",
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"DDR3_DQ13",
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"DDR3_DQ14",
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"DDR3_DQ15",
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"DDR3_DQ2",
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"DDR3_DQ3",
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"DDR3_DQ4",
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"DDR3_DQ5",
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"DDR3_DQ6",
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"DDR3_DQ7",
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"DDR3_DQ8",
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"DDR3_DQ9",
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"DDR3_DQS0_N",
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"DDR3_DQS0_P",
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"DDR3_DQS1_N",
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"DDR3_DQS1_P",
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"DDR3_ODT",
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"DDR3_RAS#",
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"DDR3_RESET#",
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"DDR3_WE#",
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"U3RX+",
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|
"U3RX-",
|
|
"U3TX+",
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|
"U3TX-",
|
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"dataA0_N",
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|
"dataA0_P",
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"dataA1_N",
|
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"dataA1_P",
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"dataA2_N",
|
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"dataA2_P",
|
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"dataA3_N",
|
|
"dataA3_P",
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"dataA4_N",
|
|
"dataA4_P",
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"dataB0_N",
|
|
"dataB0_P",
|
|
"dataB1_N",
|
|
"dataB1_P",
|
|
"dataB2_N",
|
|
"dataB2_P",
|
|
"dataB3_N",
|
|
"dataB3_P",
|
|
"dataB4_N",
|
|
"dataB4_P"
|
|
],
|
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
|
"track_width": 0.127,
|
|
"via_diameter": 0.45,
|
|
"via_drill": 0.2,
|
|
"wire_width": 6.0
|
|
}
|
|
],
|
|
"meta": {
|
|
"version": 2
|
|
},
|
|
"net_colors": null
|
|
},
|
|
"pcbnew": {
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|
"last_paths": {
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