2022-03-16 12:03:01 -06:00
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2022-03-22 03:19:58 -06:00
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2022-04-04 06:21:31 -06:00
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2022-03-29 08:08:21 -06:00
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2022-04-04 06:21:31 -06:00
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2022-04-03 03:52:35 -06:00
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2022-03-22 03:19:58 -06:00
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2022-04-03 03:52:35 -06:00
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2022-04-03 03:52:35 -06:00
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2022-03-22 03:19:58 -06:00
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2022-04-03 03:52:35 -06:00
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2022-03-16 12:03:01 -06:00
2022-04-03 03:52:35 -06:00
(text "If no SerDes channels\nare used, connect VCCAx\nto VCC. TODO: Check\nVCCAUXAx, if it is needed."
(at 242.57 31.75 0)
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 03ae3431-170e-46f8-9ee3-b4a9423602b1)
)
(text "VCCAUX: Auxiliary power supply pin. \nThis dedicated pin powers the differential\nand (SSTL)referenced input buffers. \nBank VCCAUX is also used to power the \npush-pull output pre-driver sections.\n(Pg 6 sysio): \"Some of the ratioed buffers\n are powered by VCCAUX\".\n(Pg 6 of sysio): \"VCCAUX (2.5 V), \nsupports hysteresis, \nand is used for 3.3 V and 2.5 V signaling.\" "
(at 69.85 259.08 0)
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 052d2162-5ecf-451c-8821-82e7b7c4e326)
2022-03-22 03:19:58 -06:00
)
2022-04-03 03:52:35 -06:00
(text "Current limit: 500mA" (at 20.32 43.18 0)
2022-03-29 09:54:52 -06:00
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 11c8c401-58ca-4581-b6c6-8b42a8ac5732)
)
2022-04-03 03:52:35 -06:00
(text "RX Link\n- I/Q Driver (AT86RF215 OUTPUT)\n- I/Q Receiver (FPGA INPUT)"
(at 10.16 246.38 0)
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 1cf09907-a2f0-41f6-8bb6-49240c116e56)
)
2022-04-04 07:50:18 -06:00
(text "~{INITN} (lights) goes low:\nthis indicates an error\nwith the configuration\nprocess. \nCheck sysCONFIG TN."
(at 184.15 92.71 0)
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 1fc7b0bc-c75a-4f5c-9849-13ba805f1b83)
)
2022-04-04 05:01:09 -06:00
(text "FPGA TRX" (at 71.12 140.97 90)
2022-04-03 03:52:35 -06:00
(effects (font (size 3.4036 3.4036) (thickness 0.6807) bold) (justify left bottom))
(uuid 2bec34f5-8f16-4dda-ae07-a54c3fb30eec)
)
(text "For unused banks, it is recommended to set VCCIO to 0V to minimize power and hold the bank in hot socket."
2022-04-04 06:21:31 -06:00
(at 157.48 21.59 0)
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 3a799149-6248-4b90-afdf-11275d8246f3)
)
(text "Each sysI/O\npad pair will support programmable on/off differential input termination of 100 Ω."
(at 121.92 242.57 0)
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 418e052a-4bd5-4f88-8135-0526cd1f37aa)
)
2022-04-04 07:50:18 -06:00
(text "Alternative: W25Q32JVSFIQ" (at 153.67 92.71 0)
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 48e62fd4-ea15-4c3f-81bd-76444d919ec3)
)
(text "CFG[2:0] = 010\nBoot from SPI Flash.\nCheck sysCONFIG TN."
(at 234.95 92.71 0)
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 642761d4-6b2a-47b1-bd0d-edaa6239ed5f)
)
2022-04-03 03:52:35 -06:00
(text "https://mindchasers.com/dev/pi-lattice-ecp5" (at 69.85 237.49 0)
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 6f73eb90-c978-4dbe-b223-3c8bd8144845)
)
(text "FPGA DEBUG/SPI" (at 121.92 154.94 90)
(effects (font (size 3.4036 3.4036) (thickness 0.6807) bold) (justify left bottom))
(uuid 8ada0eaa-3244-4c1e-893a-788f9dbf683f)
)
(text "PIO A and B are grouped as a pair, and PIO C and D are group as a pair. Each pair\nsupports true LVDS differential input buffer. Only PIO A and B pair supports true\nLVDS differential output buffer.\nEach A/B and C/D pair supports programmable on/off differential input\ntermination of 100 Ω."
(at 10.16 229.87 0)
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 92f6f638-55af-481a-b7ad-667d55b168c7)
)
(text "FPGA POWER" (at 281.94 60.96 90)
(effects (font (size 3.4036 3.4036) (thickness 0.6807) bold) (justify left bottom))
(uuid 9bf13e1e-4967-4c03-8620-f215ef5e2862)
)
(text "In addition the VCCIO supply, every bank also has an auxiliary global supply called VCCAUX. The bank VCCAUX supply is\nused to power the differential and referenced (SSTL) input buffer. Bank VCCAUX is also used to power the push-pull\noutput pre-driver sections"
(at 121.92 248.92 0)
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid cc62948f-f41e-4d38-8519-869e96c69cc6)
)
(text "A dedicated PCLK clock pin must always be used to route an external\nclock source to FPGA logic and I/O."
(at 10.16 217.17 0)
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid dcf10d7c-f7f9-4115-8ffa-bcd1f05f5786)
)
2022-04-04 07:50:18 -06:00
(text "FPGA CONFIGURATION" (at 281.94 147.32 90)
2022-04-03 03:52:35 -06:00
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(uuid e2416b2e-f191-40db-a0a3-64649bc9f155)
)
(text "https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02032-1-3-ECP5-ECP5G-sysIO-Usage-Guide.ashx?document_id=50464"
(at 121.92 237.49 0)
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid f2a25096-3564-4916-8c2e-b67098c44353)
2022-03-16 12:03:01 -06:00
)
2022-04-04 07:50:18 -06:00
(text "DONE (lights) goes High:\nthis indicates that FPGA\nenters user mode.\nCheck sysCONFIG TN."
(at 184.15 124.46 0)
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid f7609145-7680-487c-b45e-73108a33c279)
)
2022-04-03 03:52:35 -06:00
(text "TX Link\n- I/Q Receiver (AT86RF215 INPUT)\n- I/Q Driver (FPGA OUTPUT, A and B pair)"
(at 10.16 238.76 0)
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid f980636c-796b-47ce-8d2e-4767f413d5c9)
2022-03-16 12:03:01 -06:00
)
2022-04-04 07:50:18 -06:00
(label "CFG_IO2" (at 255.27 129.54 180)
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid 1fa05512-5fd6-4833-94af-64f9f1185217)
)
2022-04-03 03:52:35 -06:00
(label "1V1" (at 186.69 39.37 0)
(effects (font (size 1.27 1.27)) (justify left bottom))
2022-03-16 12:03:01 -06:00
(uuid 209ffad0-e58e-434a-a521-15eb5b900a94)
)
2022-04-04 07:50:18 -06:00
(label "{CFG_IO0 CFG_IO1 CFG_IO2 CFG_IO3 CFG_CLK ~{CFG_CS}}"
(at 132.08 139.7 0)
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 3375ec27-59b9-4b44-abd5-17835209557d)
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2022-04-03 03:52:35 -06:00
(label "3V3_FPGA" (at 266.7 71.12 180)
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid 34837dc0-7884-4051-85c3-ec1bd04993d3)
)
2022-04-04 07:50:18 -06:00
(label "CFG_CLK" (at 255.27 99.06 180)
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid 39debd70-bd18-4adf-b74f-e76a8ba24046)
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(label "~{CFG_CS}" (at 255.27 142.24 180)
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid 44dce111-a7fa-4c56-a8ab-6d3d01d7d8bc)
)
2022-04-03 03:52:35 -06:00
(label "2V5" (at 125.73 39.37 0)
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 47f7a18b-1c4a-4d24-96ac-ce5eaefbd0c0)
)
(label "2V5" (at 186.69 52.07 0)
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 507bdd15-2188-48bd-9ac4-6b096b935633)
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2022-04-04 07:50:18 -06:00
(label "CFG_CLK" (at 138.43 102.87 180)
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid 520b1415-9245-4b93-ba6b-5bd118f3c7bc)
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(label "3V3_FPGA" (at 152.4 71.12 180)
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid 52fb2912-f6f4-474f-9f7f-4eaf8b3b0115)
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2022-04-03 03:52:35 -06:00
(label "3V3_FPGA" (at 77.47 39.37 0)
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 581ff6ac-175c-45d8-a287-86336ac05602)
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(label "2V5" (at 237.49 52.07 180)
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid 5cb72530-d1da-447a-bddc-c4c0e752733d)
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2022-04-04 07:50:18 -06:00
(label "CFG_IO3" (at 138.43 110.49 180)
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid 5f9c17fb-517a-4a26-b1c7-9cc06f8af2b4)
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(label "CFG_IO1" (at 166.37 100.33 0)
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 7044e974-913a-4f7f-a98b-7257da0fa296)
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(label "CFG_IO1" (at 255.27 132.08 180)
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid 869debe2-c652-4c04-bf1d-1614b50ee3ae)
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2022-04-03 03:52:35 -06:00
(label "FPGA_VCC_PG" (at 160.02 44.45 0)
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 9689fe9a-43aa-4724-a38d-1f67fbb229b9)
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2022-04-04 07:50:18 -06:00
(label "3V3_FPGA" (at 107.95 71.12 180)
(effects (font (size 1.27 1.27)) (justify right bottom))
2022-03-22 03:19:58 -06:00
(uuid 9d5e7326-5602-45d9-bc0c-50e49c008da2)
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2022-04-04 07:50:18 -06:00
(label "CFG_IO3" (at 255.27 127 180)
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid a0ea42a7-261d-4e76-80ee-43f51a2dcb92)
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(label "3V3_FPGA" (at 234.95 71.12 180)
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid a7813d72-3946-4dd7-ab00-0dfe02570c66)
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(label "CFG_IO0" (at 255.27 134.62 180)
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid b1c0787b-4105-489c-ab15-a5a33a17a9a9)
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2022-04-04 05:01:09 -06:00
(label "DEBUG_CLK_IN" (at 95.25 153.67 180)
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid bab9f37e-b9aa-434d-ae21-8877a4b4669c)
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(label "1V1" (at 237.49 39.37 180)
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid bfd170d0-fc4a-4cb3-8417-d57aa9cd0377)
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2022-04-04 06:21:31 -06:00
(label "3V3_FPGA" (at 208.28 71.12 180)
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid c2d5a01e-a1f8-4e60-8db5-ca13676e1893)
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2022-04-03 03:52:35 -06:00
(label "FPGA_FAULT" (at 62.23 49.53 270)
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(uuid c4469504-3069-45ad-9da7-61160b1d99e4)
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2022-04-04 07:50:18 -06:00
(label "~{CFG_CS}" (at 138.43 105.41 180)
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(uuid cb122e25-34a1-46df-8607-a2d613de228d)
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2022-04-03 03:52:35 -06:00
(label "2V5" (at 55.88 66.04 0)
2022-03-16 12:03:01 -06:00
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid e2096c45-512e-432a-a387-88c04cb2cb97)
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2022-04-04 07:50:18 -06:00
(label "CFG_IO2" (at 138.43 107.95 180)
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid f1a4cfd4-09cc-4c7f-8893-4f404a317073)
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(label "CFG_IO0" (at 138.43 100.33 180)
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid fa3cab35-4a7b-468e-8444-535770e3eecf)
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2022-04-04 05:01:09 -06:00
(label "3V3_FPGA" (at 82.55 163.83 180)
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid fdf81741-7522-44ac-bd1a-9663251e9d45)
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2022-03-16 12:03:01 -06:00
2022-04-03 03:52:35 -06:00
(global_label "3V3" (shape input) (at 46.99 21.59 180) (fields_autoplaced)
(effects (font (size 1.27 1.27)) (justify right))
2022-03-22 03:19:58 -06:00
(uuid 02910490-7310-49f9-a0ad-041711e45745)
2022-04-03 03:52:35 -06:00
(property "Intersheet References" "${INTERSHEET_REFS}" (id 0) (at 41.0693 21.6694 0)
(effects (font (size 1.27 1.27)) (justify right) hide)
2022-03-22 03:19:58 -06:00
)
)
2022-04-03 03:52:35 -06:00
(global_label "3V3" (shape input) (at 69.85 46.99 0) (fields_autoplaced)
2022-03-22 03:19:58 -06:00
(effects (font (size 1.27 1.27)) (justify left))
(uuid 227e8405-1e6f-4ec9-87a7-0a40aee73ead)
2022-04-03 03:52:35 -06:00
(property "Intersheet References" "${INTERSHEET_REFS}" (id 0) (at 75.7707 47.0694 0)
2022-03-22 03:19:58 -06:00
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2022-03-16 12:03:01 -06:00
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)
2022-04-04 05:01:09 -06:00
(hierarchical_label "SPI_MISO" (shape input) (at 95.25 120.65 180)
2022-04-03 03:52:35 -06:00
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2022-03-16 12:03:01 -06:00
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2022-04-04 05:01:09 -06:00
(hierarchical_label "SPI_MOSI" (shape input) (at 95.25 123.19 180)
2022-04-03 03:52:35 -06:00
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2022-03-16 12:03:01 -06:00
(uuid 0921c614-3aba-4814-a792-3e77da4d559a)
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2022-04-04 05:01:09 -06:00
(hierarchical_label "RXDATAP" (shape input) (at 26.67 148.59 180)
2022-04-03 03:52:35 -06:00
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2022-03-16 12:03:01 -06:00
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2022-04-04 05:01:09 -06:00
(hierarchical_label "FPGA_IO0" (shape input) (at 95.25 148.59 180)
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
2022-03-16 12:03:01 -06:00
(uuid 2b9eea51-7036-44d5-84ce-6c3adc278715)
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2022-04-04 06:21:31 -06:00
(hierarchical_label "FPGA_INIT" (shape input) (at 198.12 109.22 180)
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