Clean up the FPGA schematic from comments

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
merge-requests/18/head
Agis Zisimatos 2022-04-05 17:29:00 +03:00
parent bdd3c06adf
commit 94313541b0
1 changed files with 38 additions and 65 deletions

View File

@ -4409,99 +4409,72 @@
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(text "If no SerDes channels\nare used, connect VCCAx\nto VCC. TODO: Check\nVCCAUXAx, if it is needed."
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(text "VCCAUX: Auxiliary power supply pin. \nThis dedicated pin powers the differential\nand (SSTL)referenced input buffers. \nBank VCCAUX is also used to power the \npush-pull output pre-driver sections.\n(Pg 6 sysio): \"Some of the ratioed buffers\n are powered by VCCAUX\".\n(Pg 6 of sysio): \"VCCAUX (2.5 V), \nsupports hysteresis, \nand is used for 3.3 V and 2.5 V signaling.\" "
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(text "Current limit: 500mA" (at 20.32 36.83 0)
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(text "RX Link\n- I/Q Driver (AT86RF215 OUTPUT)\n- I/Q Receiver (FPGA INPUT)"
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(text "~{INITN} (lights) goes low:\nthis indicates an error\nwith the configuration\nprocess. \nCheck sysCONFIG TN."
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(text "* Active read current with QSPI\nat 133MHz is 27mA(max).\n* Power-down and standby current\nis 50uA and 15uA(max)"
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(text "FPGA TRX" (at 67.31 147.32 90)
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(text "For unused banks, it is recommended to set VCCIO to 0V to minimize power and hold the bank in hot socket."
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(text "Each sysI/O\npad pair will support programmable on/off differential input termination of 100 Ω."
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(text "Alternative: W25Q32JVSFIQ" (at 157.48 116.84 0)
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(text "Quiescent current: 30uA" (at 128.27 22.86 0)
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(text "Current Consumption:\nON state (IQ): 40 uA (typ)\nOFF state (ISD): 0.2 uA (typ)"
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(text "CFG[2:0] = 010\nBoot from SPI Flash.\nCheck sysCONFIG TN."
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(text "https://mindchasers.com/dev/pi-lattice-ecp5" (at 69.85 237.49 0)
(text "Quiescent current: 38uA" (at 90.17 22.86 0)
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(text "Current Consumption: 3.8mA" (at 92.71 193.04 0)
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(text "FPGA DEBUG/SPI" (at 130.81 154.94 90)
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(text "PIO A and B are grouped as a pair, and PIO C and D are group as a pair. Each pair\nsupports true LVDS differential input buffer. Only PIO A and B pair supports true\nLVDS differential output buffer.\nEach A/B and C/D pair supports programmable on/off differential input\ntermination of 100 Ω."
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(text "FPGA POWER" (at 281.94 62.23 90)
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(text "In addition the VCCIO supply, every bank also has an auxiliary global supply called VCCAUX. The bank VCCAUX supply is\nused to power the differential and referenced (SSTL) input buffer. Bank VCCAUX is also used to power the push-pull\noutput pre-driver sections"
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(text "* VCCAUX: 14mA\n* VCC: 120mA, peak 320mA\n* VCCIO: 5mA, peak 100mA "
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(text "A dedicated PCLK clock pin must always be used to route an external\nclock source to FPGA logic and I/O."
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(text "FPGA CONFIGURATION" (at 281.94 149.86 90)
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(text "https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02032-1-3-ECP5-ECP5G-sysIO-Usage-Guide.ashx?document_id=50464"
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(text "DONE (lights) goes High:\nthis indicates that FPGA\nenters user mode.\nCheck sysCONFIG TN."
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(text "TX Link\n- I/Q Receiver (AT86RF215 INPUT)\n- I/Q Driver (FPGA OUTPUT, A and B pair)"
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