spacecruft
/
sidloc-schematic
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Fix clock-in pins 

Add them in clock compatible pins for PLL.

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
merge-requests/32/head
Agis Zisimatos 2022-04-30 11:28:11 +03:00
parent 9d9a499b54
commit b07c5fff98
1 changed files with 10 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
fpga.kicad_sch
View File

@ -2657,7 +2657,6 @@
)
)
(junction (at 302.26 29.21) (diameter 0) (color 0 0 0 0)
(uuid 015d8a49-10ae-4e19-9e70-b72c1af03708)
)
@ -3011,6 +3010,7 @@
(no_connect (at 372.11 151.13) (uuid 3d444eaa-2910-41fd-82a5-3c7378a235eb))
(no_connect (at 43.18 158.75) (uuid 3edb3167-e45b-49a4-a46e-0c3b66c8794c))
(no_connect (at 290.83 208.28) (uuid 44d1208f-3dab-4b1f-a881-04d6516bd03a))
(no_connect (at 109.22 204.47) (uuid 455a9825-82bc-46b0-baf3-83bd68bc3f1a))
(no_connect (at 43.18 168.91) (uuid 469a0a3e-9e33-4569-a802-6a64c4500215))
(no_connect (at 372.11 196.85) (uuid 46a55358-869e-448a-9422-f86b68b54aab))
(no_connect (at 372.11 212.09) (uuid 4a62429e-02c3-4ecf-bc90-f1d28c069c07))
@ -3052,9 +3052,9 @@
(no_connect (at 109.22 196.85) (uuid a0a81c39-62ab-483b-92e8-438842cf19fc))
(no_connect (at 336.55 54.61) (uuid a1ea9e06-ed8a-4942-82a7-221567c6c412))
(no_connect (at 377.19 54.61) (uuid a4413f7c-ef15-4c3e-8922-4bd0bfe13b42))
(no_connect (at 109.22 214.63) (uuid a4c425eb-bed1-45ee-b82e-843c4bdddef2))
(no_connect (at 109.22 181.61) (uuid a4c425eb-bed1-45ee-b82e-843c4bdddef4))
(no_connect (at 109.22 151.13) (uuid a4c425eb-bed1-45ee-b82e-843c4bdddef5))
(no_connect (at 372.11 163.83) (uuid a59a5b67-5d6d-445f-b030-665df087f717))
(no_connect (at 43.18 166.37) (uuid a5f92b36-b8f4-4a10-90da-5695567ef3ec))
(no_connect (at 372.11 219.71) (uuid a8d64fcc-84cb-4645-a06d-f5d6c0614188))
(no_connect (at 372.11 224.79) (uuid ac2f3eb5-9193-4a6c-bab6-d1de91fe5122))
@ -3069,7 +3069,6 @@
(no_connect (at 109.22 201.93) (uuid c6c4013d-3700-4ed7-9261-acfb9c8eeaa7))
(no_connect (at 372.11 204.47) (uuid ca537b4c-1b97-49ee-ac71-ec3ea5a88d0c))
(no_connect (at 351.79 54.61) (uuid cc3d9289-a007-4614-9162-46212988df32))
(no_connect (at 372.11 153.67) (uuid cc8c69b3-aa61-46a2-8707-33a06e5ceb64))
(no_connect (at 109.22 163.83) (uuid cdd6a1ea-c980-432f-ae87-d2e371cec527))
(no_connect (at 344.17 54.61) (uuid cf536c01-1fe3-48e2-9066-91e69081eba0))
(no_connect (at 43.18 196.85) (uuid d2a1dfde-6514-44a0-868d-aeae5393d2b9))
@ -3215,6 +3214,10 @@
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 076e2297-1cf9-4d98-99e1-3678c817b474)
)
(wire (pts (xy 102.87 214.63) (xy 102.87 228.6))
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 076e4957-2495-4b08-898d-97eae3bf3822)
)
(wire (pts (xy 73.66 120.65) (xy 73.66 184.15))
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 08a4df9e-21eb-4281-8712-e128e191f2dc)
@ -3488,7 +3491,7 @@
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 2ba91107-8e94-4a22-9b34-e412192b425b)
)
(wire (pts (xy 102.87 204.47) (xy 111.76 204.47))
(wire (pts (xy 109.22 204.47) (xy 111.76 204.47))
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 2c183096-1d91-4e5e-933c-2e61988f56c9)
)
@ -3903,10 +3906,6 @@
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 5c988bb4-5bd0-44d5-8fdd-025abb49e96f)
)
(wire (pts (xy 102.87 204.47) (xy 102.87 228.6))
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 5cc04aae-153f-46c2-9ada-74b847d93476)
)
(wire (pts (xy 233.68 81.28) (xy 237.49 81.28))
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 5cc7333d-159c-4cb3-bc53-9569d2b4097b)
@ -4964,7 +4963,7 @@
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid e8f54748-419b-403f-a816-5349f92ed1b2)
)
(wire (pts (xy 109.22 214.63) (xy 111.76 214.63))
(wire (pts (xy 102.87 214.63) (xy 111.76 214.63))
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid ea0ee2c9-885b-4c4e-992a-86782e1a690a)
)
@ -5274,7 +5273,7 @@
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid b1c0787b-4105-489c-ab15-a5a33a17a9a9)
)
(label "FPGA_CLK_IN" (at 109.22 204.47 180)
(label "FPGA_CLK_IN" (at 109.22 214.63 180)
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid bab9f37e-b9aa-434d-ae21-8877a4b4669c)
)
@ -5346,7 +5345,7 @@
(effects (font (size 1.27 1.27)) (justify right))
(uuid 476483c7-ae07-4782-b465-a561719e3442)
)
(hierarchical_label "SPI_CLK" (shape input) (at 372.11 163.83 180)
(hierarchical_label "SPI_CLK" (shape input) (at 372.11 153.67 180)
(effects (font (size 1.27 1.27)) (justify right))
(uuid 5aaaf7b3-3dab-4fdd-a264-90953e117367)
)