83 lines
1.8 KiB
Plaintext
83 lines
1.8 KiB
Plaintext
{
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"board": {
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"design_settings": {
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"defaults": {
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"board_outline_line_width": 0.1,
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"copper_line_width": 0.2,
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"copper_text_size_h": 1.5,
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"copper_text_size_v": 1.5,
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"copper_text_thickness": 0.3,
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"other_line_width": 0.15,
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"silk_line_width": 0.15,
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"silk_text_size_h": 1.0,
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"silk_text_size_v": 1.0,
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"silk_text_thickness": 0.15
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},
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"diff_pair_dimensions": [],
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"drc_exclusions": [],
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"rules": {
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"min_copper_edge_clearance": 0.0,
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"solder_mask_clearance": 0.0,
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"solder_mask_min_width": 0.0
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},
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"track_widths": [],
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"via_dimensions": []
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},
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"layer_presets": []
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},
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"boards": [],
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"cvpcb": {
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"equivalence_files": []
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},
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"libraries": {
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"pinned_footprint_libs": [],
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"pinned_symbol_libs": []
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},
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"meta": {
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"filename": "soldlow.kicad_pro",
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"version": 1
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},
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"net_settings": {
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"classes": [
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{
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"bus_width": 12.0,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "Default",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.25,
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"via_diameter": 0.8,
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"via_drill": 0.4,
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"wire_width": 6.0
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}
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],
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"meta": {
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"version": 2
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},
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"net_colors": null
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},
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"pcbnew": {
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"last_paths": {
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"gencad": "",
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"idf": "",
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"netlist": "",
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"specctra_dsn": "",
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"step": "",
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"vrml": ""
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},
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"page_layout_descr_file": ""
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},
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"schematic": {
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"legacy_lib_dir": "",
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"legacy_lib_list": []
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},
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"sheets": [],
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"text_variables": {}
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}
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