2009-06-05 06:42:42 -06:00
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/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <linux/seq_file.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2012-10-02 11:01:07 -06:00
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#include <drm/drmP.h>
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2009-06-05 06:42:42 -06:00
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#include "radeon_reg.h"
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#include "radeon.h"
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2010-03-11 14:19:17 -07:00
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#include "radeon_asic.h"
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2009-09-11 07:35:22 -06:00
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#include "atom.h"
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2010-01-06 11:28:48 -07:00
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#include "r100d.h"
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2009-09-09 14:24:20 -06:00
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#include "r420d.h"
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2010-01-08 13:58:49 -07:00
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#include "r420_reg_safe.h"
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2010-05-07 13:10:16 -06:00
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void r420_pm_init_profile(struct radeon_device *rdev)
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{
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/* default */
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rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
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rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
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rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
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rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
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/* low sh */
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rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
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2010-06-02 15:56:01 -06:00
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rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
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2010-05-07 13:10:16 -06:00
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rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
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rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
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2010-06-02 15:56:01 -06:00
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/* mid sh */
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rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
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rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
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rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
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rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
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2010-05-07 13:10:16 -06:00
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/* high sh */
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rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
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rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
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rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
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rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
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/* low mh */
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rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
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rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
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rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
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rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
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2010-06-02 15:56:01 -06:00
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/* mid mh */
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rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
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rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
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rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
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rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
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2010-05-07 13:10:16 -06:00
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/* high mh */
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rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
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rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
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rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
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rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
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}
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2010-01-08 13:58:49 -07:00
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static void r420_set_reg_safe(struct radeon_device *rdev)
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{
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rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
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rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
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}
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2009-06-05 06:42:42 -06:00
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void r420_pipes_init(struct radeon_device *rdev)
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{
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unsigned tmp;
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unsigned gb_pipe_select;
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unsigned num_pipes;
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/* GA_ENHANCE workaround TCL deadlock issue */
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2010-02-04 23:58:28 -07:00
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WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
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(1 << 2) | (1 << 3));
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2009-09-20 22:15:10 -06:00
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/* add idle wait as per freedesktop.org bug 24041 */
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if (r100_gui_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait GUI idle while "
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"programming pipes. Bad things might happen.\n");
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}
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2009-06-05 06:42:42 -06:00
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/* get max number of pipes */
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2011-01-24 21:24:59 -07:00
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gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
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2009-06-05 06:42:42 -06:00
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num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
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2010-04-22 14:57:32 -06:00
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/* SE chips have 1 pipe */
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if ((rdev->pdev->device == 0x5e4c) ||
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(rdev->pdev->device == 0x5e4f))
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num_pipes = 1;
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2009-06-05 06:42:42 -06:00
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rdev->num_gb_pipes = num_pipes;
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tmp = 0;
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switch (num_pipes) {
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default:
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/* force to 1 pipe */
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num_pipes = 1;
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case 1:
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tmp = (0 << 1);
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break;
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case 2:
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tmp = (3 << 1);
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break;
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case 3:
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tmp = (6 << 1);
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break;
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case 4:
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tmp = (7 << 1);
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break;
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}
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2010-02-04 23:58:28 -07:00
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WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
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2009-06-05 06:42:42 -06:00
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/* Sub pixel 1/12 so we can have 4K rendering according to doc */
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2010-02-04 23:58:28 -07:00
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tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
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WREG32(R300_GB_TILE_CONFIG, tmp);
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2009-06-05 06:42:42 -06:00
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if (r100_gui_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait GUI idle while "
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"programming pipes. Bad things might happen.\n");
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}
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2010-02-04 23:58:28 -07:00
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tmp = RREG32(R300_DST_PIPE_CONFIG);
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WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
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2009-06-05 06:42:42 -06:00
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WREG32(R300_RB2D_DSTCACHE_MODE,
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RREG32(R300_RB2D_DSTCACHE_MODE) |
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R300_DC_AUTOFLUSH_ENABLE |
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R300_DC_DC_DISABLE_IGNORE_PE);
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if (r100_gui_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait GUI idle while "
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"programming pipes. Bad things might happen.\n");
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}
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2009-08-19 17:11:39 -06:00
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if (rdev->family == CHIP_RV530) {
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tmp = RREG32(RV530_GB_PIPE_SELECT2);
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if ((tmp & 3) == 3)
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rdev->num_z_pipes = 2;
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else
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rdev->num_z_pipes = 1;
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} else
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rdev->num_z_pipes = 1;
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DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
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rdev->num_gb_pipes, rdev->num_z_pipes);
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2009-06-05 06:42:42 -06:00
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}
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2009-09-11 07:35:22 -06:00
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u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
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2009-06-05 06:42:42 -06:00
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{
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2009-09-11 07:35:22 -06:00
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u32 r;
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WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
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r = RREG32(R_0001FC_MC_IND_DATA);
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return r;
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}
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void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
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{
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WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
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S_0001F8_MC_IND_WR_EN(1));
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WREG32(R_0001FC_MC_IND_DATA, v);
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}
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static void r420_debugfs(struct radeon_device *rdev)
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{
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if (r100_debugfs_rbbm_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for RBBM !\n");
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}
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if (r420_debugfs_pipes_info_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for pipes !\n");
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}
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}
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static void r420_clock_resume(struct radeon_device *rdev)
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{
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u32 sclk_cntl;
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2009-10-01 02:20:52 -06:00
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if (radeon_dynclks != -1 && radeon_dynclks)
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radeon_atom_set_clock_gating(rdev, 1);
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2009-09-11 07:35:22 -06:00
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sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
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sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
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if (rdev->family == CHIP_R420)
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sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
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WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
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}
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2010-01-06 11:28:48 -07:00
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static void r420_cp_errata_init(struct radeon_device *rdev)
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{
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2011-10-23 04:56:27 -06:00
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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2011-09-23 07:11:23 -06:00
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2010-01-06 11:28:48 -07:00
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/* RV410 and R420 can lock up if CP DMA to host memory happens
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* while the 2D engine is busy.
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*
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* The proper workaround is to queue a RESYNC at the beginning
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* of the CP init, apparently.
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*/
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radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
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2011-10-23 04:56:27 -06:00
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radeon_ring_lock(rdev, ring, 8);
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radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));
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radeon_ring_write(ring, rdev->config.r300.resync_scratch);
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radeon_ring_write(ring, 0xDEADBEEF);
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radeon_ring_unlock_commit(rdev, ring);
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2010-01-06 11:28:48 -07:00
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}
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static void r420_cp_errata_fini(struct radeon_device *rdev)
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{
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2011-10-23 04:56:27 -06:00
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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2011-09-23 07:11:23 -06:00
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2010-01-06 11:28:48 -07:00
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/* Catch the RESYNC we dispatched all the way back,
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* at the very beginning of the CP init.
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*/
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2011-10-23 04:56:27 -06:00
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radeon_ring_lock(rdev, ring, 8);
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radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
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radeon_ring_write(ring, R300_RB3D_DC_FINISH);
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radeon_ring_unlock_commit(rdev, ring);
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2010-01-06 11:28:48 -07:00
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radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
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}
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2009-09-17 23:19:37 -06:00
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static int r420_startup(struct radeon_device *rdev)
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2009-09-11 07:35:22 -06:00
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{
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int r;
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|
|
|
|
2009-12-04 08:55:12 -07:00
|
|
|
/* set common regs */
|
|
|
|
r100_set_common_regs(rdev);
|
|
|
|
/* program mc */
|
2009-09-11 07:35:22 -06:00
|
|
|
r300_mc_program(rdev);
|
2009-10-01 02:20:52 -06:00
|
|
|
/* Resume clock */
|
|
|
|
r420_clock_resume(rdev);
|
2009-09-11 07:35:22 -06:00
|
|
|
/* Initialize GART (initialize after TTM so we can allocate
|
|
|
|
* memory through TTM but finalize after TTM) */
|
2009-09-14 10:29:49 -06:00
|
|
|
if (rdev->flags & RADEON_IS_PCIE) {
|
|
|
|
r = rv370_pcie_gart_enable(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
if (rdev->flags & RADEON_IS_PCI) {
|
|
|
|
r = r100_pci_gart_enable(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
2009-09-11 07:35:22 -06:00
|
|
|
}
|
2009-06-05 06:42:42 -06:00
|
|
|
r420_pipes_init(rdev);
|
2010-08-27 16:25:25 -06:00
|
|
|
|
|
|
|
/* allocate wb buffer */
|
|
|
|
r = radeon_wb_init(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
2011-11-20 13:45:34 -07:00
|
|
|
r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
|
|
|
|
if (r) {
|
|
|
|
dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2009-09-11 07:35:22 -06:00
|
|
|
/* Enable IRQ */
|
|
|
|
r100_irq_set(rdev);
|
2010-01-07 04:39:21 -07:00
|
|
|
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
|
2009-09-11 07:35:22 -06:00
|
|
|
/* 1M ring buffer */
|
|
|
|
r = r100_cp_init(rdev, 1024 * 1024);
|
|
|
|
if (r) {
|
2011-01-28 15:32:04 -07:00
|
|
|
dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
|
2009-09-11 07:35:22 -06:00
|
|
|
return r;
|
|
|
|
}
|
2010-01-06 11:28:48 -07:00
|
|
|
r420_cp_errata_init(rdev);
|
drm/radeon: introduce a sub allocator and convert ib pool to it v4
Somewhat specializaed sub-allocator designed to perform sub-allocation
for command buffer not only for current cs ioctl but for future command
submission ioctl as well. Patch also convert current ib pool to use
the sub allocator. Idea is that ib poll buffer can be share with other
command buffer submission not having 64K granularity.
v2 Harmonize pool handling and add suspend/resume callback to pin/unpin
sa bo (tested on rv280, rv370, r420, rv515, rv610, rv710, redwood, cayman,
rs480, rs690, rs880)
v3 Simplify allocator
v4 Fix radeon_ib_get error path to properly free fence
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-15 09:48:34 -07:00
|
|
|
|
2012-07-05 03:55:34 -06:00
|
|
|
r = radeon_ib_pool_init(rdev);
|
|
|
|
if (r) {
|
|
|
|
dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
|
drm/radeon: introduce a sub allocator and convert ib pool to it v4
Somewhat specializaed sub-allocator designed to perform sub-allocation
for command buffer not only for current cs ioctl but for future command
submission ioctl as well. Patch also convert current ib pool to use
the sub allocator. Idea is that ib poll buffer can be share with other
command buffer submission not having 64K granularity.
v2 Harmonize pool handling and add suspend/resume callback to pin/unpin
sa bo (tested on rv280, rv370, r420, rv515, rv610, rv710, redwood, cayman,
rs480, rs690, rs880)
v3 Simplify allocator
v4 Fix radeon_ib_get error path to properly free fence
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-15 09:48:34 -07:00
|
|
|
return r;
|
2012-07-05 03:55:34 -06:00
|
|
|
}
|
drm/radeon: introduce a sub allocator and convert ib pool to it v4
Somewhat specializaed sub-allocator designed to perform sub-allocation
for command buffer not only for current cs ioctl but for future command
submission ioctl as well. Patch also convert current ib pool to use
the sub allocator. Idea is that ib poll buffer can be share with other
command buffer submission not having 64K granularity.
v2 Harmonize pool handling and add suspend/resume callback to pin/unpin
sa bo (tested on rv280, rv370, r420, rv515, rv610, rv710, redwood, cayman,
rs480, rs690, rs880)
v3 Simplify allocator
v4 Fix radeon_ib_get error path to properly free fence
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-15 09:48:34 -07:00
|
|
|
|
2009-09-11 07:35:22 -06:00
|
|
|
return 0;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
2009-09-17 23:19:37 -06:00
|
|
|
int r420_resume(struct radeon_device *rdev)
|
|
|
|
{
|
2012-02-20 15:57:20 -07:00
|
|
|
int r;
|
|
|
|
|
2009-09-17 23:19:37 -06:00
|
|
|
/* Make sur GART are not working */
|
|
|
|
if (rdev->flags & RADEON_IS_PCIE)
|
|
|
|
rv370_pcie_gart_disable(rdev);
|
|
|
|
if (rdev->flags & RADEON_IS_PCI)
|
|
|
|
r100_pci_gart_disable(rdev);
|
|
|
|
/* Resume clock before doing reset */
|
|
|
|
r420_clock_resume(rdev);
|
|
|
|
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
|
2010-03-09 07:45:11 -07:00
|
|
|
if (radeon_asic_reset(rdev)) {
|
2009-09-17 23:19:37 -06:00
|
|
|
dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
|
|
|
|
RREG32(R_000E40_RBBM_STATUS),
|
|
|
|
RREG32(R_0007C0_CP_STAT));
|
|
|
|
}
|
|
|
|
/* check if cards are posted or not */
|
|
|
|
if (rdev->is_atom_bios) {
|
|
|
|
atom_asic_init(rdev->mode_info.atom_context);
|
|
|
|
} else {
|
|
|
|
radeon_combios_asic_init(rdev->ddev);
|
|
|
|
}
|
|
|
|
/* Resume clock after posting */
|
|
|
|
r420_clock_resume(rdev);
|
2009-12-08 21:15:38 -07:00
|
|
|
/* Initialize surface registers */
|
|
|
|
radeon_surface_init(rdev);
|
drm/radeon: introduce a sub allocator and convert ib pool to it v4
Somewhat specializaed sub-allocator designed to perform sub-allocation
for command buffer not only for current cs ioctl but for future command
submission ioctl as well. Patch also convert current ib pool to use
the sub allocator. Idea is that ib poll buffer can be share with other
command buffer submission not having 64K granularity.
v2 Harmonize pool handling and add suspend/resume callback to pin/unpin
sa bo (tested on rv280, rv370, r420, rv515, rv610, rv710, redwood, cayman,
rs480, rs690, rs880)
v3 Simplify allocator
v4 Fix radeon_ib_get error path to properly free fence
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-15 09:48:34 -07:00
|
|
|
|
|
|
|
rdev->accel_working = true;
|
2012-02-20 15:57:20 -07:00
|
|
|
r = r420_startup(rdev);
|
|
|
|
if (r) {
|
|
|
|
rdev->accel_working = false;
|
|
|
|
}
|
|
|
|
return r;
|
2009-09-17 23:19:37 -06:00
|
|
|
}
|
|
|
|
|
2009-09-11 07:35:22 -06:00
|
|
|
int r420_suspend(struct radeon_device *rdev)
|
|
|
|
{
|
2010-01-06 11:28:48 -07:00
|
|
|
r420_cp_errata_fini(rdev);
|
2009-09-11 07:35:22 -06:00
|
|
|
r100_cp_disable(rdev);
|
2010-08-27 16:25:25 -06:00
|
|
|
radeon_wb_disable(rdev);
|
2009-09-11 07:35:22 -06:00
|
|
|
r100_irq_disable(rdev);
|
2009-09-14 10:29:49 -06:00
|
|
|
if (rdev->flags & RADEON_IS_PCIE)
|
|
|
|
rv370_pcie_gart_disable(rdev);
|
|
|
|
if (rdev->flags & RADEON_IS_PCI)
|
|
|
|
r100_pci_gart_disable(rdev);
|
2009-09-11 07:35:22 -06:00
|
|
|
return 0;
|
|
|
|
}
|
2009-06-05 06:42:42 -06:00
|
|
|
|
2009-09-11 07:35:22 -06:00
|
|
|
void r420_fini(struct radeon_device *rdev)
|
2009-06-05 06:42:42 -06:00
|
|
|
{
|
2009-09-11 07:35:22 -06:00
|
|
|
r100_cp_fini(rdev);
|
2010-08-27 16:25:25 -06:00
|
|
|
radeon_wb_fini(rdev);
|
2012-07-05 03:55:34 -06:00
|
|
|
radeon_ib_pool_fini(rdev);
|
2009-09-11 07:35:22 -06:00
|
|
|
radeon_gem_fini(rdev);
|
2009-09-14 10:29:49 -06:00
|
|
|
if (rdev->flags & RADEON_IS_PCIE)
|
|
|
|
rv370_pcie_gart_fini(rdev);
|
|
|
|
if (rdev->flags & RADEON_IS_PCI)
|
|
|
|
r100_pci_gart_fini(rdev);
|
2009-09-11 07:35:22 -06:00
|
|
|
radeon_agp_fini(rdev);
|
|
|
|
radeon_irq_kms_fini(rdev);
|
|
|
|
radeon_fence_driver_fini(rdev);
|
2009-11-20 06:29:23 -07:00
|
|
|
radeon_bo_fini(rdev);
|
2009-09-11 07:35:22 -06:00
|
|
|
if (rdev->is_atom_bios) {
|
|
|
|
radeon_atombios_fini(rdev);
|
|
|
|
} else {
|
|
|
|
radeon_combios_fini(rdev);
|
|
|
|
}
|
|
|
|
kfree(rdev->bios);
|
|
|
|
rdev->bios = NULL;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
2009-09-11 07:35:22 -06:00
|
|
|
int r420_init(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
int r;
|
|
|
|
|
|
|
|
/* Initialize scratch registers */
|
|
|
|
radeon_scratch_init(rdev);
|
|
|
|
/* Initialize surface registers */
|
|
|
|
radeon_surface_init(rdev);
|
|
|
|
/* TODO: disable VGA need to use VGA request */
|
2010-07-14 20:13:50 -06:00
|
|
|
/* restore some register to sane defaults */
|
|
|
|
r100_restore_sanity(rdev);
|
2009-09-11 07:35:22 -06:00
|
|
|
/* BIOS*/
|
|
|
|
if (!radeon_get_bios(rdev)) {
|
|
|
|
if (ASIC_IS_AVIVO(rdev))
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
if (rdev->is_atom_bios) {
|
|
|
|
r = radeon_atombios_init(rdev);
|
|
|
|
if (r) {
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
r = radeon_combios_init(rdev);
|
|
|
|
if (r) {
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
|
2010-03-09 07:45:11 -07:00
|
|
|
if (radeon_asic_reset(rdev)) {
|
2009-09-11 07:35:22 -06:00
|
|
|
dev_warn(rdev->dev,
|
|
|
|
"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
|
|
|
|
RREG32(R_000E40_RBBM_STATUS),
|
|
|
|
RREG32(R_0007C0_CP_STAT));
|
|
|
|
}
|
|
|
|
/* check if cards are posted or not */
|
2009-11-30 21:06:31 -07:00
|
|
|
if (radeon_boot_test_post_card(rdev) == false)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2009-09-11 07:35:22 -06:00
|
|
|
/* Initialize clocks */
|
|
|
|
radeon_get_clock_info(rdev->ddev);
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 14:54:29 -07:00
|
|
|
/* initialize AGP */
|
|
|
|
if (rdev->flags & RADEON_IS_AGP) {
|
|
|
|
r = radeon_agp_init(rdev);
|
|
|
|
if (r) {
|
|
|
|
radeon_agp_disable(rdev);
|
|
|
|
}
|
2009-09-11 07:35:22 -06:00
|
|
|
}
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 14:54:29 -07:00
|
|
|
/* initialize memory controller */
|
|
|
|
r300_mc_init(rdev);
|
2009-09-11 07:35:22 -06:00
|
|
|
r420_debugfs(rdev);
|
|
|
|
/* Fence driver */
|
2011-11-20 13:45:34 -07:00
|
|
|
r = radeon_fence_driver_init(rdev);
|
2009-09-11 07:35:22 -06:00
|
|
|
if (r) {
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
r = radeon_irq_kms_init(rdev);
|
|
|
|
if (r) {
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
/* Memory manager */
|
2009-11-20 06:29:23 -07:00
|
|
|
r = radeon_bo_init(rdev);
|
2009-09-11 07:35:22 -06:00
|
|
|
if (r) {
|
|
|
|
return r;
|
|
|
|
}
|
2009-11-04 22:36:53 -07:00
|
|
|
if (rdev->family == CHIP_R420)
|
|
|
|
r100_enable_bm(rdev);
|
|
|
|
|
2009-09-14 10:29:49 -06:00
|
|
|
if (rdev->flags & RADEON_IS_PCIE) {
|
|
|
|
r = rv370_pcie_gart_init(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
if (rdev->flags & RADEON_IS_PCI) {
|
|
|
|
r = r100_pci_gart_init(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
}
|
2010-01-08 13:58:49 -07:00
|
|
|
r420_set_reg_safe(rdev);
|
drm/radeon: introduce a sub allocator and convert ib pool to it v4
Somewhat specializaed sub-allocator designed to perform sub-allocation
for command buffer not only for current cs ioctl but for future command
submission ioctl as well. Patch also convert current ib pool to use
the sub allocator. Idea is that ib poll buffer can be share with other
command buffer submission not having 64K granularity.
v2 Harmonize pool handling and add suspend/resume callback to pin/unpin
sa bo (tested on rv280, rv370, r420, rv515, rv610, rv710, redwood, cayman,
rs480, rs690, rs880)
v3 Simplify allocator
v4 Fix radeon_ib_get error path to properly free fence
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-15 09:48:34 -07:00
|
|
|
|
2009-09-16 07:24:21 -06:00
|
|
|
rdev->accel_working = true;
|
2009-09-17 23:19:37 -06:00
|
|
|
r = r420_startup(rdev);
|
2009-09-11 07:35:22 -06:00
|
|
|
if (r) {
|
|
|
|
/* Somethings want wront with the accel init stop accel */
|
|
|
|
dev_err(rdev->dev, "Disabling GPU acceleration\n");
|
|
|
|
r100_cp_fini(rdev);
|
2010-08-27 16:25:25 -06:00
|
|
|
radeon_wb_fini(rdev);
|
2012-07-05 03:55:34 -06:00
|
|
|
radeon_ib_pool_fini(rdev);
|
2010-02-02 03:51:45 -07:00
|
|
|
radeon_irq_kms_fini(rdev);
|
2009-09-14 10:29:49 -06:00
|
|
|
if (rdev->flags & RADEON_IS_PCIE)
|
|
|
|
rv370_pcie_gart_fini(rdev);
|
|
|
|
if (rdev->flags & RADEON_IS_PCI)
|
|
|
|
r100_pci_gart_fini(rdev);
|
2009-09-11 07:35:22 -06:00
|
|
|
radeon_agp_fini(rdev);
|
2009-09-16 07:24:21 -06:00
|
|
|
rdev->accel_working = false;
|
2009-09-11 07:35:22 -06:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
2009-06-05 06:42:42 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Debugfs info
|
|
|
|
*/
|
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
|
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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struct radeon_device *rdev = dev->dev_private;
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uint32_t tmp;
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tmp = RREG32(R400_GB_PIPE_SELECT);
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seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
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tmp = RREG32(R300_GB_TILE_CONFIG);
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seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
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tmp = RREG32(R300_DST_PIPE_CONFIG);
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seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
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return 0;
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}
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static struct drm_info_list r420_pipes_info_list[] = {
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{"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
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};
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#endif
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int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
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{
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#if defined(CONFIG_DEBUG_FS)
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return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
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#else
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return 0;
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#endif
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}
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