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alistair23-linux/drivers/spi/spi-fsl-espi.c

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-27 00:55:01 -06:00
// SPDX-License-Identifier: GPL-2.0-or-later
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
/*
* Freescale eSPI controller driver.
*
* Copyright 2010 Freescale Semiconductor, Inc.
*/
#include <linux/delay.h>
spi: fsl: Sort include headers alphabetically Sort all the include headers alphabetically for the freescale spi drivers. If the inlcude headers sorted out of order, maybe the best logical choice is to append new ones after the exist ones, while this may create a lot of potential for duplicates and conflicts for each diffenent changes will add new headers in the same location. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-09-28 20:57:06 -06:00
#include <linux/err.h>
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
#include <linux/fsl_devices.h>
spi: fsl: Sort include headers alphabetically Sort all the include headers alphabetically for the freescale spi drivers. If the inlcude headers sorted out of order, maybe the best logical choice is to append new ones after the exist ones, while this may create a lot of potential for duplicates and conflicts for each diffenent changes will add new headers in the same location. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-09-28 20:57:06 -06:00
#include <linux/interrupt.h>
#include <linux/module.h>
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
#include <linux/mm.h>
#include <linux/of.h>
drivers: clean-up prom.h implicit includes Powerpc is a mess of implicit includes by prom.h. Add the necessary explicit includes to drivers in preparation of prom.h cleanup. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Grant Likely <grant.likely@linaro.org>
2013-09-17 13:28:33 -06:00
#include <linux/of_address.h>
#include <linux/of_irq.h>
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
#include <linux/of_platform.h>
spi: fsl: Sort include headers alphabetically Sort all the include headers alphabetically for the freescale spi drivers. If the inlcude headers sorted out of order, maybe the best logical choice is to append new ones after the exist ones, while this may create a lot of potential for duplicates and conflicts for each diffenent changes will add new headers in the same location. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-09-28 20:57:06 -06:00
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
spi: fsl-espi: add runtime PM Add runtime PM and use autosuspend instead of suspending the SPI controller after each transfer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-26 13:21:55 -06:00
#include <linux/pm_runtime.h>
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
#include <sysdev/fsl_soc.h>
/* eSPI Controller registers */
spi: fsl-espi: align register access with other drivers Change register access to the method used in other drivers too. - use register names as in the chip spec for constants - avoid hard to read statements like __be32 __iomem *espi_mode = &reg_base->mode - get rid of old powerpc-specific functions like in_8 In addition annotate reg_base in struct mpc8xxx_spi as __iomem. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-13 15:16:02 -06:00
#define ESPI_SPMODE 0x00 /* eSPI mode register */
#define ESPI_SPIE 0x04 /* eSPI event register */
#define ESPI_SPIM 0x08 /* eSPI mask register */
#define ESPI_SPCOM 0x0c /* eSPI command register */
#define ESPI_SPITF 0x10 /* eSPI transmit FIFO access register*/
#define ESPI_SPIRF 0x14 /* eSPI receive FIFO access register*/
#define ESPI_SPMODE0 0x20 /* eSPI cs0 mode register */
#define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4)
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
/* eSPI Controller mode register definitions */
spi: fsl-espi: improve and extend register bit definitions Add definition of further register bits for use in upcoming driver extensions and improve current bit definitions: - use BIT macro - use bit names as in the chip spec Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-13 15:16:06 -06:00
#define SPMODE_ENABLE BIT(31)
#define SPMODE_LOOP BIT(30)
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
#define SPMODE_TXTHR(x) ((x) << 8)
#define SPMODE_RXTHR(x) ((x) << 0)
/* eSPI Controller CS mode register definitions */
spi: fsl-espi: improve and extend register bit definitions Add definition of further register bits for use in upcoming driver extensions and improve current bit definitions: - use BIT macro - use bit names as in the chip spec Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-13 15:16:06 -06:00
#define CSMODE_CI_INACTIVEHIGH BIT(31)
#define CSMODE_CP_BEGIN_EDGECLK BIT(30)
#define CSMODE_REV BIT(29)
#define CSMODE_DIV16 BIT(28)
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
#define CSMODE_PM(x) ((x) << 24)
spi: fsl-espi: improve and extend register bit definitions Add definition of further register bits for use in upcoming driver extensions and improve current bit definitions: - use BIT macro - use bit names as in the chip spec Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-13 15:16:06 -06:00
#define CSMODE_POL_1 BIT(20)
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
#define CSMODE_LEN(x) ((x) << 16)
#define CSMODE_BEF(x) ((x) << 12)
#define CSMODE_AFT(x) ((x) << 8)
#define CSMODE_CG(x) ((x) << 3)
spi: fsl-espi: fix and improve writing to TX FIFO This change addresses two issues: - If the TX FIFO is full the ISR polls until there's free space again. An ISR should never wait for something. - Currently the number of bytes to transfer is rounded up to the next multiple of 4. For most transfers therefore few bytes remain in the TX FIFO after end of transfer. This would cause the next transfer to fail and as a workaround the ESPI block is disabled / re-enabled in fsl_espi_change_mode. This seems to clear the FIFO's (although it's not mentioned in the spec). With this change the TX FIFO is filled as much as possible initially and whenever the ISR is called. Also the exact number of bytes is transferred. The spinlock protects against a potential race if the first interrupt occurs whilst the TX FIFO is still being initially filled. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:25:58 -06:00
#define FSL_ESPI_FIFO_SIZE 32
spi: fsl-espi: make better use of the RX FIFO So far an interrupt is triggered whenever there's at least one byte in the RX FIFO. This results in a unnecessarily high number of interrupts. Change this to generate an interrupt if - RX FIFO is half full (except if all bytes to read fit into the RX FIFO anyway) - end of transfer has been reached This way the number of interrupts can be significantly reduced. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:27:56 -06:00
#define FSL_ESPI_RXTHR 15
spi: fsl-espi: fix and improve writing to TX FIFO This change addresses two issues: - If the TX FIFO is full the ISR polls until there's free space again. An ISR should never wait for something. - Currently the number of bytes to transfer is rounded up to the next multiple of 4. For most transfers therefore few bytes remain in the TX FIFO after end of transfer. This would cause the next transfer to fail and as a workaround the ESPI block is disabled / re-enabled in fsl_espi_change_mode. This seems to clear the FIFO's (although it's not mentioned in the spec). With this change the TX FIFO is filled as much as possible initially and whenever the ISR is called. Also the exact number of bytes is transferred. The spinlock protects against a potential race if the first interrupt occurs whilst the TX FIFO is still being initially filled. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:25:58 -06:00
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
/* Default mode/csmode for eSPI controller */
spi: fsl-espi: make better use of the RX FIFO So far an interrupt is triggered whenever there's at least one byte in the RX FIFO. This results in a unnecessarily high number of interrupts. Change this to generate an interrupt if - RX FIFO is half full (except if all bytes to read fit into the RX FIFO anyway) - end of transfer has been reached This way the number of interrupts can be significantly reduced. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:27:56 -06:00
#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(FSL_ESPI_RXTHR))
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
| CSMODE_AFT(0) | CSMODE_CG(1))
/* SPIE register values */
#define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
#define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
spi: fsl-espi: improve and extend register bit definitions Add definition of further register bits for use in upcoming driver extensions and improve current bit definitions: - use BIT macro - use bit names as in the chip spec Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-13 15:16:06 -06:00
#define SPIE_TXE BIT(15) /* TX FIFO empty */
#define SPIE_DON BIT(14) /* TX done */
#define SPIE_RXT BIT(13) /* RX FIFO threshold */
#define SPIE_RXF BIT(12) /* RX FIFO full */
#define SPIE_TXT BIT(11) /* TX FIFO threshold*/
#define SPIE_RNE BIT(9) /* RX FIFO not empty */
#define SPIE_TNF BIT(8) /* TX FIFO not full */
/* SPIM register values */
#define SPIM_TXE BIT(15) /* TX FIFO empty */
#define SPIM_DON BIT(14) /* TX done */
#define SPIM_RXT BIT(13) /* RX FIFO threshold */
#define SPIM_RXF BIT(12) /* RX FIFO full */
#define SPIM_TXT BIT(11) /* TX FIFO threshold*/
#define SPIM_RNE BIT(9) /* RX FIFO not empty */
#define SPIM_TNF BIT(8) /* TX FIFO not full */
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
/* SPCOM register values */
#define SPCOM_CS(x) ((x) << 30)
spi: fsl-espi: improve and extend register bit definitions Add definition of further register bits for use in upcoming driver extensions and improve current bit definitions: - use BIT macro - use bit names as in the chip spec Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-13 15:16:06 -06:00
#define SPCOM_DO BIT(28) /* Dual output */
#define SPCOM_TO BIT(27) /* TX only */
#define SPCOM_RXSKIP(x) ((x) << 16)
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
#define SPCOM_TRANLEN(x) ((x) << 0)
spi: fsl-espi: improve and extend register bit definitions Add definition of further register bits for use in upcoming driver extensions and improve current bit definitions: - use BIT macro - use bit names as in the chip spec Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-13 15:16:06 -06:00
spi/fsl-espi: Correct the maximum transaction length The maximum length during one transcation is 64KiB. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-01-22 03:58:26 -07:00
#define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: add runtime PM Add runtime PM and use autosuspend instead of suspending the SPI controller after each transfer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-26 13:21:55 -06:00
#define AUTOSUSPEND_TIMEOUT 2000
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
struct fsl_espi {
struct device *dev;
void __iomem *reg_base;
spi: fsl-espi: eliminate need for linearization when writing to hardware Eliminate need for linearization when writing to the hardware and read from the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:24 -07:00
struct list_head *m_transfers;
struct spi_transfer *tx_t;
unsigned int tx_pos;
bool tx_done;
spi: fsl-espi: eliminate need for linearization when reading from hardware Eliminate need for linearization when reading from the hardware and write to the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:57 -07:00
struct spi_transfer *rx_t;
unsigned int rx_pos;
bool rx_done;
spi: fsl-espi: eliminate need for linearization when writing to hardware Eliminate need for linearization when writing to the hardware and read from the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:24 -07:00
spi: fsl-espi: determine need for byte swap only once Determine need for byte swap only once and store it in new member swab in struct fsl_espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:58:49 -07:00
bool swab;
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
unsigned int rxskip;
spinlock_t lock;
u32 spibrg; /* SPIBRG input clock */
struct completion done;
};
spi: fsl-espi: introduce struct fsl_espi_cs Very little from struct spi_mpc8xxx_cs is relevant for fsl-espi. Therefore replace it with struct fsl_espi_cs. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:38:05 -07:00
struct fsl_espi_cs {
u32 hw_mode;
};
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
static inline u32 fsl_espi_read_reg(struct fsl_espi *espi, int offset)
spi: fsl-espi: align register access with other drivers Change register access to the method used in other drivers too. - use register names as in the chip spec for constants - avoid hard to read statements like __be32 __iomem *espi_mode = &reg_base->mode - get rid of old powerpc-specific functions like in_8 In addition annotate reg_base in struct mpc8xxx_spi as __iomem. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-13 15:16:02 -06:00
{
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
return ioread32be(espi->reg_base + offset);
spi: fsl-espi: align register access with other drivers Change register access to the method used in other drivers too. - use register names as in the chip spec for constants - avoid hard to read statements like __be32 __iomem *espi_mode = &reg_base->mode - get rid of old powerpc-specific functions like in_8 In addition annotate reg_base in struct mpc8xxx_spi as __iomem. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-13 15:16:02 -06:00
}
spi: fsl-espi: eliminate need for linearization when reading from hardware Eliminate need for linearization when reading from the hardware and write to the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:57 -07:00
static inline u16 fsl_espi_read_reg16(struct fsl_espi *espi, int offset)
{
spi: fsl-espi: fix ioread16/iowrite16 endianness fsl_espi_read_reg16 / fsl_espi_write_reg16 are supposed to read / write big endian values. Therefore ioread16be / iowrite16be have to be used. Fixes: 058234328445 ("eliminate need for linearization when writing to hardware") Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-30 12:28:09 -07:00
return ioread16be(espi->reg_base + offset);
spi: fsl-espi: eliminate need for linearization when reading from hardware Eliminate need for linearization when reading from the hardware and write to the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:57 -07:00
}
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
static inline u8 fsl_espi_read_reg8(struct fsl_espi *espi, int offset)
spi: fsl-espi: align register access with other drivers Change register access to the method used in other drivers too. - use register names as in the chip spec for constants - avoid hard to read statements like __be32 __iomem *espi_mode = &reg_base->mode - get rid of old powerpc-specific functions like in_8 In addition annotate reg_base in struct mpc8xxx_spi as __iomem. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-13 15:16:02 -06:00
{
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
return ioread8(espi->reg_base + offset);
spi: fsl-espi: align register access with other drivers Change register access to the method used in other drivers too. - use register names as in the chip spec for constants - avoid hard to read statements like __be32 __iomem *espi_mode = &reg_base->mode - get rid of old powerpc-specific functions like in_8 In addition annotate reg_base in struct mpc8xxx_spi as __iomem. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-13 15:16:02 -06:00
}
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
static inline void fsl_espi_write_reg(struct fsl_espi *espi, int offset,
spi: fsl-espi: align register access with other drivers Change register access to the method used in other drivers too. - use register names as in the chip spec for constants - avoid hard to read statements like __be32 __iomem *espi_mode = &reg_base->mode - get rid of old powerpc-specific functions like in_8 In addition annotate reg_base in struct mpc8xxx_spi as __iomem. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-13 15:16:02 -06:00
u32 val)
{
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
iowrite32be(val, espi->reg_base + offset);
spi: fsl-espi: align register access with other drivers Change register access to the method used in other drivers too. - use register names as in the chip spec for constants - avoid hard to read statements like __be32 __iomem *espi_mode = &reg_base->mode - get rid of old powerpc-specific functions like in_8 In addition annotate reg_base in struct mpc8xxx_spi as __iomem. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-13 15:16:02 -06:00
}
spi: fsl-espi: eliminate need for linearization when writing to hardware Eliminate need for linearization when writing to the hardware and read from the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:24 -07:00
static inline void fsl_espi_write_reg16(struct fsl_espi *espi, int offset,
u16 val)
{
spi: fsl-espi: fix ioread16/iowrite16 endianness fsl_espi_read_reg16 / fsl_espi_write_reg16 are supposed to read / write big endian values. Therefore ioread16be / iowrite16be have to be used. Fixes: 058234328445 ("eliminate need for linearization when writing to hardware") Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-30 12:28:09 -07:00
iowrite16be(val, espi->reg_base + offset);
spi: fsl-espi: eliminate need for linearization when writing to hardware Eliminate need for linearization when writing to the hardware and read from the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:24 -07:00
}
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
static inline void fsl_espi_write_reg8(struct fsl_espi *espi, int offset,
spi: fsl-espi: align register access with other drivers Change register access to the method used in other drivers too. - use register names as in the chip spec for constants - avoid hard to read statements like __be32 __iomem *espi_mode = &reg_base->mode - get rid of old powerpc-specific functions like in_8 In addition annotate reg_base in struct mpc8xxx_spi as __iomem. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-13 15:16:02 -06:00
u8 val)
{
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
iowrite8(val, espi->reg_base + offset);
spi: fsl-espi: align register access with other drivers Change register access to the method used in other drivers too. - use register names as in the chip spec for constants - avoid hard to read statements like __be32 __iomem *espi_mode = &reg_base->mode - get rid of old powerpc-specific functions like in_8 In addition annotate reg_base in struct mpc8xxx_spi as __iomem. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-13 15:16:02 -06:00
}
spi: fsl-espi: factor out initial message checking Checking the message is currently done at diffrent places in the driver. Factor it out to fsl_espi_check_message. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:53:38 -06:00
static int fsl_espi_check_message(struct spi_message *m)
{
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
struct fsl_espi *espi = spi_master_get_devdata(m->spi->master);
spi: fsl-espi: factor out initial message checking Checking the message is currently done at diffrent places in the driver. Factor it out to fsl_espi_check_message. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:53:38 -06:00
struct spi_transfer *t, *first;
if (m->frame_length > SPCOM_TRANLEN_MAX) {
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
dev_err(espi->dev, "message too long, size is %u bytes\n",
spi: fsl-espi: factor out initial message checking Checking the message is currently done at diffrent places in the driver. Factor it out to fsl_espi_check_message. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:53:38 -06:00
m->frame_length);
return -EMSGSIZE;
}
first = list_first_entry(&m->transfers, struct spi_transfer,
transfer_list);
spi: fsl-espi: reject MSB-first transfers with word sizes other than 8 or 16 According to the ESPI spec MSB-first transfers are supported for word size 8 and 16 only. Check for this and reject MSB-first transfers with other word sizes. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-02 06:22:35 -06:00
spi: fsl-espi: factor out initial message checking Checking the message is currently done at diffrent places in the driver. Factor it out to fsl_espi_check_message. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:53:38 -06:00
list_for_each_entry(t, &m->transfers, transfer_list) {
if (first->bits_per_word != t->bits_per_word ||
first->speed_hz != t->speed_hz) {
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
dev_err(espi->dev, "bits_per_word/speed_hz should be the same for all transfers\n");
spi: fsl-espi: factor out initial message checking Checking the message is currently done at diffrent places in the driver. Factor it out to fsl_espi_check_message. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:53:38 -06:00
return -EINVAL;
}
}
spi: fsl-espi: reject MSB-first transfers with word sizes other than 8 or 16 According to the ESPI spec MSB-first transfers are supported for word size 8 and 16 only. Check for this and reject MSB-first transfers with other word sizes. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-02 06:22:35 -06:00
/* ESPI supports MSB-first transfers for word size 8 / 16 only */
if (!(m->spi->mode & SPI_LSB_FIRST) && first->bits_per_word != 8 &&
first->bits_per_word != 16) {
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
dev_err(espi->dev,
spi: fsl-espi: reject MSB-first transfers with word sizes other than 8 or 16 According to the ESPI spec MSB-first transfers are supported for word size 8 and 16 only. Check for this and reject MSB-first transfers with other word sizes. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-02 06:22:35 -06:00
"MSB-first transfer not supported for wordsize %u\n",
first->bits_per_word);
return -EINVAL;
}
spi: fsl-espi: factor out initial message checking Checking the message is currently done at diffrent places in the driver. Factor it out to fsl_espi_check_message. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:53:38 -06:00
return 0;
}
spi: fsl-espi: add support for ESPI RXSKIP mode This patch adds support for ESPI RXSKIP mode. This mode is optimized for flash reads: - sends a number of bytes and then reads a number of bytes - shifts out zeros automatically when reading Supporting RXSKIP mode is a prerequisite for supporting dual output read mode. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-09 14:58:01 -07:00
static unsigned int fsl_espi_check_rxskip_mode(struct spi_message *m)
{
struct spi_transfer *t;
unsigned int i = 0, rxskip = 0;
/*
* prerequisites for ESPI rxskip mode:
* - message has two transfers
* - first transfer is a write and second is a read
*
* In addition the current low-level transfer mechanism requires
* that the rxskip bytes fit into the TX FIFO. Else the transfer
* would hang because after the first FSL_ESPI_FIFO_SIZE bytes
* the TX FIFO isn't re-filled.
*/
list_for_each_entry(t, &m->transfers, transfer_list) {
if (i == 0) {
if (!t->tx_buf || t->rx_buf ||
t->len > FSL_ESPI_FIFO_SIZE)
return 0;
rxskip = t->len;
} else if (i == 1) {
if (t->tx_buf || !t->rx_buf)
return 0;
}
i++;
}
return i == 2 ? rxskip : 0;
}
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
static void fsl_espi_fill_tx_fifo(struct fsl_espi *espi, u32 events)
spi: fsl-espi: fix and improve writing to TX FIFO This change addresses two issues: - If the TX FIFO is full the ISR polls until there's free space again. An ISR should never wait for something. - Currently the number of bytes to transfer is rounded up to the next multiple of 4. For most transfers therefore few bytes remain in the TX FIFO after end of transfer. This would cause the next transfer to fail and as a workaround the ESPI block is disabled / re-enabled in fsl_espi_change_mode. This seems to clear the FIFO's (although it's not mentioned in the spec). With this change the TX FIFO is filled as much as possible initially and whenever the ISR is called. Also the exact number of bytes is transferred. The spinlock protects against a potential race if the first interrupt occurs whilst the TX FIFO is still being initially filled. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:25:58 -06:00
{
u32 tx_fifo_avail;
spi: fsl-espi: eliminate need for linearization when writing to hardware Eliminate need for linearization when writing to the hardware and read from the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:24 -07:00
unsigned int tx_left;
const void *tx_buf;
spi: fsl-espi: fix and improve writing to TX FIFO This change addresses two issues: - If the TX FIFO is full the ISR polls until there's free space again. An ISR should never wait for something. - Currently the number of bytes to transfer is rounded up to the next multiple of 4. For most transfers therefore few bytes remain in the TX FIFO after end of transfer. This would cause the next transfer to fail and as a workaround the ESPI block is disabled / re-enabled in fsl_espi_change_mode. This seems to clear the FIFO's (although it's not mentioned in the spec). With this change the TX FIFO is filled as much as possible initially and whenever the ISR is called. Also the exact number of bytes is transferred. The spinlock protects against a potential race if the first interrupt occurs whilst the TX FIFO is still being initially filled. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:25:58 -06:00
/* if events is zero transfer has not started and tx fifo is empty */
tx_fifo_avail = events ? SPIE_TXCNT(events) : FSL_ESPI_FIFO_SIZE;
spi: fsl-espi: eliminate need for linearization when writing to hardware Eliminate need for linearization when writing to the hardware and read from the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:24 -07:00
start:
tx_left = espi->tx_t->len - espi->tx_pos;
tx_buf = espi->tx_t->tx_buf;
while (tx_fifo_avail >= min(4U, tx_left) && tx_left) {
if (tx_left >= 4) {
if (!tx_buf)
fsl_espi_write_reg(espi, ESPI_SPITF, 0);
else if (espi->swab)
fsl_espi_write_reg(espi, ESPI_SPITF,
swahb32p(tx_buf + espi->tx_pos));
else
fsl_espi_write_reg(espi, ESPI_SPITF,
*(u32 *)(tx_buf + espi->tx_pos));
espi->tx_pos += 4;
tx_left -= 4;
spi: fsl-espi: fix and improve writing to TX FIFO This change addresses two issues: - If the TX FIFO is full the ISR polls until there's free space again. An ISR should never wait for something. - Currently the number of bytes to transfer is rounded up to the next multiple of 4. For most transfers therefore few bytes remain in the TX FIFO after end of transfer. This would cause the next transfer to fail and as a workaround the ESPI block is disabled / re-enabled in fsl_espi_change_mode. This seems to clear the FIFO's (although it's not mentioned in the spec). With this change the TX FIFO is filled as much as possible initially and whenever the ISR is called. Also the exact number of bytes is transferred. The spinlock protects against a potential race if the first interrupt occurs whilst the TX FIFO is still being initially filled. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:25:58 -06:00
tx_fifo_avail -= 4;
spi: fsl-espi: eliminate need for linearization when writing to hardware Eliminate need for linearization when writing to the hardware and read from the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:24 -07:00
} else if (tx_left >= 2 && tx_buf && espi->swab) {
fsl_espi_write_reg16(espi, ESPI_SPITF,
swab16p(tx_buf + espi->tx_pos));
espi->tx_pos += 2;
tx_left -= 2;
tx_fifo_avail -= 2;
spi: fsl-espi: fix and improve writing to TX FIFO This change addresses two issues: - If the TX FIFO is full the ISR polls until there's free space again. An ISR should never wait for something. - Currently the number of bytes to transfer is rounded up to the next multiple of 4. For most transfers therefore few bytes remain in the TX FIFO after end of transfer. This would cause the next transfer to fail and as a workaround the ESPI block is disabled / re-enabled in fsl_espi_change_mode. This seems to clear the FIFO's (although it's not mentioned in the spec). With this change the TX FIFO is filled as much as possible initially and whenever the ISR is called. Also the exact number of bytes is transferred. The spinlock protects against a potential race if the first interrupt occurs whilst the TX FIFO is still being initially filled. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:25:58 -06:00
} else {
spi: fsl-espi: eliminate need for linearization when writing to hardware Eliminate need for linearization when writing to the hardware and read from the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:24 -07:00
if (!tx_buf)
fsl_espi_write_reg8(espi, ESPI_SPITF, 0);
else
fsl_espi_write_reg8(espi, ESPI_SPITF,
*(u8 *)(tx_buf + espi->tx_pos));
espi->tx_pos += 1;
tx_left -= 1;
spi: fsl-espi: fix and improve writing to TX FIFO This change addresses two issues: - If the TX FIFO is full the ISR polls until there's free space again. An ISR should never wait for something. - Currently the number of bytes to transfer is rounded up to the next multiple of 4. For most transfers therefore few bytes remain in the TX FIFO after end of transfer. This would cause the next transfer to fail and as a workaround the ESPI block is disabled / re-enabled in fsl_espi_change_mode. This seems to clear the FIFO's (although it's not mentioned in the spec). With this change the TX FIFO is filled as much as possible initially and whenever the ISR is called. Also the exact number of bytes is transferred. The spinlock protects against a potential race if the first interrupt occurs whilst the TX FIFO is still being initially filled. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:25:58 -06:00
tx_fifo_avail -= 1;
}
spi: fsl-espi: eliminate need for linearization when writing to hardware Eliminate need for linearization when writing to the hardware and read from the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:24 -07:00
}
if (!tx_left) {
/* Last transfer finished, in rxskip mode only one is needed */
if (list_is_last(&espi->tx_t->transfer_list,
espi->m_transfers) || espi->rxskip) {
espi->tx_done = true;
return;
}
espi->tx_t = list_next_entry(espi->tx_t, transfer_list);
espi->tx_pos = 0;
/* continue with next transfer if tx fifo is not full */
if (tx_fifo_avail)
goto start;
}
spi: fsl-espi: fix and improve writing to TX FIFO This change addresses two issues: - If the TX FIFO is full the ISR polls until there's free space again. An ISR should never wait for something. - Currently the number of bytes to transfer is rounded up to the next multiple of 4. For most transfers therefore few bytes remain in the TX FIFO after end of transfer. This would cause the next transfer to fail and as a workaround the ESPI block is disabled / re-enabled in fsl_espi_change_mode. This seems to clear the FIFO's (although it's not mentioned in the spec). With this change the TX FIFO is filled as much as possible initially and whenever the ISR is called. Also the exact number of bytes is transferred. The spinlock protects against a potential race if the first interrupt occurs whilst the TX FIFO is still being initially filled. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:25:58 -06:00
}
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
static void fsl_espi_read_rx_fifo(struct fsl_espi *espi, u32 events)
spi: fsl-espi: fix and improve reading from RX FIFO Currently the driver polls in the ISR for enough bytes in the RX FIFO. An ISR should never do this. Change it to read as much as possible whenever the ISR is called. This also allows to significantly simplify the code. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:27:35 -06:00
{
u32 rx_fifo_avail = SPIE_RXCNT(events);
spi: fsl-espi: eliminate need for linearization when reading from hardware Eliminate need for linearization when reading from the hardware and write to the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:57 -07:00
unsigned int rx_left;
void *rx_buf;
spi: fsl-espi: fix and improve reading from RX FIFO Currently the driver polls in the ISR for enough bytes in the RX FIFO. An ISR should never do this. Change it to read as much as possible whenever the ISR is called. This also allows to significantly simplify the code. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:27:35 -06:00
spi: fsl-espi: eliminate need for linearization when reading from hardware Eliminate need for linearization when reading from the hardware and write to the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:57 -07:00
start:
rx_left = espi->rx_t->len - espi->rx_pos;
rx_buf = espi->rx_t->rx_buf;
while (rx_fifo_avail >= min(4U, rx_left) && rx_left) {
if (rx_left >= 4) {
u32 val = fsl_espi_read_reg(espi, ESPI_SPIRF);
if (rx_buf && espi->swab)
*(u32 *)(rx_buf + espi->rx_pos) = swahb32(val);
else if (rx_buf)
*(u32 *)(rx_buf + espi->rx_pos) = val;
espi->rx_pos += 4;
rx_left -= 4;
spi: fsl-espi: fix and improve reading from RX FIFO Currently the driver polls in the ISR for enough bytes in the RX FIFO. An ISR should never do this. Change it to read as much as possible whenever the ISR is called. This also allows to significantly simplify the code. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:27:35 -06:00
rx_fifo_avail -= 4;
spi: fsl-espi: eliminate need for linearization when reading from hardware Eliminate need for linearization when reading from the hardware and write to the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:57 -07:00
} else if (rx_left >= 2 && rx_buf && espi->swab) {
u16 val = fsl_espi_read_reg16(espi, ESPI_SPIRF);
*(u16 *)(rx_buf + espi->rx_pos) = swab16(val);
espi->rx_pos += 2;
rx_left -= 2;
rx_fifo_avail -= 2;
spi: fsl-espi: fix and improve reading from RX FIFO Currently the driver polls in the ISR for enough bytes in the RX FIFO. An ISR should never do this. Change it to read as much as possible whenever the ISR is called. This also allows to significantly simplify the code. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:27:35 -06:00
} else {
spi: fsl-espi: eliminate need for linearization when reading from hardware Eliminate need for linearization when reading from the hardware and write to the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:57 -07:00
u8 val = fsl_espi_read_reg8(espi, ESPI_SPIRF);
if (rx_buf)
*(u8 *)(rx_buf + espi->rx_pos) = val;
espi->rx_pos += 1;
rx_left -= 1;
spi: fsl-espi: fix and improve reading from RX FIFO Currently the driver polls in the ISR for enough bytes in the RX FIFO. An ISR should never do this. Change it to read as much as possible whenever the ISR is called. This also allows to significantly simplify the code. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:27:35 -06:00
rx_fifo_avail -= 1;
}
spi: fsl-espi: eliminate need for linearization when reading from hardware Eliminate need for linearization when reading from the hardware and write to the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:57 -07:00
}
if (!rx_left) {
if (list_is_last(&espi->rx_t->transfer_list,
espi->m_transfers)) {
espi->rx_done = true;
return;
}
espi->rx_t = list_next_entry(espi->rx_t, transfer_list);
espi->rx_pos = 0;
/* continue with next transfer if rx fifo is not empty */
if (rx_fifo_avail)
goto start;
}
spi: fsl-espi: fix and improve reading from RX FIFO Currently the driver polls in the ISR for enough bytes in the RX FIFO. An ISR should never do this. Change it to read as much as possible whenever the ISR is called. This also allows to significantly simplify the code. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:27:35 -06:00
}
spi: fsl-espi: change return type of fsl_espi_setup_transfer to void fsl_espi_setup_transfer always returns 0, so change the return type to void. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-08-24 22:44:42 -06:00
static void fsl_espi_setup_transfer(struct spi_device *spi,
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
struct spi_transfer *t)
{
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
struct fsl_espi *espi = spi_master_get_devdata(spi->master);
spi: fsl-espi: simplify fsl_espi_setup_transfer If t is not null then the SPI core takes care that bits_per_word and speed_hz are populated. This allows to simplify fsl_espi_setup_transfer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-13 15:15:45 -06:00
int bits_per_word = t ? t->bits_per_word : spi->bits_per_word;
spi: fsl-espi: fix support for all available clock rates According to NXP ESPI datasheet, the SPI clock rate is: spi_clk = System_Clock / ( 2 * DIV16 * ( 1 + PM ) ) Where System_Clock is the platform clock divided by 2, DIV16 may be 1 or 16, and PM is a 4 bits integer (0 to 15). Isolating PM on the expression, we get: PM = (System_Clock / ( 2 * DIV16 * spi_clk ) ) - 1 Where System_Clock = mpc8xxx_spi->spibrg / 2, spi_clk = hz, and DIV16 = 1 or DIV16 = 16. So, PM = (mpc8xxx_spi->spibrg / ( 4 * hz) ) - 1 or PM = (mpc8xxx_spi->spibrg / ( 16 * 4 * hz) ) - 1 Current spi-fsl-espi driver can't configure the HW for all supported clock rates. It filters out clock rates for PM = 0 and PM = 1. This patch allows all range of supported clock rates to be configured on the ESPI controller. Signed-off-by: Paulo Zaneti <paulo.zaneti@datacom.ind.br> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-29 03:02:19 -06:00
u32 pm, hz = t ? t->speed_hz : spi->max_speed_hz;
spi: fsl-espi: introduce struct fsl_espi_cs Very little from struct spi_mpc8xxx_cs is relevant for fsl-espi. Therefore replace it with struct fsl_espi_cs. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:38:05 -07:00
struct fsl_espi_cs *cs = spi_get_ctldata(spi);
spi: fsl-espi: don't write ESPI_SPMODE register if the mode doesn't change There's no need to bother the chip if the mode doesn't change. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-04 14:01:12 -06:00
u32 hw_mode_old = cs->hw_mode;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
/* mask out bits we are going to set */
cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
spi: fsl-espi: simplify fsl_espi_setup_transfer Simplify fsl_espi_setup_transfer a little. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-04 01:56:57 -06:00
cs->hw_mode |= CSMODE_LEN(bits_per_word - 1);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
pm = DIV_ROUND_UP(espi->spibrg, hz * 4) - 1;
spi: fsl-espi: fix support for all available clock rates According to NXP ESPI datasheet, the SPI clock rate is: spi_clk = System_Clock / ( 2 * DIV16 * ( 1 + PM ) ) Where System_Clock is the platform clock divided by 2, DIV16 may be 1 or 16, and PM is a 4 bits integer (0 to 15). Isolating PM on the expression, we get: PM = (System_Clock / ( 2 * DIV16 * spi_clk ) ) - 1 Where System_Clock = mpc8xxx_spi->spibrg / 2, spi_clk = hz, and DIV16 = 1 or DIV16 = 16. So, PM = (mpc8xxx_spi->spibrg / ( 4 * hz) ) - 1 or PM = (mpc8xxx_spi->spibrg / ( 16 * 4 * hz) ) - 1 Current spi-fsl-espi driver can't configure the HW for all supported clock rates. It filters out clock rates for PM = 0 and PM = 1. This patch allows all range of supported clock rates to be configured on the ESPI controller. Signed-off-by: Paulo Zaneti <paulo.zaneti@datacom.ind.br> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-29 03:02:19 -06:00
if (pm > 15) {
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
cs->hw_mode |= CSMODE_DIV16;
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
pm = DIV_ROUND_UP(espi->spibrg, hz * 16 * 4) - 1;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
}
cs->hw_mode |= CSMODE_PM(pm);
spi: fsl-espi: don't write ESPI_SPMODE register if the mode doesn't change There's no need to bother the chip if the mode doesn't change. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-04 14:01:12 -06:00
/* don't write the mode register if the mode doesn't change */
if (cs->hw_mode != hw_mode_old)
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
fsl_espi_write_reg(espi, ESPI_SPMODEx(spi->chip_select),
spi: fsl-espi: don't write ESPI_SPMODE register if the mode doesn't change There's no need to bother the chip if the mode doesn't change. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-04 14:01:12 -06:00
cs->hw_mode);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
}
static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
{
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
struct fsl_espi *espi = spi_master_get_devdata(spi->master);
spi: fsl-espi: eliminate need for linearization when reading from hardware Eliminate need for linearization when reading from the hardware and write to the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:57 -07:00
unsigned int rx_len = t->len;
spi: fsl-espi: add support for ESPI RXSKIP mode This patch adds support for ESPI RXSKIP mode. This mode is optimized for flash reads: - sends a number of bytes and then reads a number of bytes - shifts out zeros automatically when reading Supporting RXSKIP mode is a prerequisite for supporting dual output read mode. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-09 14:58:01 -07:00
u32 mask, spcom;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
int ret;
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
reinit_completion(&espi->done);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
/* Set SPCOM[CS] and SPCOM[TRANLEN] field */
spi: fsl-espi: add support for ESPI RXSKIP mode This patch adds support for ESPI RXSKIP mode. This mode is optimized for flash reads: - sends a number of bytes and then reads a number of bytes - shifts out zeros automatically when reading Supporting RXSKIP mode is a prerequisite for supporting dual output read mode. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-09 14:58:01 -07:00
spcom = SPCOM_CS(spi->chip_select);
spcom |= SPCOM_TRANLEN(t->len - 1);
/* configure RXSKIP mode */
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
if (espi->rxskip) {
spcom |= SPCOM_RXSKIP(espi->rxskip);
spi: fsl-espi: eliminate need for linearization when reading from hardware Eliminate need for linearization when reading from the hardware and write to the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:57 -07:00
rx_len = t->len - espi->rxskip;
spi: fsl-espi: add support for dual output read mode This patch adds support for dual output read mode. It was successfully tested on a P1014-based device with S25FL128S SPINOR flash. With 50MHz SPI clock the read rate is 11MByte/s. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-09 14:58:34 -07:00
if (t->rx_nbits == SPI_NBITS_DUAL)
spcom |= SPCOM_DO;
spi: fsl-espi: add support for ESPI RXSKIP mode This patch adds support for ESPI RXSKIP mode. This mode is optimized for flash reads: - sends a number of bytes and then reads a number of bytes - shifts out zeros automatically when reading Supporting RXSKIP mode is a prerequisite for supporting dual output read mode. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-09 14:58:01 -07:00
}
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
fsl_espi_write_reg(espi, ESPI_SPCOM, spcom);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: make better use of the RX FIFO So far an interrupt is triggered whenever there's at least one byte in the RX FIFO. This results in a unnecessarily high number of interrupts. Change this to generate an interrupt if - RX FIFO is half full (except if all bytes to read fit into the RX FIFO anyway) - end of transfer has been reached This way the number of interrupts can be significantly reduced. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:27:56 -06:00
/* enable interrupts */
mask = SPIM_DON;
spi: fsl-espi: eliminate need for linearization when reading from hardware Eliminate need for linearization when reading from the hardware and write to the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:57 -07:00
if (rx_len > FSL_ESPI_FIFO_SIZE)
spi: fsl-espi: make better use of the RX FIFO So far an interrupt is triggered whenever there's at least one byte in the RX FIFO. This results in a unnecessarily high number of interrupts. Change this to generate an interrupt if - RX FIFO is half full (except if all bytes to read fit into the RX FIFO anyway) - end of transfer has been reached This way the number of interrupts can be significantly reduced. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:27:56 -06:00
mask |= SPIM_RXT;
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
fsl_espi_write_reg(espi, ESPI_SPIM, mask);
spi: fsl-espi: merge fsl_espi_bufs and fsl_espi_cpu_bufs fsl_espi_bufs and fsl_espi_cpu_bufs are very small that we can merge them. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:53:01 -06:00
spi: fsl-espi: fix and improve writing to TX FIFO This change addresses two issues: - If the TX FIFO is full the ISR polls until there's free space again. An ISR should never wait for something. - Currently the number of bytes to transfer is rounded up to the next multiple of 4. For most transfers therefore few bytes remain in the TX FIFO after end of transfer. This would cause the next transfer to fail and as a workaround the ESPI block is disabled / re-enabled in fsl_espi_change_mode. This seems to clear the FIFO's (although it's not mentioned in the spec). With this change the TX FIFO is filled as much as possible initially and whenever the ISR is called. Also the exact number of bytes is transferred. The spinlock protects against a potential race if the first interrupt occurs whilst the TX FIFO is still being initially filled. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:25:58 -06:00
/* Prevent filling the fifo from getting interrupted */
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
spin_lock_irq(&espi->lock);
fsl_espi_fill_tx_fifo(espi, 0);
spin_unlock_irq(&espi->lock);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi/fsl-espi: Don't wait transaction completion forever Because the eSPI driver uses wait_for_completion(), any stuck-able phenomenon at half-way transaction progress made worker task hang up. This phenomenon is perhaps caused by eSPI device errata which seems not to be published from vendor site yet. Anyway, we fix hang task by using fixed 2 seconds timeout that is our preferred value for eSPI maximum transaction size. It seems to be better that eSPI driver can detect this stuck and report error (EMSGSIZE) to the upper device driver because the upper device driver can decide to retry or recover. Signed-off-by: Nobuteru Hayashi <hayashi.nbb@ncos.nec.co.jp> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-03-18 05:35:21 -06:00
/* Won't hang up forever, SPI bus sometimes got lost interrupts... */
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
ret = wait_for_completion_timeout(&espi->done, 2 * HZ);
spi/fsl-espi: Don't wait transaction completion forever Because the eSPI driver uses wait_for_completion(), any stuck-able phenomenon at half-way transaction progress made worker task hang up. This phenomenon is perhaps caused by eSPI device errata which seems not to be published from vendor site yet. Anyway, we fix hang task by using fixed 2 seconds timeout that is our preferred value for eSPI maximum transaction size. It seems to be better that eSPI driver can detect this stuck and report error (EMSGSIZE) to the upper device driver because the upper device driver can decide to retry or recover. Signed-off-by: Nobuteru Hayashi <hayashi.nbb@ncos.nec.co.jp> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-03-18 05:35:21 -06:00
if (ret == 0)
spi: fsl-espi: eliminate need for linearization when writing to hardware Eliminate need for linearization when writing to the hardware and read from the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:24 -07:00
dev_err(espi->dev, "Transfer timed out!\n");
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
/* disable rx ints */
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
fsl_espi_write_reg(espi, ESPI_SPIM, 0);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: extend and improve transfer error handling Extend and improve transfer error handling - in case of timeout report also number of remaining rx bytes - in case of timeout return ETIMEDOUT instead of EMSGSIZE - add sanity checks after all bytes have been sent / read: - check that HW has flag SPIE_DON set - check that RX / TX FIFO are empty Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:28:02 -06:00
return ret == 0 ? -ETIMEDOUT : 0;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
}
spi: fsl-espi: merge fsl_espi_trans and fsl_espi_do_trans Merge both functions to reduce source code size and improve readability. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:54:51 -06:00
static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans)
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
{
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
struct fsl_espi *espi = spi_master_get_devdata(m->spi->master);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
struct spi_device *spi = m->spi;
spi: fsl-espi: merge fsl_espi_trans and fsl_espi_do_trans Merge both functions to reduce source code size and improve readability. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:54:51 -06:00
int ret;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: determine need for byte swap only once Determine need for byte swap only once and store it in new member swab in struct fsl_espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:58:49 -07:00
/* In case of LSB-first and bits_per_word > 8 byte-swap all words */
espi->swab = spi->mode & SPI_LSB_FIRST && trans->bits_per_word > 8;
spi: fsl-espi: eliminate need for linearization when writing to hardware Eliminate need for linearization when writing to the hardware and read from the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:24 -07:00
espi->m_transfers = &m->transfers;
espi->tx_t = list_first_entry(&m->transfers, struct spi_transfer,
transfer_list);
espi->tx_pos = 0;
espi->tx_done = false;
spi: fsl-espi: eliminate need for linearization when reading from hardware Eliminate need for linearization when reading from the hardware and write to the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:57 -07:00
espi->rx_t = list_first_entry(&m->transfers, struct spi_transfer,
transfer_list);
espi->rx_pos = 0;
espi->rx_done = false;
spi: fsl-espi: eliminate need for linearization when writing to hardware Eliminate need for linearization when writing to the hardware and read from the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:24 -07:00
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
espi->rxskip = fsl_espi_check_rxskip_mode(m);
if (trans->rx_nbits == SPI_NBITS_DUAL && !espi->rxskip) {
dev_err(espi->dev, "Dual output mode requires RXSKIP mode!\n");
spi: fsl-espi: add support for dual output read mode This patch adds support for dual output read mode. It was successfully tested on a P1014-based device with S25FL128S SPINOR flash. With 50MHz SPI clock the read rate is 11MByte/s. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-09 14:58:34 -07:00
return -EINVAL;
}
spi: fsl-espi: eliminate need for linearization when reading from hardware Eliminate need for linearization when reading from the hardware and write to the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:57 -07:00
/* In RXSKIP mode skip first transfer for reads */
if (espi->rxskip)
espi->rx_t = list_next_entry(espi->rx_t, transfer_list);
spi: fsl-espi: eliminate struct fsl_espi_transfer The remaining elements of struct fsl_espi_transfer are part of struct spi_transfer anyway. So we can get rid of struct fsl_espi_transfer and use a struct spi_transfer only. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:52:06 -06:00
fsl_espi_setup_transfer(spi, trans);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: improve message length handling Move checking for a zero-length message up in the call chain and use m->frame_length instead of re-calculating the overall length of all transfers in the message. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:54:35 -06:00
ret = fsl_espi_bufs(spi, trans);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: eliminate struct fsl_espi_transfer The remaining elements of struct fsl_espi_transfer are part of struct spi_transfer anyway. So we can get rid of struct fsl_espi_transfer and use a struct spi_transfer only. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:52:06 -06:00
if (trans->delay_usecs)
udelay(trans->delay_usecs);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: remove element status from struct fsl_espi_transfer Use the return values of the functions in the call chain to transport status information instead of using an element in struct fsl_espi_transfer for this. This is more in line with the general approach how to handle status information and is one step further to eventually get rid of struct fsl_espi_transfer completely. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:51:10 -06:00
return ret;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
}
spi: fsl-(e)spi: migrate to generic master queueing Migrates the fsl-(e)spi driver to use the generic master queuing. Avoids the "master is unqueued, this is deprecated" warning. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-12-02 23:56:17 -07:00
static int fsl_espi_do_one_msg(struct spi_master *master,
struct spi_message *m)
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
{
spi: fsl-espi: add support for dual output read mode This patch adds support for dual output read mode. It was successfully tested on a P1014-based device with S25FL128S SPINOR flash. With 50MHz SPI clock the read rate is 11MByte/s. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-09 14:58:34 -07:00
unsigned int delay_usecs = 0, rx_nbits = 0;
spi: fsl-espi: eliminate struct fsl_espi_transfer The remaining elements of struct fsl_espi_transfer are part of struct spi_transfer anyway. So we can get rid of struct fsl_espi_transfer and use a struct spi_transfer only. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:52:06 -06:00
struct spi_transfer *t, trans = {};
spi: fsl-espi: remove element status from struct fsl_espi_transfer Use the return values of the functions in the call chain to transport status information instead of using an element in struct fsl_espi_transfer for this. This is more in line with the general approach how to handle status information and is one step further to eventually get rid of struct fsl_espi_transfer completely. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:51:10 -06:00
int ret;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: factor out initial message checking Checking the message is currently done at diffrent places in the driver. Factor it out to fsl_espi_check_message. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:53:38 -06:00
ret = fsl_espi_check_message(m);
if (ret)
goto out;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
list_for_each_entry(t, &m->transfers, transfer_list) {
spi: fsl-espi: centralize populating struct spi_transfer Better structure the code by population all elements of struct spi_transfer in one place. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:54:00 -06:00
if (t->delay_usecs > delay_usecs)
delay_usecs = t->delay_usecs;
spi: fsl-espi: add support for dual output read mode This patch adds support for dual output read mode. It was successfully tested on a P1014-based device with S25FL128S SPINOR flash. With 50MHz SPI clock the read rate is 11MByte/s. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-09 14:58:34 -07:00
if (t->rx_nbits > rx_nbits)
rx_nbits = t->rx_nbits;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
}
spi: fsl-espi: centralize populating struct spi_transfer Better structure the code by population all elements of struct spi_transfer in one place. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:54:00 -06:00
t = list_first_entry(&m->transfers, struct spi_transfer,
transfer_list);
spi: fsl-espi: improve message length handling Move checking for a zero-length message up in the call chain and use m->frame_length instead of re-calculating the overall length of all transfers in the message. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:54:35 -06:00
trans.len = m->frame_length;
spi: fsl-espi: centralize populating struct spi_transfer Better structure the code by population all elements of struct spi_transfer in one place. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:54:00 -06:00
trans.speed_hz = t->speed_hz;
trans.bits_per_word = t->bits_per_word;
trans.delay_usecs = delay_usecs;
spi: fsl-espi: add support for dual output read mode This patch adds support for dual output read mode. It was successfully tested on a P1014-based device with S25FL128S SPINOR flash. With 50MHz SPI clock the read rate is 11MByte/s. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-09 14:58:34 -07:00
trans.rx_nbits = rx_nbits;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: improve message length handling Move checking for a zero-length message up in the call chain and use m->frame_length instead of re-calculating the overall length of all transfers in the message. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:54:35 -06:00
if (trans.len)
ret = fsl_espi_trans(m, &trans);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: eliminate struct fsl_espi_transfer The remaining elements of struct fsl_espi_transfer are part of struct spi_transfer anyway. So we can get rid of struct fsl_espi_transfer and use a struct spi_transfer only. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:52:06 -06:00
m->actual_length = ret ? 0 : trans.len;
spi: fsl-espi: factor out initial message checking Checking the message is currently done at diffrent places in the driver. Factor it out to fsl_espi_check_message. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:53:38 -06:00
out:
spi: fsl-espi: fix status handling in fsl_espi_do_one_msg If an error occurred during message handling return this error instead of always returning 0 and align the code with the generic implementation in spi_transfer_one_message. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:51:29 -06:00
if (m->status == -EINPROGRESS)
m->status = ret;
spi: fsl-(e)spi: migrate to generic master queueing Migrates the fsl-(e)spi driver to use the generic master queuing. Avoids the "master is unqueued, this is deprecated" warning. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-12-02 23:56:17 -07:00
spi_finalize_current_message(master);
spi: fsl-espi: fix status handling in fsl_espi_do_one_msg If an error occurred during message handling return this error instead of always returning 0 and align the code with the generic implementation in spi_transfer_one_message. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-07 14:51:29 -06:00
return ret;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
}
static int fsl_espi_setup(struct spi_device *spi)
{
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
struct fsl_espi *espi;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
u32 loop_mode;
spi: fsl-espi: introduce struct fsl_espi_cs Very little from struct spi_mpc8xxx_cs is relevant for fsl-espi. Therefore replace it with struct fsl_espi_cs. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:38:05 -07:00
struct fsl_espi_cs *cs = spi_get_ctldata(spi);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
if (!cs) {
spi: fsl: Don't use devm_kzalloc in master->setup callback device_add() expects that any memory allocated via devm_* API is only done in the device's probe function. Fix below boot warning: [ 3.092348] WARNING: at drivers/base/dd.c:286 [ 3.096637] Modules linked in: [ 3.099697] CPU: 0 PID: 25 Comm: kworker/u2:1 Tainted: G W 3.16.1-s3k-drv-999-svn5771_knld-999 #158 [ 3.109610] Workqueue: deferwq deferred_probe_work_func [ 3.114736] task: c787f020 ti: c790c000 task.ti: c790c000 [ 3.120062] NIP: c01df158 LR: c01df144 CTR: 00000000 [ 3.124983] REGS: c790db30 TRAP: 0700 Tainted: G W (3.16.1-s3k-drv-999-svn5771_knld-999) [ 3.134162] MSR: 00029032 <EE,ME,IR,DR,RI> CR: 22002082 XER: 20000000 [ 3.140703] [ 3.140703] GPR00: 00000001 c790dbe0 c787f020 00000044 00000054 00000308 c056da0e 20737069 [ 3.140703] GPR08: 33323736 000ebfe0 00000308 000ebfdf 22002082 00000000 c046c5a0 c046c608 [ 3.140703] GPR16: c046c614 c046c620 c046c62c c046c638 c046c648 c046c654 c046c68c c046c6c4 [ 3.140703] GPR24: 00000000 00000000 00000003 c0401aa0 c0596638 c059662c c054e7a8 c7996800 [ 3.170102] NIP [c01df158] driver_probe_device+0xf8/0x334 [ 3.175431] LR [c01df144] driver_probe_device+0xe4/0x334 [ 3.180633] Call Trace: [ 3.183093] [c790dbe0] [c01df144] driver_probe_device+0xe4/0x334 (unreliable) [ 3.190147] [c790dc10] [c01dd15c] bus_for_each_drv+0x7c/0xc0 [ 3.195741] [c790dc40] [c01df5fc] device_attach+0xcc/0xf8 [ 3.201076] [c790dc60] [c01dd6d4] bus_probe_device+0xb4/0xc4 [ 3.206666] [c790dc80] [c01db9f8] device_add+0x270/0x564 [ 3.211923] [c790dcc0] [c0219e84] spi_add_device+0xc0/0x190 [ 3.217427] [c790dce0] [c021a79c] spi_register_master+0x720/0x834 [ 3.223455] [c790dd40] [c021cb48] of_fsl_spi_probe+0x55c/0x614 [ 3.229234] [c790dda0] [c01e0d2c] platform_drv_probe+0x30/0x74 [ 3.234987] [c790ddb0] [c01df18c] driver_probe_device+0x12c/0x334 [ 3.241008] [c790dde0] [c01dd15c] bus_for_each_drv+0x7c/0xc0 [ 3.246602] [c790de10] [c01df5fc] device_attach+0xcc/0xf8 [ 3.251937] [c790de30] [c01dd6d4] bus_probe_device+0xb4/0xc4 [ 3.257536] [c790de50] [c01de9d8] deferred_probe_work_func+0x98/0xe0 [ 3.263816] [c790de70] [c00305b8] process_one_work+0x18c/0x440 [ 3.269577] [c790dea0] [c0030a00] worker_thread+0x194/0x67c [ 3.275105] [c790def0] [c0039198] kthread+0xd0/0xe4 [ 3.279911] [c790df40] [c000c6d0] ret_from_kernel_thread+0x5c/0x64 [ 3.285970] Instruction dump: [ 3.288900] 80de0000 419e01d0 3b7b0038 3c60c046 7f65db78 38635264 48211b99 813f00a0 [ 3.296559] 381f00a0 7d290278 3169ffff 7c0b4910 <0f000000> 93df0044 7fe3fb78 4bfffd4d Reported-by: leroy christophe <christophe.leroy@c-s.fr> Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
2014-08-30 22:44:09 -06:00
cs = kzalloc(sizeof(*cs), GFP_KERNEL);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
if (!cs)
return -ENOMEM;
spi: fsl: Don't use devm_kzalloc in master->setup callback device_add() expects that any memory allocated via devm_* API is only done in the device's probe function. Fix below boot warning: [ 3.092348] WARNING: at drivers/base/dd.c:286 [ 3.096637] Modules linked in: [ 3.099697] CPU: 0 PID: 25 Comm: kworker/u2:1 Tainted: G W 3.16.1-s3k-drv-999-svn5771_knld-999 #158 [ 3.109610] Workqueue: deferwq deferred_probe_work_func [ 3.114736] task: c787f020 ti: c790c000 task.ti: c790c000 [ 3.120062] NIP: c01df158 LR: c01df144 CTR: 00000000 [ 3.124983] REGS: c790db30 TRAP: 0700 Tainted: G W (3.16.1-s3k-drv-999-svn5771_knld-999) [ 3.134162] MSR: 00029032 <EE,ME,IR,DR,RI> CR: 22002082 XER: 20000000 [ 3.140703] [ 3.140703] GPR00: 00000001 c790dbe0 c787f020 00000044 00000054 00000308 c056da0e 20737069 [ 3.140703] GPR08: 33323736 000ebfe0 00000308 000ebfdf 22002082 00000000 c046c5a0 c046c608 [ 3.140703] GPR16: c046c614 c046c620 c046c62c c046c638 c046c648 c046c654 c046c68c c046c6c4 [ 3.140703] GPR24: 00000000 00000000 00000003 c0401aa0 c0596638 c059662c c054e7a8 c7996800 [ 3.170102] NIP [c01df158] driver_probe_device+0xf8/0x334 [ 3.175431] LR [c01df144] driver_probe_device+0xe4/0x334 [ 3.180633] Call Trace: [ 3.183093] [c790dbe0] [c01df144] driver_probe_device+0xe4/0x334 (unreliable) [ 3.190147] [c790dc10] [c01dd15c] bus_for_each_drv+0x7c/0xc0 [ 3.195741] [c790dc40] [c01df5fc] device_attach+0xcc/0xf8 [ 3.201076] [c790dc60] [c01dd6d4] bus_probe_device+0xb4/0xc4 [ 3.206666] [c790dc80] [c01db9f8] device_add+0x270/0x564 [ 3.211923] [c790dcc0] [c0219e84] spi_add_device+0xc0/0x190 [ 3.217427] [c790dce0] [c021a79c] spi_register_master+0x720/0x834 [ 3.223455] [c790dd40] [c021cb48] of_fsl_spi_probe+0x55c/0x614 [ 3.229234] [c790dda0] [c01e0d2c] platform_drv_probe+0x30/0x74 [ 3.234987] [c790ddb0] [c01df18c] driver_probe_device+0x12c/0x334 [ 3.241008] [c790dde0] [c01dd15c] bus_for_each_drv+0x7c/0xc0 [ 3.246602] [c790de10] [c01df5fc] device_attach+0xcc/0xf8 [ 3.251937] [c790de30] [c01dd6d4] bus_probe_device+0xb4/0xc4 [ 3.257536] [c790de50] [c01de9d8] deferred_probe_work_func+0x98/0xe0 [ 3.263816] [c790de70] [c00305b8] process_one_work+0x18c/0x440 [ 3.269577] [c790dea0] [c0030a00] worker_thread+0x194/0x67c [ 3.275105] [c790def0] [c0039198] kthread+0xd0/0xe4 [ 3.279911] [c790df40] [c000c6d0] ret_from_kernel_thread+0x5c/0x64 [ 3.285970] Instruction dump: [ 3.288900] 80de0000 419e01d0 3b7b0038 3c60c046 7f65db78 38635264 48211b99 813f00a0 [ 3.296559] 381f00a0 7d290278 3169ffff 7c0b4910 <0f000000> 93df0044 7fe3fb78 4bfffd4d Reported-by: leroy christophe <christophe.leroy@c-s.fr> Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
2014-08-30 22:44:09 -06:00
spi_set_ctldata(spi, cs);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
}
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
espi = spi_master_get_devdata(spi->master);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
pm_runtime_get_sync(espi->dev);
spi: fsl-espi: add runtime PM Add runtime PM and use autosuspend instead of suspending the SPI controller after each transfer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-26 13:21:55 -06:00
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
cs->hw_mode = fsl_espi_read_reg(espi, ESPI_SPMODEx(spi->chip_select));
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
/* mask out bits we are going to set */
cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
| CSMODE_REV);
if (spi->mode & SPI_CPHA)
cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
if (spi->mode & SPI_CPOL)
cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
if (!(spi->mode & SPI_LSB_FIRST))
cs->hw_mode |= CSMODE_REV;
/* Handle the loop mode */
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
loop_mode = fsl_espi_read_reg(espi, ESPI_SPMODE);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
loop_mode &= ~SPMODE_LOOP;
if (spi->mode & SPI_LOOP)
loop_mode |= SPMODE_LOOP;
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
fsl_espi_write_reg(espi, ESPI_SPMODE, loop_mode);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: change return type of fsl_espi_setup_transfer to void fsl_espi_setup_transfer always returns 0, so change the return type to void. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-08-24 22:44:42 -06:00
fsl_espi_setup_transfer(spi, NULL);
spi: fsl-espi: add runtime PM Add runtime PM and use autosuspend instead of suspending the SPI controller after each transfer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-26 13:21:55 -06:00
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
pm_runtime_mark_last_busy(espi->dev);
pm_runtime_put_autosuspend(espi->dev);
spi: fsl-espi: add runtime PM Add runtime PM and use autosuspend instead of suspending the SPI controller after each transfer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-26 13:21:55 -06:00
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
return 0;
}
spi: fsl: Don't use devm_kzalloc in master->setup callback device_add() expects that any memory allocated via devm_* API is only done in the device's probe function. Fix below boot warning: [ 3.092348] WARNING: at drivers/base/dd.c:286 [ 3.096637] Modules linked in: [ 3.099697] CPU: 0 PID: 25 Comm: kworker/u2:1 Tainted: G W 3.16.1-s3k-drv-999-svn5771_knld-999 #158 [ 3.109610] Workqueue: deferwq deferred_probe_work_func [ 3.114736] task: c787f020 ti: c790c000 task.ti: c790c000 [ 3.120062] NIP: c01df158 LR: c01df144 CTR: 00000000 [ 3.124983] REGS: c790db30 TRAP: 0700 Tainted: G W (3.16.1-s3k-drv-999-svn5771_knld-999) [ 3.134162] MSR: 00029032 <EE,ME,IR,DR,RI> CR: 22002082 XER: 20000000 [ 3.140703] [ 3.140703] GPR00: 00000001 c790dbe0 c787f020 00000044 00000054 00000308 c056da0e 20737069 [ 3.140703] GPR08: 33323736 000ebfe0 00000308 000ebfdf 22002082 00000000 c046c5a0 c046c608 [ 3.140703] GPR16: c046c614 c046c620 c046c62c c046c638 c046c648 c046c654 c046c68c c046c6c4 [ 3.140703] GPR24: 00000000 00000000 00000003 c0401aa0 c0596638 c059662c c054e7a8 c7996800 [ 3.170102] NIP [c01df158] driver_probe_device+0xf8/0x334 [ 3.175431] LR [c01df144] driver_probe_device+0xe4/0x334 [ 3.180633] Call Trace: [ 3.183093] [c790dbe0] [c01df144] driver_probe_device+0xe4/0x334 (unreliable) [ 3.190147] [c790dc10] [c01dd15c] bus_for_each_drv+0x7c/0xc0 [ 3.195741] [c790dc40] [c01df5fc] device_attach+0xcc/0xf8 [ 3.201076] [c790dc60] [c01dd6d4] bus_probe_device+0xb4/0xc4 [ 3.206666] [c790dc80] [c01db9f8] device_add+0x270/0x564 [ 3.211923] [c790dcc0] [c0219e84] spi_add_device+0xc0/0x190 [ 3.217427] [c790dce0] [c021a79c] spi_register_master+0x720/0x834 [ 3.223455] [c790dd40] [c021cb48] of_fsl_spi_probe+0x55c/0x614 [ 3.229234] [c790dda0] [c01e0d2c] platform_drv_probe+0x30/0x74 [ 3.234987] [c790ddb0] [c01df18c] driver_probe_device+0x12c/0x334 [ 3.241008] [c790dde0] [c01dd15c] bus_for_each_drv+0x7c/0xc0 [ 3.246602] [c790de10] [c01df5fc] device_attach+0xcc/0xf8 [ 3.251937] [c790de30] [c01dd6d4] bus_probe_device+0xb4/0xc4 [ 3.257536] [c790de50] [c01de9d8] deferred_probe_work_func+0x98/0xe0 [ 3.263816] [c790de70] [c00305b8] process_one_work+0x18c/0x440 [ 3.269577] [c790dea0] [c0030a00] worker_thread+0x194/0x67c [ 3.275105] [c790def0] [c0039198] kthread+0xd0/0xe4 [ 3.279911] [c790df40] [c000c6d0] ret_from_kernel_thread+0x5c/0x64 [ 3.285970] Instruction dump: [ 3.288900] 80de0000 419e01d0 3b7b0038 3c60c046 7f65db78 38635264 48211b99 813f00a0 [ 3.296559] 381f00a0 7d290278 3169ffff 7c0b4910 <0f000000> 93df0044 7fe3fb78 4bfffd4d Reported-by: leroy christophe <christophe.leroy@c-s.fr> Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
2014-08-30 22:44:09 -06:00
static void fsl_espi_cleanup(struct spi_device *spi)
{
spi: fsl-espi: introduce struct fsl_espi_cs Very little from struct spi_mpc8xxx_cs is relevant for fsl-espi. Therefore replace it with struct fsl_espi_cs. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:38:05 -07:00
struct fsl_espi_cs *cs = spi_get_ctldata(spi);
spi: fsl: Don't use devm_kzalloc in master->setup callback device_add() expects that any memory allocated via devm_* API is only done in the device's probe function. Fix below boot warning: [ 3.092348] WARNING: at drivers/base/dd.c:286 [ 3.096637] Modules linked in: [ 3.099697] CPU: 0 PID: 25 Comm: kworker/u2:1 Tainted: G W 3.16.1-s3k-drv-999-svn5771_knld-999 #158 [ 3.109610] Workqueue: deferwq deferred_probe_work_func [ 3.114736] task: c787f020 ti: c790c000 task.ti: c790c000 [ 3.120062] NIP: c01df158 LR: c01df144 CTR: 00000000 [ 3.124983] REGS: c790db30 TRAP: 0700 Tainted: G W (3.16.1-s3k-drv-999-svn5771_knld-999) [ 3.134162] MSR: 00029032 <EE,ME,IR,DR,RI> CR: 22002082 XER: 20000000 [ 3.140703] [ 3.140703] GPR00: 00000001 c790dbe0 c787f020 00000044 00000054 00000308 c056da0e 20737069 [ 3.140703] GPR08: 33323736 000ebfe0 00000308 000ebfdf 22002082 00000000 c046c5a0 c046c608 [ 3.140703] GPR16: c046c614 c046c620 c046c62c c046c638 c046c648 c046c654 c046c68c c046c6c4 [ 3.140703] GPR24: 00000000 00000000 00000003 c0401aa0 c0596638 c059662c c054e7a8 c7996800 [ 3.170102] NIP [c01df158] driver_probe_device+0xf8/0x334 [ 3.175431] LR [c01df144] driver_probe_device+0xe4/0x334 [ 3.180633] Call Trace: [ 3.183093] [c790dbe0] [c01df144] driver_probe_device+0xe4/0x334 (unreliable) [ 3.190147] [c790dc10] [c01dd15c] bus_for_each_drv+0x7c/0xc0 [ 3.195741] [c790dc40] [c01df5fc] device_attach+0xcc/0xf8 [ 3.201076] [c790dc60] [c01dd6d4] bus_probe_device+0xb4/0xc4 [ 3.206666] [c790dc80] [c01db9f8] device_add+0x270/0x564 [ 3.211923] [c790dcc0] [c0219e84] spi_add_device+0xc0/0x190 [ 3.217427] [c790dce0] [c021a79c] spi_register_master+0x720/0x834 [ 3.223455] [c790dd40] [c021cb48] of_fsl_spi_probe+0x55c/0x614 [ 3.229234] [c790dda0] [c01e0d2c] platform_drv_probe+0x30/0x74 [ 3.234987] [c790ddb0] [c01df18c] driver_probe_device+0x12c/0x334 [ 3.241008] [c790dde0] [c01dd15c] bus_for_each_drv+0x7c/0xc0 [ 3.246602] [c790de10] [c01df5fc] device_attach+0xcc/0xf8 [ 3.251937] [c790de30] [c01dd6d4] bus_probe_device+0xb4/0xc4 [ 3.257536] [c790de50] [c01de9d8] deferred_probe_work_func+0x98/0xe0 [ 3.263816] [c790de70] [c00305b8] process_one_work+0x18c/0x440 [ 3.269577] [c790dea0] [c0030a00] worker_thread+0x194/0x67c [ 3.275105] [c790def0] [c0039198] kthread+0xd0/0xe4 [ 3.279911] [c790df40] [c000c6d0] ret_from_kernel_thread+0x5c/0x64 [ 3.285970] Instruction dump: [ 3.288900] 80de0000 419e01d0 3b7b0038 3c60c046 7f65db78 38635264 48211b99 813f00a0 [ 3.296559] 381f00a0 7d290278 3169ffff 7c0b4910 <0f000000> 93df0044 7fe3fb78 4bfffd4d Reported-by: leroy christophe <christophe.leroy@c-s.fr> Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
2014-08-30 22:44:09 -06:00
kfree(cs);
spi_set_ctldata(spi, NULL);
}
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
static void fsl_espi_cpu_irq(struct fsl_espi *espi, u32 events)
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
{
spi: fsl-espi: eliminate need for linearization when reading from hardware Eliminate need for linearization when reading from the hardware and write to the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:57 -07:00
if (!espi->rx_done)
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
fsl_espi_read_rx_fifo(espi, events);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: eliminate need for linearization when writing to hardware Eliminate need for linearization when writing to the hardware and read from the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:24 -07:00
if (!espi->tx_done)
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
fsl_espi_fill_tx_fifo(espi, events);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: eliminate need for linearization when reading from hardware Eliminate need for linearization when reading from the hardware and write to the transfer buffers directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25 15:59:57 -07:00
if (!espi->tx_done || !espi->rx_done)
spi: fsl-espi: extend and improve transfer error handling Extend and improve transfer error handling - in case of timeout report also number of remaining rx bytes - in case of timeout return ETIMEDOUT instead of EMSGSIZE - add sanity checks after all bytes have been sent / read: - check that HW has flag SPIE_DON set - check that RX / TX FIFO are empty Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:28:02 -06:00
return;
/* we're done, but check for errors before returning */
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
events = fsl_espi_read_reg(espi, ESPI_SPIE);
spi: fsl-espi: extend and improve transfer error handling Extend and improve transfer error handling - in case of timeout report also number of remaining rx bytes - in case of timeout return ETIMEDOUT instead of EMSGSIZE - add sanity checks after all bytes have been sent / read: - check that HW has flag SPIE_DON set - check that RX / TX FIFO are empty Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:28:02 -06:00
if (!(events & SPIE_DON))
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
dev_err(espi->dev,
spi: fsl-espi: extend and improve transfer error handling Extend and improve transfer error handling - in case of timeout report also number of remaining rx bytes - in case of timeout return ETIMEDOUT instead of EMSGSIZE - add sanity checks after all bytes have been sent / read: - check that HW has flag SPIE_DON set - check that RX / TX FIFO are empty Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:28:02 -06:00
"Transfer done but SPIE_DON isn't set!\n");
spi: spi-fsl-espi: Log fifo counters on error Log RX and TX fifo counters when a transfer is done and these are not zero. Signed-off-by: Tiago Brusamarello <tiago.brusamarello@datacom.ind.br> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-07-26 08:12:11 -06:00
if (SPIE_RXCNT(events) || SPIE_TXCNT(events) != FSL_ESPI_FIFO_SIZE) {
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
dev_err(espi->dev, "Transfer done but rx/tx fifo's aren't empty!\n");
spi: spi-fsl-espi: Log fifo counters on error Log RX and TX fifo counters when a transfer is done and these are not zero. Signed-off-by: Tiago Brusamarello <tiago.brusamarello@datacom.ind.br> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-07-26 08:12:11 -06:00
dev_err(espi->dev, "SPIE_RXCNT = %d, SPIE_TXCNT = %d\n",
SPIE_RXCNT(events), SPIE_TXCNT(events));
}
spi: fsl-espi: extend and improve transfer error handling Extend and improve transfer error handling - in case of timeout report also number of remaining rx bytes - in case of timeout return ETIMEDOUT instead of EMSGSIZE - add sanity checks after all bytes have been sent / read: - check that HW has flag SPIE_DON set - check that RX / TX FIFO are empty Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:28:02 -06:00
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
complete(&espi->done);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
}
static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
{
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
struct fsl_espi *espi = context_data;
spi: fsl-espi: Only process interrupts for expected events [ Upstream commit b867eef4cf548cd9541225aadcdcee644669b9e1 ] The SPIE register contains counts for the TX FIFO so any time the irq handler was invoked we would attempt to process the RX/TX fifos. Use the SPIM value to mask the events so that we only process interrupts that were expected. This was a latent issue exposed by commit 3282a3da25bd ("powerpc/64: Implement soft interrupt replay in C"). Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Link: https://lore.kernel.org/r/20200904002812.7300-1-chris.packham@alliedtelesis.co.nz Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-09-03 18:28:12 -06:00
u32 events, mask;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
spin_lock(&espi->lock);
spi: fsl-espi: fix and improve writing to TX FIFO This change addresses two issues: - If the TX FIFO is full the ISR polls until there's free space again. An ISR should never wait for something. - Currently the number of bytes to transfer is rounded up to the next multiple of 4. For most transfers therefore few bytes remain in the TX FIFO after end of transfer. This would cause the next transfer to fail and as a workaround the ESPI block is disabled / re-enabled in fsl_espi_change_mode. This seems to clear the FIFO's (although it's not mentioned in the spec). With this change the TX FIFO is filled as much as possible initially and whenever the ISR is called. Also the exact number of bytes is transferred. The spinlock protects against a potential race if the first interrupt occurs whilst the TX FIFO is still being initially filled. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:25:58 -06:00
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
/* Get interrupt events(tx/rx) */
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
events = fsl_espi_read_reg(espi, ESPI_SPIE);
spi: fsl-espi: Only process interrupts for expected events [ Upstream commit b867eef4cf548cd9541225aadcdcee644669b9e1 ] The SPIE register contains counts for the TX FIFO so any time the irq handler was invoked we would attempt to process the RX/TX fifos. Use the SPIM value to mask the events so that we only process interrupts that were expected. This was a latent issue exposed by commit 3282a3da25bd ("powerpc/64: Implement soft interrupt replay in C"). Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Link: https://lore.kernel.org/r/20200904002812.7300-1-chris.packham@alliedtelesis.co.nz Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-09-03 18:28:12 -06:00
mask = fsl_espi_read_reg(espi, ESPI_SPIM);
if (!(events & mask)) {
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
spin_unlock(&espi->lock);
spi: fsl-espi: improve and simplify interrupt handler Simplify the interrupt handler a little. In addition don't call fsl_espi_cpu_irq() if no event bit is set. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-13 15:15:57 -06:00
return IRQ_NONE;
spi: fsl-espi: fix and improve writing to TX FIFO This change addresses two issues: - If the TX FIFO is full the ISR polls until there's free space again. An ISR should never wait for something. - Currently the number of bytes to transfer is rounded up to the next multiple of 4. For most transfers therefore few bytes remain in the TX FIFO after end of transfer. This would cause the next transfer to fail and as a workaround the ESPI block is disabled / re-enabled in fsl_espi_change_mode. This seems to clear the FIFO's (although it's not mentioned in the spec). With this change the TX FIFO is filled as much as possible initially and whenever the ISR is called. Also the exact number of bytes is transferred. The spinlock protects against a potential race if the first interrupt occurs whilst the TX FIFO is still being initially filled. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:25:58 -06:00
}
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
dev_vdbg(espi->dev, "%s: events %x\n", __func__, events);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
fsl_espi_cpu_irq(espi, events);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: improve and simplify interrupt handler Simplify the interrupt handler a little. In addition don't call fsl_espi_cpu_irq() if no event bit is set. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-13 15:15:57 -06:00
/* Clear the events */
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
fsl_espi_write_reg(espi, ESPI_SPIE, events);
spi: fsl-espi: improve and simplify interrupt handler Simplify the interrupt handler a little. In addition don't call fsl_espi_cpu_irq() if no event bit is set. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-13 15:15:57 -06:00
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
spin_unlock(&espi->lock);
spi: fsl-espi: fix and improve writing to TX FIFO This change addresses two issues: - If the TX FIFO is full the ISR polls until there's free space again. An ISR should never wait for something. - Currently the number of bytes to transfer is rounded up to the next multiple of 4. For most transfers therefore few bytes remain in the TX FIFO after end of transfer. This would cause the next transfer to fail and as a workaround the ESPI block is disabled / re-enabled in fsl_espi_change_mode. This seems to clear the FIFO's (although it's not mentioned in the spec). With this change the TX FIFO is filled as much as possible initially and whenever the ISR is called. Also the exact number of bytes is transferred. The spinlock protects against a potential race if the first interrupt occurs whilst the TX FIFO is still being initially filled. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-27 13:25:58 -06:00
spi: fsl-espi: improve and simplify interrupt handler Simplify the interrupt handler a little. In addition don't call fsl_espi_cpu_irq() if no event bit is set. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-13 15:15:57 -06:00
return IRQ_HANDLED;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
}
spi: fsl-espi: add runtime PM Add runtime PM and use autosuspend instead of suspending the SPI controller after each transfer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-26 13:21:55 -06:00
#ifdef CONFIG_PM
static int fsl_espi_runtime_suspend(struct device *dev)
spi: fsl-espi: add (un)prepare_transfer_hardware calls to save power if SPI is not in use Use (un)prepare_transfer_hardware calls to set fsl-espi to low-power idle if not in use. Reference manual states: "The eSPI is in a idle state and consumes minimal power. The eSPI BRG is not functioning and the input clock is disabled" Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-12-02 23:56:19 -07:00
{
spi: fsl-espi: add runtime PM Add runtime PM and use autosuspend instead of suspending the SPI controller after each transfer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-26 13:21:55 -06:00
struct spi_master *master = dev_get_drvdata(dev);
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
struct fsl_espi *espi = spi_master_get_devdata(master);
spi: fsl-espi: add (un)prepare_transfer_hardware calls to save power if SPI is not in use Use (un)prepare_transfer_hardware calls to set fsl-espi to low-power idle if not in use. Reference manual states: "The eSPI is in a idle state and consumes minimal power. The eSPI BRG is not functioning and the input clock is disabled" Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-12-02 23:56:19 -07:00
u32 regval;
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
regval = fsl_espi_read_reg(espi, ESPI_SPMODE);
spi: fsl-espi: add (un)prepare_transfer_hardware calls to save power if SPI is not in use Use (un)prepare_transfer_hardware calls to set fsl-espi to low-power idle if not in use. Reference manual states: "The eSPI is in a idle state and consumes minimal power. The eSPI BRG is not functioning and the input clock is disabled" Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-12-02 23:56:19 -07:00
regval &= ~SPMODE_ENABLE;
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
fsl_espi_write_reg(espi, ESPI_SPMODE, regval);
spi: fsl-espi: add (un)prepare_transfer_hardware calls to save power if SPI is not in use Use (un)prepare_transfer_hardware calls to set fsl-espi to low-power idle if not in use. Reference manual states: "The eSPI is in a idle state and consumes minimal power. The eSPI BRG is not functioning and the input clock is disabled" Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-12-02 23:56:19 -07:00
return 0;
}
spi: fsl-espi: add runtime PM Add runtime PM and use autosuspend instead of suspending the SPI controller after each transfer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-26 13:21:55 -06:00
static int fsl_espi_runtime_resume(struct device *dev)
spi: fsl-espi: add (un)prepare_transfer_hardware calls to save power if SPI is not in use Use (un)prepare_transfer_hardware calls to set fsl-espi to low-power idle if not in use. Reference manual states: "The eSPI is in a idle state and consumes minimal power. The eSPI BRG is not functioning and the input clock is disabled" Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-12-02 23:56:19 -07:00
{
spi: fsl-espi: add runtime PM Add runtime PM and use autosuspend instead of suspending the SPI controller after each transfer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-26 13:21:55 -06:00
struct spi_master *master = dev_get_drvdata(dev);
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
struct fsl_espi *espi = spi_master_get_devdata(master);
spi: fsl-espi: add (un)prepare_transfer_hardware calls to save power if SPI is not in use Use (un)prepare_transfer_hardware calls to set fsl-espi to low-power idle if not in use. Reference manual states: "The eSPI is in a idle state and consumes minimal power. The eSPI BRG is not functioning and the input clock is disabled" Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-12-02 23:56:19 -07:00
u32 regval;
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
regval = fsl_espi_read_reg(espi, ESPI_SPMODE);
spi: fsl-espi: add (un)prepare_transfer_hardware calls to save power if SPI is not in use Use (un)prepare_transfer_hardware calls to set fsl-espi to low-power idle if not in use. Reference manual states: "The eSPI is in a idle state and consumes minimal power. The eSPI BRG is not functioning and the input clock is disabled" Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-12-02 23:56:19 -07:00
regval |= SPMODE_ENABLE;
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
fsl_espi_write_reg(espi, ESPI_SPMODE, regval);
spi: fsl-espi: add (un)prepare_transfer_hardware calls to save power if SPI is not in use Use (un)prepare_transfer_hardware calls to set fsl-espi to low-power idle if not in use. Reference manual states: "The eSPI is in a idle state and consumes minimal power. The eSPI BRG is not functioning and the input clock is disabled" Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-12-02 23:56:19 -07:00
return 0;
}
spi: fsl-espi: add runtime PM Add runtime PM and use autosuspend instead of suspending the SPI controller after each transfer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-26 13:21:55 -06:00
#endif
spi: fsl-espi: add (un)prepare_transfer_hardware calls to save power if SPI is not in use Use (un)prepare_transfer_hardware calls to set fsl-espi to low-power idle if not in use. Reference manual states: "The eSPI is in a idle state and consumes minimal power. The eSPI BRG is not functioning and the input clock is disabled" Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-12-02 23:56:19 -07:00
spi: fsl-espi: eliminate spi nor flash read loop The fsl-espi driver contains a read loop that implicitely assumes that the device to read from is a m25p80 SPI NOR flash (bytes 2 - 4 of the first write transfer are interpreted as 3 byte flash address). Now that we have such a read loop in the spi-nor driver and are able to correctly indicate the message size limit of the controller, the read loop can be removed from the fsl-espi driver. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-08-17 13:11:01 -06:00
static size_t fsl_espi_max_message_size(struct spi_device *spi)
spi: fsl-espi: expose maximum transfer size limit The fsl-espi hardware can trasfer at most 64K data so report teh limitation. Based on patch by Heiner Kallweit <hkallweit1@gmail.com> CC: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Michal Suchanek <hramrach@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-12-02 03:38:21 -07:00
{
return SPCOM_TRANLEN_MAX;
}
spi: fsl-espi: factor out fsl_espi_init_regs The register initialization is the same in fsl_espi_probe and in of_fsl_espi_resume. Therefore factor it out into fsl_espi_init_regs. It was actually a bug that CSMODE_BEF and CSMODE_AFT were not set in of_fsl_espi_resume. Seems like nobody ever used values other than zero for these parameters. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:18 -07:00
static void fsl_espi_init_regs(struct device *dev, bool initial)
{
struct spi_master *master = dev_get_drvdata(dev);
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
struct fsl_espi *espi = spi_master_get_devdata(master);
spi: fsl-espi: factor out fsl_espi_init_regs The register initialization is the same in fsl_espi_probe and in of_fsl_espi_resume. Therefore factor it out into fsl_espi_init_regs. It was actually a bug that CSMODE_BEF and CSMODE_AFT were not set in of_fsl_espi_resume. Seems like nobody ever used values other than zero for these parameters. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:18 -07:00
struct device_node *nc;
u32 csmode, cs, prop;
int ret;
/* SPI controller initializations */
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
fsl_espi_write_reg(espi, ESPI_SPMODE, 0);
fsl_espi_write_reg(espi, ESPI_SPIM, 0);
fsl_espi_write_reg(espi, ESPI_SPCOM, 0);
fsl_espi_write_reg(espi, ESPI_SPIE, 0xffffffff);
spi: fsl-espi: factor out fsl_espi_init_regs The register initialization is the same in fsl_espi_probe and in of_fsl_espi_resume. Therefore factor it out into fsl_espi_init_regs. It was actually a bug that CSMODE_BEF and CSMODE_AFT were not set in of_fsl_espi_resume. Seems like nobody ever used values other than zero for these parameters. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:18 -07:00
/* Init eSPI CS mode register */
for_each_available_child_of_node(master->dev.of_node, nc) {
/* get chip select */
ret = of_property_read_u32(nc, "reg", &cs);
if (ret || cs >= master->num_chipselect)
continue;
csmode = CSMODE_INIT_VAL;
/* check if CSBEF is set in device tree */
ret = of_property_read_u32(nc, "fsl,csbef", &prop);
if (!ret) {
csmode &= ~(CSMODE_BEF(0xf));
csmode |= CSMODE_BEF(prop);
}
/* check if CSAFT is set in device tree */
ret = of_property_read_u32(nc, "fsl,csaft", &prop);
if (!ret) {
csmode &= ~(CSMODE_AFT(0xf));
csmode |= CSMODE_AFT(prop);
}
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
fsl_espi_write_reg(espi, ESPI_SPMODEx(cs), csmode);
spi: fsl-espi: factor out fsl_espi_init_regs The register initialization is the same in fsl_espi_probe and in of_fsl_espi_resume. Therefore factor it out into fsl_espi_init_regs. It was actually a bug that CSMODE_BEF and CSMODE_AFT were not set in of_fsl_espi_resume. Seems like nobody ever used values other than zero for these parameters. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:18 -07:00
if (initial)
dev_info(dev, "cs=%u, init_csmode=0x%x\n", cs, csmode);
}
/* Enable SPI interface */
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
fsl_espi_write_reg(espi, ESPI_SPMODE, SPMODE_INIT_VAL | SPMODE_ENABLE);
spi: fsl-espi: factor out fsl_espi_init_regs The register initialization is the same in fsl_espi_probe and in of_fsl_espi_resume. Therefore factor it out into fsl_espi_init_regs. It was actually a bug that CSMODE_BEF and CSMODE_AFT were not set in of_fsl_espi_resume. Seems like nobody ever used values other than zero for these parameters. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:18 -07:00
}
spi: fsl-espi: improve return value handling in fsl_espi_probe The return value of fsl_espi_probe (currently struct spi_master *) is just used for checking whether an error occurred. Change the return value type to int and simplify the code. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-17 07:43:31 -06:00
static int fsl_espi_probe(struct device *dev, struct resource *mem,
spi: fsl-espi: remove remaining usage of struct fsl_spi_platform_data Use master->num_chipselect directly instead of pdata->max_chipselect. In this context let of_fsl_espi_get_chipselects return max_chipselect. This change allows us to get rid of struct fsl_spi_platform_data completely in the fsl-espi driver. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:36:39 -07:00
unsigned int irq, unsigned int num_cs)
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
{
struct spi_master *master;
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
struct fsl_espi *espi;
spi: fsl-espi: replace of_get_property with of_property_read_u32 of_property_read_u32 is better here than generic of_get_property: - implicit endianness conversion if needed - implicit checking of size of property Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-01 13:07:52 -06:00
int ret;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
master = spi_alloc_master(dev, sizeof(struct fsl_espi));
spi: fsl-espi: improve return value handling in fsl_espi_probe The return value of fsl_espi_probe (currently struct spi_master *) is just used for checking whether an error occurred. Change the return value type to int and simplify the code. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-17 07:43:31 -06:00
if (!master)
return -ENOMEM;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
dev_set_drvdata(dev, master);
spi: fsl-espi: migrate relevant parts of mpc8xxx_spi_probe and of_mpc8xxx_spi_probe Very little of the library functions mpc8xxx_spi_probe and of_mpc8xxx_spi_probe is relevant for fsl-espi. Therefore migrate the relevant parts to fsl-espi (considering that get_brgfreq() always returns -1 on systems with ESPI) and remove use of these functions. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:37:41 -07:00
master->mode_bits = SPI_RX_DUAL | SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
SPI_LSB_FIRST | SPI_LOOP;
master->dev.of_node = dev->of_node;
spi: convert drivers to use bits_per_word_mask Fill in the recently added spi_master.bits_per_word_mask field in as many drivers as possible. Make related cleanups, such as removing any redundant error-checking, or empty setup callbacks. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2013-05-21 20:36:35 -06:00
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
master->setup = fsl_espi_setup;
spi: fsl: Don't use devm_kzalloc in master->setup callback device_add() expects that any memory allocated via devm_* API is only done in the device's probe function. Fix below boot warning: [ 3.092348] WARNING: at drivers/base/dd.c:286 [ 3.096637] Modules linked in: [ 3.099697] CPU: 0 PID: 25 Comm: kworker/u2:1 Tainted: G W 3.16.1-s3k-drv-999-svn5771_knld-999 #158 [ 3.109610] Workqueue: deferwq deferred_probe_work_func [ 3.114736] task: c787f020 ti: c790c000 task.ti: c790c000 [ 3.120062] NIP: c01df158 LR: c01df144 CTR: 00000000 [ 3.124983] REGS: c790db30 TRAP: 0700 Tainted: G W (3.16.1-s3k-drv-999-svn5771_knld-999) [ 3.134162] MSR: 00029032 <EE,ME,IR,DR,RI> CR: 22002082 XER: 20000000 [ 3.140703] [ 3.140703] GPR00: 00000001 c790dbe0 c787f020 00000044 00000054 00000308 c056da0e 20737069 [ 3.140703] GPR08: 33323736 000ebfe0 00000308 000ebfdf 22002082 00000000 c046c5a0 c046c608 [ 3.140703] GPR16: c046c614 c046c620 c046c62c c046c638 c046c648 c046c654 c046c68c c046c6c4 [ 3.140703] GPR24: 00000000 00000000 00000003 c0401aa0 c0596638 c059662c c054e7a8 c7996800 [ 3.170102] NIP [c01df158] driver_probe_device+0xf8/0x334 [ 3.175431] LR [c01df144] driver_probe_device+0xe4/0x334 [ 3.180633] Call Trace: [ 3.183093] [c790dbe0] [c01df144] driver_probe_device+0xe4/0x334 (unreliable) [ 3.190147] [c790dc10] [c01dd15c] bus_for_each_drv+0x7c/0xc0 [ 3.195741] [c790dc40] [c01df5fc] device_attach+0xcc/0xf8 [ 3.201076] [c790dc60] [c01dd6d4] bus_probe_device+0xb4/0xc4 [ 3.206666] [c790dc80] [c01db9f8] device_add+0x270/0x564 [ 3.211923] [c790dcc0] [c0219e84] spi_add_device+0xc0/0x190 [ 3.217427] [c790dce0] [c021a79c] spi_register_master+0x720/0x834 [ 3.223455] [c790dd40] [c021cb48] of_fsl_spi_probe+0x55c/0x614 [ 3.229234] [c790dda0] [c01e0d2c] platform_drv_probe+0x30/0x74 [ 3.234987] [c790ddb0] [c01df18c] driver_probe_device+0x12c/0x334 [ 3.241008] [c790dde0] [c01dd15c] bus_for_each_drv+0x7c/0xc0 [ 3.246602] [c790de10] [c01df5fc] device_attach+0xcc/0xf8 [ 3.251937] [c790de30] [c01dd6d4] bus_probe_device+0xb4/0xc4 [ 3.257536] [c790de50] [c01de9d8] deferred_probe_work_func+0x98/0xe0 [ 3.263816] [c790de70] [c00305b8] process_one_work+0x18c/0x440 [ 3.269577] [c790dea0] [c0030a00] worker_thread+0x194/0x67c [ 3.275105] [c790def0] [c0039198] kthread+0xd0/0xe4 [ 3.279911] [c790df40] [c000c6d0] ret_from_kernel_thread+0x5c/0x64 [ 3.285970] Instruction dump: [ 3.288900] 80de0000 419e01d0 3b7b0038 3c60c046 7f65db78 38635264 48211b99 813f00a0 [ 3.296559] 381f00a0 7d290278 3169ffff 7c0b4910 <0f000000> 93df0044 7fe3fb78 4bfffd4d Reported-by: leroy christophe <christophe.leroy@c-s.fr> Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
2014-08-30 22:44:09 -06:00
master->cleanup = fsl_espi_cleanup;
spi: fsl-(e)spi: migrate to generic master queueing Migrates the fsl-(e)spi driver to use the generic master queuing. Avoids the "master is unqueued, this is deprecated" warning. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-12-02 23:56:17 -07:00
master->transfer_one_message = fsl_espi_do_one_msg;
spi: fsl-espi: add runtime PM Add runtime PM and use autosuspend instead of suspending the SPI controller after each transfer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-26 13:21:55 -06:00
master->auto_runtime_pm = true;
spi: fsl-espi: eliminate spi nor flash read loop The fsl-espi driver contains a read loop that implicitely assumes that the device to read from is a m25p80 SPI NOR flash (bytes 2 - 4 of the first write transfer are interpreted as 3 byte flash address). Now that we have such a read loop in the spi-nor driver and are able to correctly indicate the message size limit of the controller, the read loop can be removed from the fsl-espi driver. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-08-17 13:11:01 -06:00
master->max_message_size = fsl_espi_max_message_size;
spi: fsl-espi: remove remaining usage of struct fsl_spi_platform_data Use master->num_chipselect directly instead of pdata->max_chipselect. In this context let of_fsl_espi_get_chipselects return max_chipselect. This change allows us to get rid of struct fsl_spi_platform_data completely in the fsl-espi driver. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:36:39 -07:00
master->num_chipselect = num_cs;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
espi = spi_master_get_devdata(master);
spin_lock_init(&espi->lock);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
espi->dev = dev;
espi->spibrg = fsl_get_sys_freq();
if (espi->spibrg == -1) {
spi: fsl-espi: migrate relevant parts of mpc8xxx_spi_probe and of_mpc8xxx_spi_probe Very little of the library functions mpc8xxx_spi_probe and of_mpc8xxx_spi_probe is relevant for fsl-espi. Therefore migrate the relevant parts to fsl-espi (considering that get_brgfreq() always returns -1 on systems with ESPI) and remove use of these functions. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:37:41 -07:00
dev_err(dev, "Can't get sys frequency!\n");
ret = -EINVAL;
goto err_probe;
}
spi: fsl-espi: set spi_master members min_speed_hz and max_speed_hz ESPI has a max and min supported SPI frequency, determined by the clock divider range. Set master->min_speed_hz/max_speed_hz to inform the SPI core about these limits. Then the SPI core handles cases where a transfer requests a frequency outside the supported range. So far the driver simply set the lowest supported frequency if the requested frequency was below the supported range. This is not necessarily an appropriate action as the device might not support frequencies greater than the requested one. With this patch the SPI core will reject transfers requesting a too low frequency. The check in fsl_espi_setup can be removed because the SPI core sets spi->max_speed_hz to master->max_speed_hz if it's not set already. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-15 13:56:33 -07:00
/* determined by clock divider fields DIV16/PM in register SPMODEx */
master->min_speed_hz = DIV_ROUND_UP(espi->spibrg, 4 * 16 * 16);
master->max_speed_hz = DIV_ROUND_UP(espi->spibrg, 4);
spi: fsl-espi: migrate relevant parts of mpc8xxx_spi_probe and of_mpc8xxx_spi_probe Very little of the library functions mpc8xxx_spi_probe and of_mpc8xxx_spi_probe is relevant for fsl-espi. Therefore migrate the relevant parts to fsl-espi (considering that get_brgfreq() always returns -1 on systems with ESPI) and remove use of these functions. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:37:41 -07:00
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
init_completion(&espi->done);
spi: fsl-espi: migrate relevant parts of mpc8xxx_spi_probe and of_mpc8xxx_spi_probe Very little of the library functions mpc8xxx_spi_probe and of_mpc8xxx_spi_probe is relevant for fsl-espi. Therefore migrate the relevant parts to fsl-espi (considering that get_brgfreq() always returns -1 on systems with ESPI) and remove use of these functions. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:37:41 -07:00
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
espi->reg_base = devm_ioremap_resource(dev, mem);
if (IS_ERR(espi->reg_base)) {
ret = PTR_ERR(espi->reg_base);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
goto err_probe;
}
/* Register for SPI Interrupt */
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
ret = devm_request_irq(dev, irq, fsl_espi_irq, 0, "fsl_espi", espi);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
if (ret)
spi: fsl-(e)spi: migrate to using devm_ functions to simplify cleanup Migrate fsl-espi and fsl-spi to using the managed devm_ functions for resource handling. This simplifies the cleanup. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-26 13:21:50 -06:00
goto err_probe;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: factor out fsl_espi_init_regs The register initialization is the same in fsl_espi_probe and in of_fsl_espi_resume. Therefore factor it out into fsl_espi_init_regs. It was actually a bug that CSMODE_BEF and CSMODE_AFT were not set in of_fsl_espi_resume. Seems like nobody ever used values other than zero for these parameters. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:18 -07:00
fsl_espi_init_regs(dev, true);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: add runtime PM Add runtime PM and use autosuspend instead of suspending the SPI controller after each transfer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-26 13:21:55 -06:00
pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT);
pm_runtime_use_autosuspend(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
spi: fsl-(e)spi: migrate to using devm_ functions to simplify cleanup Migrate fsl-espi and fsl-spi to using the managed devm_ functions for resource handling. This simplifies the cleanup. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-26 13:21:50 -06:00
ret = devm_spi_register_master(dev, master);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
if (ret < 0)
spi: fsl-espi: add runtime PM Add runtime PM and use autosuspend instead of suspending the SPI controller after each transfer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-26 13:21:55 -06:00
goto err_pm;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: introduce struct fsl_espi Only few members of struct mpc8xxx_spi are relevant for fsl-espi. Therefore replace it with a ESPI-specific struct fsl_espi. Replace variable names mpc8xxx_spi and mspi with espi. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:51 -07:00
dev_info(dev, "at 0x%p (irq = %u)\n", espi->reg_base, irq);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: add runtime PM Add runtime PM and use autosuspend instead of suspending the SPI controller after each transfer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-26 13:21:55 -06:00
pm_runtime_mark_last_busy(dev);
pm_runtime_put_autosuspend(dev);
spi: fsl-espi: improve return value handling in fsl_espi_probe The return value of fsl_espi_probe (currently struct spi_master *) is just used for checking whether an error occurred. Change the return value type to int and simplify the code. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-17 07:43:31 -06:00
return 0;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: add runtime PM Add runtime PM and use autosuspend instead of suspending the SPI controller after each transfer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-26 13:21:55 -06:00
err_pm:
pm_runtime_put_noidle(dev);
pm_runtime_disable(dev);
pm_runtime_set_suspended(dev);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
err_probe:
spi_master_put(master);
spi: fsl-espi: improve return value handling in fsl_espi_probe The return value of fsl_espi_probe (currently struct spi_master *) is just used for checking whether an error occurred. Change the return value type to int and simplify the code. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-17 07:43:31 -06:00
return ret;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
}
static int of_fsl_espi_get_chipselects(struct device *dev)
{
struct device_node *np = dev->of_node;
spi: fsl-espi: replace of_get_property with of_property_read_u32 of_property_read_u32 is better here than generic of_get_property: - implicit endianness conversion if needed - implicit checking of size of property Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-01 13:07:52 -06:00
u32 num_cs;
int ret;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: replace of_get_property with of_property_read_u32 of_property_read_u32 is better here than generic of_get_property: - implicit endianness conversion if needed - implicit checking of size of property Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-10-01 13:07:52 -06:00
ret = of_property_read_u32(np, "fsl,espi-num-chipselects", &num_cs);
if (ret) {
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
spi: fsl-espi: remove remaining usage of struct fsl_spi_platform_data Use master->num_chipselect directly instead of pdata->max_chipselect. In this context let of_fsl_espi_get_chipselects return max_chipselect. This change allows us to get rid of struct fsl_spi_platform_data completely in the fsl-espi driver. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:36:39 -07:00
return 0;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
}
spi: fsl-espi: remove remaining usage of struct fsl_spi_platform_data Use master->num_chipselect directly instead of pdata->max_chipselect. In this context let of_fsl_espi_get_chipselects return max_chipselect. This change allows us to get rid of struct fsl_spi_platform_data completely in the fsl-espi driver. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:36:39 -07:00
return num_cs;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
}
spi: Remove HOTPLUG section attributes CONFIG_HOTPLUG is going away as an option. As result the __dev* markings will be going away. Remove use of __devinit, __devexit_p, __devinitdata, __devinitconst, and __devexit. Bill Pemberton has done most of the legwork on this series. I've used his script to purge the attributes from the drivers/gpio tree. Reported-by: Bill Pemberton <wfp5p@virginia.edu> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2012-12-07 09:57:14 -07:00
static int of_fsl_espi_probe(struct platform_device *ofdev)
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
{
struct device *dev = &ofdev->dev;
struct device_node *np = ofdev->dev.of_node;
struct resource mem;
spi: fsl-espi: remove remaining usage of struct fsl_spi_platform_data Use master->num_chipselect directly instead of pdata->max_chipselect. In this context let of_fsl_espi_get_chipselects return max_chipselect. This change allows us to get rid of struct fsl_spi_platform_data completely in the fsl-espi driver. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:36:39 -07:00
unsigned int irq, num_cs;
spi: fsl-espi: simplify of_fsl_espi_probe Simplify of_fsl_espi_probe. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-17 07:43:00 -06:00
int ret;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: remove usage of mpc8xxx_spi->flags Change the check to access property "mode" directly. This allows us to get rid of mpc8xxx_spi->flags in a subsequent patch in this patch series as it's used nowhere else. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:37:18 -07:00
if (of_property_read_bool(np, "mode")) {
dev_err(dev, "mode property is not supported on ESPI!\n");
return -EINVAL;
}
spi: fsl-espi: remove remaining usage of struct fsl_spi_platform_data Use master->num_chipselect directly instead of pdata->max_chipselect. In this context let of_fsl_espi_get_chipselects return max_chipselect. This change allows us to get rid of struct fsl_spi_platform_data completely in the fsl-espi driver. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:36:39 -07:00
num_cs = of_fsl_espi_get_chipselects(dev);
if (!num_cs)
return -EINVAL;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
ret = of_address_to_resource(np, 0, &mem);
if (ret)
spi: fsl-espi: simplify of_fsl_espi_probe Simplify of_fsl_espi_probe. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-17 07:43:00 -06:00
return ret;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
of/irq: Use irq_of_parse_and_map() Replace some instances of of_irq_map_one()/irq_create_of_mapping() and of_irq_to_resource() by the simpler equivalent irq_of_parse_and_map(). Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Rob Herring <rob.herring@calxeda.com> [grant.likely: resolved conflicts with core code renames] Signed-off-by: Grant Likely <grant.likely@linaro.org>
2013-09-18 07:24:44 -06:00
irq = irq_of_parse_and_map(np, 0);
spi: fsl-espi: simplify of_fsl_espi_probe Simplify of_fsl_espi_probe. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-17 07:43:00 -06:00
if (!irq)
return -EINVAL;
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
spi: fsl-espi: remove remaining usage of struct fsl_spi_platform_data Use master->num_chipselect directly instead of pdata->max_chipselect. In this context let of_fsl_espi_get_chipselects return max_chipselect. This change allows us to get rid of struct fsl_spi_platform_data completely in the fsl-espi driver. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:36:39 -07:00
return fsl_espi_probe(dev, &mem, irq, num_cs);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
}
spi: fsl-espi: add runtime PM Add runtime PM and use autosuspend instead of suspending the SPI controller after each transfer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-26 13:21:55 -06:00
static int of_fsl_espi_remove(struct platform_device *dev)
{
pm_runtime_disable(&dev->dev);
return 0;
}
spi/fsl-espi: Add Power Management support for eSPI controller Add PM support for eSPI controller using callback function suspend and resume in .driver.pm of platform_driver. Signed-off-by: Hou Zhiqiang <b48286@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2013-12-11 21:53:52 -07:00
#ifdef CONFIG_PM_SLEEP
static int of_fsl_espi_suspend(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
int ret;
ret = spi_master_suspend(master);
spi: Do not print a message if spi_controller_{suspend,resume}() fails spi_controller_{suspend,resume}() already prints an error message on failure, so there is no need to repeat this in individual drivers. Note: spi_master_{suspend,resume}() is an alias for spi_controller_{suspend,resume}(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Daniel Mack <daniel@zonque.org> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-09-05 02:51:57 -06:00
if (ret)
spi/fsl-espi: Add Power Management support for eSPI controller Add PM support for eSPI controller using callback function suspend and resume in .driver.pm of platform_driver. Signed-off-by: Hou Zhiqiang <b48286@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2013-12-11 21:53:52 -07:00
return ret;
spi: fsl-espi: simplify of_fsl_espi_suspend Simplify of_fsl_espi_suspend a little. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-15 13:37:17 -07:00
return pm_runtime_force_suspend(dev);
spi/fsl-espi: Add Power Management support for eSPI controller Add PM support for eSPI controller using callback function suspend and resume in .driver.pm of platform_driver. Signed-off-by: Hou Zhiqiang <b48286@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2013-12-11 21:53:52 -07:00
}
static int of_fsl_espi_resume(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
spi: fsl-espi: factor out fsl_espi_init_regs The register initialization is the same in fsl_espi_probe and in of_fsl_espi_resume. Therefore factor it out into fsl_espi_init_regs. It was actually a bug that CSMODE_BEF and CSMODE_AFT were not set in of_fsl_espi_resume. Seems like nobody ever used values other than zero for these parameters. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:18 -07:00
int ret;
spi/fsl-espi: Add Power Management support for eSPI controller Add PM support for eSPI controller using callback function suspend and resume in .driver.pm of platform_driver. Signed-off-by: Hou Zhiqiang <b48286@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2013-12-11 21:53:52 -07:00
spi: fsl-espi: factor out fsl_espi_init_regs The register initialization is the same in fsl_espi_probe and in of_fsl_espi_resume. Therefore factor it out into fsl_espi_init_regs. It was actually a bug that CSMODE_BEF and CSMODE_AFT were not set in of_fsl_espi_resume. Seems like nobody ever used values other than zero for these parameters. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-13 06:40:18 -07:00
fsl_espi_init_regs(dev, false);
spi/fsl-espi: Add Power Management support for eSPI controller Add PM support for eSPI controller using callback function suspend and resume in .driver.pm of platform_driver. Signed-off-by: Hou Zhiqiang <b48286@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2013-12-11 21:53:52 -07:00
spi: fsl-espi: add runtime PM Add runtime PM and use autosuspend instead of suspending the SPI controller after each transfer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-26 13:21:55 -06:00
ret = pm_runtime_force_resume(dev);
if (ret < 0)
return ret;
spi/fsl-espi: Add Power Management support for eSPI controller Add PM support for eSPI controller using callback function suspend and resume in .driver.pm of platform_driver. Signed-off-by: Hou Zhiqiang <b48286@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2013-12-11 21:53:52 -07:00
return spi_master_resume(master);
}
#endif /* CONFIG_PM_SLEEP */
static const struct dev_pm_ops espi_pm = {
spi: fsl-espi: add runtime PM Add runtime PM and use autosuspend instead of suspending the SPI controller after each transfer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-26 13:21:55 -06:00
SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend,
fsl_espi_runtime_resume, NULL)
spi/fsl-espi: Add Power Management support for eSPI controller Add PM support for eSPI controller using callback function suspend and resume in .driver.pm of platform_driver. Signed-off-by: Hou Zhiqiang <b48286@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2013-12-11 21:53:52 -07:00
SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
};
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
static const struct of_device_id of_fsl_espi_match[] = {
{ .compatible = "fsl,mpc8536-espi" },
{}
};
MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
dt/spi: Eliminate users of of_platform_{,un}register_driver Get rid of users of of_platform_driver in drivers/spi. The of_platform_{,un}register_driver functions are going away, so the users need to be converted to using the platform_bus_type directly. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-02-22 21:02:43 -07:00
static struct platform_driver fsl_espi_driver = {
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
.driver = {
.name = "fsl_espi",
.of_match_table = of_fsl_espi_match,
spi/fsl-espi: Add Power Management support for eSPI controller Add PM support for eSPI controller using callback function suspend and resume in .driver.pm of platform_driver. Signed-off-by: Hou Zhiqiang <b48286@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2013-12-11 21:53:52 -07:00
.pm = &espi_pm,
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
},
.probe = of_fsl_espi_probe,
spi: fsl-espi: add runtime PM Add runtime PM and use autosuspend instead of suspending the SPI controller after each transfer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-26 13:21:55 -06:00
.remove = of_fsl_espi_remove,
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
};
drivercore: Add helper macro for platform_driver boilerplate For simple modules that contain a single platform_driver without any additional setup code then ends up being a block of duplicated boilerplate. This patch adds a new macro, module_platform_driver(), which replaces the module_init()/module_exit() registrations with template functions. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Reviewed-by: Magnus Damm <magnus.damm@gmail.com> Reviewed-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
2011-10-05 11:29:49 -06:00
module_platform_driver(fsl_espi_driver);
spi/fsl_spi: add eSPI controller support Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 04:18:32 -06:00
MODULE_AUTHOR("Mingkai Hu");
MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
MODULE_LICENSE("GPL");