2009-06-05 06:42:42 -06:00
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/*
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* Copyright 2009 Jerome Glisse.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors:
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* Jerome Glisse <glisse@freedesktop.org>
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* Dave Airlie
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*/
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#include <linux/seq_file.h>
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2011-07-26 17:09:06 -06:00
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#include <linux/atomic.h>
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2009-06-05 06:42:42 -06:00
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#include <linux/wait.h>
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#include <linux/kref.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2013-04-08 04:41:29 -06:00
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#include <linux/firmware.h>
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2012-10-02 11:01:07 -06:00
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#include <drm/drmP.h>
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2009-06-05 06:42:42 -06:00
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#include "radeon_reg.h"
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#include "radeon.h"
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2010-11-22 18:47:49 -07:00
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#include "radeon_trace.h"
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2009-06-05 06:42:42 -06:00
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2012-07-17 12:02:37 -06:00
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/*
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* Fences
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* Fences mark an event in the GPUs pipeline and are used
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* for GPU/CPU synchronization. When the fence is written,
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* it is expected that all buffers associated with that fence
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* are no longer in use by the associated ring on the GPU and
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* that the the relevant GPU caches have been flushed. Whether
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* we use a scratch register or memory location depends on the asic
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* and whether writeback is enabled.
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*/
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/**
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* radeon_fence_write - write a fence value
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*
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* @rdev: radeon_device pointer
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* @seq: sequence number to write
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* @ring: ring index the fence is associated with
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*
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* Writes a fence value to memory or a scratch register (all asics).
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*/
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2011-08-25 11:39:48 -06:00
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static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
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2011-06-13 15:39:06 -06:00
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{
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2012-07-09 02:52:39 -06:00
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struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
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if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
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2013-06-06 15:51:21 -06:00
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if (drv->cpu_addr) {
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*drv->cpu_addr = cpu_to_le32(seq);
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}
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2011-11-20 13:45:34 -07:00
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} else {
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2012-07-09 02:52:39 -06:00
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WREG32(drv->scratch_reg, seq);
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2011-11-20 13:45:34 -07:00
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}
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2011-06-13 15:39:06 -06:00
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}
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2012-07-17 12:02:37 -06:00
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/**
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* radeon_fence_read - read a fence value
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*
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* @rdev: radeon_device pointer
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* @ring: ring index the fence is associated with
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*
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* Reads a fence value from memory or a scratch register (all asics).
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* Returns the value of the fence read from memory or register.
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*/
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2011-08-25 11:39:48 -06:00
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static u32 radeon_fence_read(struct radeon_device *rdev, int ring)
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2011-06-13 15:39:06 -06:00
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{
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2012-07-09 02:52:39 -06:00
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struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
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2011-08-25 11:39:48 -06:00
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u32 seq = 0;
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2011-06-13 15:39:06 -06:00
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2012-07-09 02:52:39 -06:00
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if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
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2013-06-06 15:51:21 -06:00
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if (drv->cpu_addr) {
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seq = le32_to_cpu(*drv->cpu_addr);
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} else {
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seq = lower_32_bits(atomic64_read(&drv->last_seq));
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}
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2011-11-20 13:45:34 -07:00
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} else {
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2012-07-09 02:52:39 -06:00
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seq = RREG32(drv->scratch_reg);
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2011-11-20 13:45:34 -07:00
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}
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2011-06-13 15:39:06 -06:00
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return seq;
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}
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2012-07-17 12:02:37 -06:00
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/**
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* radeon_fence_emit - emit a fence on the requested ring
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*
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* @rdev: radeon_device pointer
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* @fence: radeon fence object
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* @ring: ring index the fence is associated with
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*
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* Emits a fence command on the requested ring (all asics).
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* Returns 0 on success, -ENOMEM on failure.
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*/
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2012-05-08 06:24:01 -06:00
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int radeon_fence_emit(struct radeon_device *rdev,
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struct radeon_fence **fence,
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int ring)
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2009-06-05 06:42:42 -06:00
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{
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2012-05-09 07:34:47 -06:00
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/* we are protected by the ring emission mutex */
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2012-05-08 06:24:01 -06:00
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*fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
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if ((*fence) == NULL) {
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return -ENOMEM;
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2009-06-05 06:42:42 -06:00
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}
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2012-05-08 06:24:01 -06:00
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kref_init(&((*fence)->kref));
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(*fence)->rdev = rdev;
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2012-05-10 07:57:31 -06:00
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(*fence)->seq = ++rdev->fence_drv[ring].sync_seq[ring];
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2012-05-08 06:24:01 -06:00
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(*fence)->ring = ring;
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radeon_fence_ring_emit(rdev, ring, *fence);
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trace_radeon_fence_emit(rdev->ddev, (*fence)->seq);
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2009-06-05 06:42:42 -06:00
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return 0;
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}
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2012-07-17 12:02:37 -06:00
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/**
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* radeon_fence_process - process a fence
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*
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* @rdev: radeon_device pointer
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* @ring: ring index the fence is associated with
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*
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* Checks the current fence value and wakes the fence queue
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* if the sequence number has increased (all asics).
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*/
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2012-05-09 07:34:47 -06:00
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void radeon_fence_process(struct radeon_device *rdev, int ring)
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2009-06-05 06:42:42 -06:00
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{
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2012-09-13 02:33:47 -06:00
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uint64_t seq, last_seq, last_emitted;
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2012-05-09 07:34:46 -06:00
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unsigned count_loop = 0;
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2009-06-05 06:42:42 -06:00
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bool wake = false;
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2012-05-09 07:34:46 -06:00
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/* Note there is a scenario here for an infinite loop but it's
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* very unlikely to happen. For it to happen, the current polling
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* process need to be interrupted by another process and another
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* process needs to update the last_seq btw the atomic read and
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* xchg of the current process.
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*
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* More over for this to go in infinite loop there need to be
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* continuously new fence signaled ie radeon_fence_read needs
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* to return a different value each time for both the currently
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* polling process and the other process that xchg the last_seq
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* btw atomic read and xchg of the current process. And the
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* value the other process set as last seq must be higher than
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* the seq value we just read. Which means that current process
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* need to be interrupted after radeon_fence_read and before
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* atomic xchg.
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*
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* To be even more safe we count the number of time we loop and
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* we bail after 10 loop just accepting the fact that we might
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* have temporarly set the last_seq not to the true real last
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* seq but to an older one.
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*/
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last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
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do {
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2012-09-13 02:33:47 -06:00
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last_emitted = rdev->fence_drv[ring].sync_seq[ring];
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2012-05-09 07:34:46 -06:00
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seq = radeon_fence_read(rdev, ring);
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seq |= last_seq & 0xffffffff00000000LL;
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if (seq < last_seq) {
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2012-09-13 02:33:47 -06:00
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seq &= 0xffffffff;
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seq |= last_emitted & 0xffffffff00000000LL;
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2012-05-09 07:34:46 -06:00
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}
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2012-05-02 07:11:13 -06:00
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2012-09-13 02:33:47 -06:00
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if (seq <= last_seq || seq > last_emitted) {
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2012-05-09 07:34:47 -06:00
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break;
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2012-05-09 07:34:46 -06:00
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}
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/* If we loop over we don't want to return without
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* checking if a fence is signaled as it means that the
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* seq we just read is different from the previous on.
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*/
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wake = true;
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2012-05-09 07:34:47 -06:00
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last_seq = seq;
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2012-05-09 07:34:46 -06:00
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if ((count_loop++) > 10) {
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/* We looped over too many time leave with the
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* fact that we might have set an older fence
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* seq then the current real last seq as signaled
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* by the hw.
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*/
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break;
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}
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} while (atomic64_xchg(&rdev->fence_drv[ring].last_seq, seq) > seq);
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2012-05-09 07:34:47 -06:00
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if (wake) {
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rdev->fence_drv[ring].last_activity = jiffies;
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2012-05-09 07:34:55 -06:00
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wake_up_all(&rdev->fence_queue);
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2009-06-05 06:42:42 -06:00
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}
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}
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2012-07-17 12:02:37 -06:00
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/**
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* radeon_fence_destroy - destroy a fence
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*
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* @kref: fence kref
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*
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* Frees the fence object (all asics).
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*/
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2009-06-05 06:42:42 -06:00
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static void radeon_fence_destroy(struct kref *kref)
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{
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2012-05-09 07:34:47 -06:00
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struct radeon_fence *fence;
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2009-06-05 06:42:42 -06:00
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fence = container_of(kref, struct radeon_fence, kref);
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kfree(fence);
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}
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2012-07-17 12:02:37 -06:00
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/**
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* radeon_fence_seq_signaled - check if a fence sequeuce number has signaled
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*
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* @rdev: radeon device pointer
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* @seq: sequence number
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* @ring: ring index the fence is associated with
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*
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* Check if the last singled fence sequnce number is >= the requested
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* sequence number (all asics).
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* Returns true if the fence has signaled (current fence value
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* is >= requested value) or false if it has not (current fence
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* value is < the requested value. Helper function for
|
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* radeon_fence_signaled().
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*/
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2012-05-09 07:34:47 -06:00
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static bool radeon_fence_seq_signaled(struct radeon_device *rdev,
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u64 seq, unsigned ring)
|
2009-06-05 06:42:42 -06:00
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{
|
2012-05-09 07:34:47 -06:00
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if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
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return true;
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}
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|
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/* poll new last sequence at least once */
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radeon_fence_process(rdev, ring);
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if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
|
2009-06-05 06:42:42 -06:00
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return true;
|
2012-05-09 07:34:47 -06:00
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}
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return false;
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}
|
2009-12-29 18:20:05 -07:00
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|
2012-07-17 12:02:37 -06:00
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/**
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* radeon_fence_signaled - check if a fence has signaled
|
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*
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* @fence: radeon fence object
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*
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* Check if the requested fence has signaled (all asics).
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* Returns true if the fence has signaled or false if it has not.
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*/
|
2012-05-09 07:34:47 -06:00
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|
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bool radeon_fence_signaled(struct radeon_fence *fence)
|
|
|
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{
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|
if (!fence) {
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return true;
|
2009-06-05 06:42:42 -06:00
|
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|
}
|
2012-05-09 07:34:47 -06:00
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|
|
if (fence->seq == RADEON_FENCE_SIGNALED_SEQ) {
|
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|
return true;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
2012-05-09 07:34:47 -06:00
|
|
|
if (radeon_fence_seq_signaled(fence->rdev, fence->seq, fence->ring)) {
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|
fence->seq = RADEON_FENCE_SIGNALED_SEQ;
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|
return true;
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|
}
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|
|
|
return false;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:37 -06:00
|
|
|
/**
|
|
|
|
* radeon_fence_wait_seq - wait for a specific sequence number
|
|
|
|
*
|
|
|
|
* @rdev: radeon device pointer
|
|
|
|
* @target_seq: sequence number we want to wait for
|
|
|
|
* @ring: ring index the fence is associated with
|
|
|
|
* @intr: use interruptable sleep
|
|
|
|
* @lock_ring: whether the ring should be locked or not
|
|
|
|
*
|
|
|
|
* Wait for the requested sequence number to be written (all asics).
|
|
|
|
* @intr selects whether to use interruptable (true) or non-interruptable
|
|
|
|
* (false) sleep when waiting for the sequence number. Helper function
|
|
|
|
* for radeon_fence_wait(), et al.
|
|
|
|
* Returns 0 if the sequence number has passed, error for all other cases.
|
|
|
|
* -EDEADLK is returned when a GPU lockup has been detected and the ring is
|
|
|
|
* marked as not ready so no further jobs get scheduled until a successful
|
|
|
|
* reset.
|
|
|
|
*/
|
2012-05-09 07:34:47 -06:00
|
|
|
static int radeon_fence_wait_seq(struct radeon_device *rdev, u64 target_seq,
|
2012-05-09 07:34:48 -06:00
|
|
|
unsigned ring, bool intr, bool lock_ring)
|
2009-06-05 06:42:42 -06:00
|
|
|
{
|
2012-05-09 07:34:47 -06:00
|
|
|
unsigned long timeout, last_activity;
|
2012-05-09 07:34:46 -06:00
|
|
|
uint64_t seq;
|
2012-05-09 07:34:47 -06:00
|
|
|
unsigned i;
|
2012-05-02 07:11:13 -06:00
|
|
|
bool signaled;
|
2012-05-09 07:34:47 -06:00
|
|
|
int r;
|
2009-06-05 06:42:42 -06:00
|
|
|
|
2012-05-09 07:34:47 -06:00
|
|
|
while (target_seq > atomic64_read(&rdev->fence_drv[ring].last_seq)) {
|
|
|
|
if (!rdev->ring[ring].ready) {
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
2012-05-02 07:11:13 -06:00
|
|
|
|
|
|
|
timeout = jiffies - RADEON_FENCE_JIFFIES_TIMEOUT;
|
2012-05-09 07:34:47 -06:00
|
|
|
if (time_after(rdev->fence_drv[ring].last_activity, timeout)) {
|
2012-05-02 07:11:13 -06:00
|
|
|
/* the normal case, timeout is somewhere before last_activity */
|
2012-05-09 07:34:47 -06:00
|
|
|
timeout = rdev->fence_drv[ring].last_activity - timeout;
|
2012-05-02 07:11:13 -06:00
|
|
|
} else {
|
|
|
|
/* either jiffies wrapped around, or no fence was signaled in the last 500ms
|
2012-05-09 07:34:47 -06:00
|
|
|
* anyway we will just wait for the minimum amount and then check for a lockup
|
|
|
|
*/
|
2012-05-02 07:11:13 -06:00
|
|
|
timeout = 1;
|
|
|
|
}
|
2012-05-09 07:34:47 -06:00
|
|
|
seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
|
2012-05-09 07:34:46 -06:00
|
|
|
/* Save current last activity valuee, used to check for GPU lockups */
|
2012-05-09 07:34:47 -06:00
|
|
|
last_activity = rdev->fence_drv[ring].last_activity;
|
2012-05-02 07:11:13 -06:00
|
|
|
|
|
|
|
trace_radeon_fence_wait_begin(rdev->ddev, seq);
|
2012-05-09 07:34:47 -06:00
|
|
|
radeon_irq_kms_sw_irq_get(rdev, ring);
|
2012-05-02 07:11:13 -06:00
|
|
|
if (intr) {
|
2012-05-09 07:34:55 -06:00
|
|
|
r = wait_event_interruptible_timeout(rdev->fence_queue,
|
2012-05-09 07:34:47 -06:00
|
|
|
(signaled = radeon_fence_seq_signaled(rdev, target_seq, ring)),
|
|
|
|
timeout);
|
|
|
|
} else {
|
2012-05-09 07:34:55 -06:00
|
|
|
r = wait_event_timeout(rdev->fence_queue,
|
2012-05-09 07:34:47 -06:00
|
|
|
(signaled = radeon_fence_seq_signaled(rdev, target_seq, ring)),
|
|
|
|
timeout);
|
2012-05-02 07:11:13 -06:00
|
|
|
}
|
2012-05-09 07:34:47 -06:00
|
|
|
radeon_irq_kms_sw_irq_put(rdev, ring);
|
2010-03-09 07:45:12 -07:00
|
|
|
if (unlikely(r < 0)) {
|
2009-12-07 10:36:19 -07:00
|
|
|
return r;
|
2010-03-09 07:45:12 -07:00
|
|
|
}
|
2012-05-02 07:11:13 -06:00
|
|
|
trace_radeon_fence_wait_end(rdev->ddev, seq);
|
2012-05-02 07:11:10 -06:00
|
|
|
|
2012-05-02 07:11:13 -06:00
|
|
|
if (unlikely(!signaled)) {
|
|
|
|
/* we were interrupted for some reason and fence
|
|
|
|
* isn't signaled yet, resume waiting */
|
|
|
|
if (r) {
|
|
|
|
continue;
|
|
|
|
}
|
2012-05-02 07:11:10 -06:00
|
|
|
|
2012-05-09 07:34:47 -06:00
|
|
|
/* check if sequence value has changed since last_activity */
|
|
|
|
if (seq != atomic64_read(&rdev->fence_drv[ring].last_seq)) {
|
|
|
|
continue;
|
|
|
|
}
|
2012-05-09 07:34:48 -06:00
|
|
|
|
|
|
|
if (lock_ring) {
|
|
|
|
mutex_lock(&rdev->ring_lock);
|
|
|
|
}
|
|
|
|
|
2012-05-09 07:34:46 -06:00
|
|
|
/* test if somebody else has already decided that this is a lockup */
|
2012-05-09 07:34:47 -06:00
|
|
|
if (last_activity != rdev->fence_drv[ring].last_activity) {
|
2012-05-09 07:34:48 -06:00
|
|
|
if (lock_ring) {
|
|
|
|
mutex_unlock(&rdev->ring_lock);
|
|
|
|
}
|
2012-05-02 07:11:13 -06:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2012-05-09 07:34:47 -06:00
|
|
|
if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) {
|
2012-05-02 07:11:13 -06:00
|
|
|
/* good news we believe it's a lockup */
|
2012-05-09 07:34:46 -06:00
|
|
|
dev_warn(rdev->dev, "GPU lockup (waiting for 0x%016llx last fence id 0x%016llx)\n",
|
2012-05-09 07:34:47 -06:00
|
|
|
target_seq, seq);
|
|
|
|
|
|
|
|
/* change last activity so nobody else think there is a lockup */
|
|
|
|
for (i = 0; i < RADEON_NUM_RINGS; ++i) {
|
|
|
|
rdev->fence_drv[i].last_activity = jiffies;
|
|
|
|
}
|
2012-05-09 07:34:46 -06:00
|
|
|
|
2012-05-02 07:11:13 -06:00
|
|
|
/* mark the ring as not ready any more */
|
2012-05-09 07:34:47 -06:00
|
|
|
rdev->ring[ring].ready = false;
|
2012-05-09 07:34:48 -06:00
|
|
|
if (lock_ring) {
|
|
|
|
mutex_unlock(&rdev->ring_lock);
|
|
|
|
}
|
2012-05-02 07:11:19 -06:00
|
|
|
return -EDEADLK;
|
2012-05-02 07:11:13 -06:00
|
|
|
}
|
2012-05-09 07:34:48 -06:00
|
|
|
|
|
|
|
if (lock_ring) {
|
|
|
|
mutex_unlock(&rdev->ring_lock);
|
|
|
|
}
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:37 -06:00
|
|
|
/**
|
|
|
|
* radeon_fence_wait - wait for a fence to signal
|
|
|
|
*
|
|
|
|
* @fence: radeon fence object
|
|
|
|
* @intr: use interruptable sleep
|
|
|
|
*
|
|
|
|
* Wait for the requested fence to signal (all asics).
|
|
|
|
* @intr selects whether to use interruptable (true) or non-interruptable
|
|
|
|
* (false) sleep when waiting for the fence.
|
|
|
|
* Returns 0 if the fence has passed, error for all other cases.
|
|
|
|
*/
|
2012-05-09 07:34:47 -06:00
|
|
|
int radeon_fence_wait(struct radeon_fence *fence, bool intr)
|
2009-06-05 06:42:42 -06:00
|
|
|
{
|
|
|
|
int r;
|
|
|
|
|
2012-05-09 07:34:47 -06:00
|
|
|
if (fence == NULL) {
|
|
|
|
WARN(1, "Querying an invalid fence : %p !\n", fence);
|
|
|
|
return -EINVAL;
|
2012-05-02 07:11:10 -06:00
|
|
|
}
|
2012-05-09 07:34:47 -06:00
|
|
|
|
2012-05-09 07:34:48 -06:00
|
|
|
r = radeon_fence_wait_seq(fence->rdev, fence->seq,
|
|
|
|
fence->ring, intr, true);
|
2012-05-09 07:34:47 -06:00
|
|
|
if (r) {
|
|
|
|
return r;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
2012-05-09 07:34:47 -06:00
|
|
|
fence->seq = RADEON_FENCE_SIGNALED_SEQ;
|
|
|
|
return 0;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
2012-08-31 11:43:50 -06:00
|
|
|
static bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq)
|
2012-05-09 07:34:55 -06:00
|
|
|
{
|
|
|
|
unsigned i;
|
|
|
|
|
|
|
|
for (i = 0; i < RADEON_NUM_RINGS; ++i) {
|
|
|
|
if (seq[i] && radeon_fence_seq_signaled(rdev, seq[i], i)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:37 -06:00
|
|
|
/**
|
|
|
|
* radeon_fence_wait_any_seq - wait for a sequence number on any ring
|
|
|
|
*
|
|
|
|
* @rdev: radeon device pointer
|
|
|
|
* @target_seq: sequence number(s) we want to wait for
|
|
|
|
* @intr: use interruptable sleep
|
|
|
|
*
|
|
|
|
* Wait for the requested sequence number(s) to be written by any ring
|
|
|
|
* (all asics). Sequnce number array is indexed by ring id.
|
|
|
|
* @intr selects whether to use interruptable (true) or non-interruptable
|
|
|
|
* (false) sleep when waiting for the sequence number. Helper function
|
|
|
|
* for radeon_fence_wait_any(), et al.
|
|
|
|
* Returns 0 if the sequence number has passed, error for all other cases.
|
|
|
|
*/
|
2012-05-09 07:34:55 -06:00
|
|
|
static int radeon_fence_wait_any_seq(struct radeon_device *rdev,
|
|
|
|
u64 *target_seq, bool intr)
|
|
|
|
{
|
|
|
|
unsigned long timeout, last_activity, tmp;
|
|
|
|
unsigned i, ring = RADEON_NUM_RINGS;
|
|
|
|
bool signaled;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
for (i = 0, last_activity = 0; i < RADEON_NUM_RINGS; ++i) {
|
|
|
|
if (!target_seq[i]) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* use the most recent one as indicator */
|
|
|
|
if (time_after(rdev->fence_drv[i].last_activity, last_activity)) {
|
|
|
|
last_activity = rdev->fence_drv[i].last_activity;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* For lockup detection just pick the lowest ring we are
|
|
|
|
* actively waiting for
|
|
|
|
*/
|
|
|
|
if (i < ring) {
|
|
|
|
ring = i;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* nothing to wait for ? */
|
|
|
|
if (ring == RADEON_NUM_RINGS) {
|
2012-07-11 09:12:11 -06:00
|
|
|
return -ENOENT;
|
2012-05-09 07:34:55 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
while (!radeon_fence_any_seq_signaled(rdev, target_seq)) {
|
|
|
|
timeout = jiffies - RADEON_FENCE_JIFFIES_TIMEOUT;
|
|
|
|
if (time_after(last_activity, timeout)) {
|
|
|
|
/* the normal case, timeout is somewhere before last_activity */
|
|
|
|
timeout = last_activity - timeout;
|
|
|
|
} else {
|
|
|
|
/* either jiffies wrapped around, or no fence was signaled in the last 500ms
|
|
|
|
* anyway we will just wait for the minimum amount and then check for a lockup
|
|
|
|
*/
|
|
|
|
timeout = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
trace_radeon_fence_wait_begin(rdev->ddev, target_seq[ring]);
|
|
|
|
for (i = 0; i < RADEON_NUM_RINGS; ++i) {
|
|
|
|
if (target_seq[i]) {
|
|
|
|
radeon_irq_kms_sw_irq_get(rdev, i);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (intr) {
|
|
|
|
r = wait_event_interruptible_timeout(rdev->fence_queue,
|
|
|
|
(signaled = radeon_fence_any_seq_signaled(rdev, target_seq)),
|
|
|
|
timeout);
|
|
|
|
} else {
|
|
|
|
r = wait_event_timeout(rdev->fence_queue,
|
|
|
|
(signaled = radeon_fence_any_seq_signaled(rdev, target_seq)),
|
|
|
|
timeout);
|
|
|
|
}
|
|
|
|
for (i = 0; i < RADEON_NUM_RINGS; ++i) {
|
|
|
|
if (target_seq[i]) {
|
|
|
|
radeon_irq_kms_sw_irq_put(rdev, i);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (unlikely(r < 0)) {
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
trace_radeon_fence_wait_end(rdev->ddev, target_seq[ring]);
|
|
|
|
|
|
|
|
if (unlikely(!signaled)) {
|
|
|
|
/* we were interrupted for some reason and fence
|
|
|
|
* isn't signaled yet, resume waiting */
|
|
|
|
if (r) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
mutex_lock(&rdev->ring_lock);
|
|
|
|
for (i = 0, tmp = 0; i < RADEON_NUM_RINGS; ++i) {
|
|
|
|
if (time_after(rdev->fence_drv[i].last_activity, tmp)) {
|
|
|
|
tmp = rdev->fence_drv[i].last_activity;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/* test if somebody else has already decided that this is a lockup */
|
|
|
|
if (last_activity != tmp) {
|
|
|
|
last_activity = tmp;
|
|
|
|
mutex_unlock(&rdev->ring_lock);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) {
|
|
|
|
/* good news we believe it's a lockup */
|
|
|
|
dev_warn(rdev->dev, "GPU lockup (waiting for 0x%016llx)\n",
|
|
|
|
target_seq[ring]);
|
|
|
|
|
|
|
|
/* change last activity so nobody else think there is a lockup */
|
|
|
|
for (i = 0; i < RADEON_NUM_RINGS; ++i) {
|
|
|
|
rdev->fence_drv[i].last_activity = jiffies;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* mark the ring as not ready any more */
|
|
|
|
rdev->ring[ring].ready = false;
|
|
|
|
mutex_unlock(&rdev->ring_lock);
|
|
|
|
return -EDEADLK;
|
|
|
|
}
|
|
|
|
mutex_unlock(&rdev->ring_lock);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:37 -06:00
|
|
|
/**
|
|
|
|
* radeon_fence_wait_any - wait for a fence to signal on any ring
|
|
|
|
*
|
|
|
|
* @rdev: radeon device pointer
|
|
|
|
* @fences: radeon fence object(s)
|
|
|
|
* @intr: use interruptable sleep
|
|
|
|
*
|
|
|
|
* Wait for any requested fence to signal (all asics). Fence
|
|
|
|
* array is indexed by ring id. @intr selects whether to use
|
|
|
|
* interruptable (true) or non-interruptable (false) sleep when
|
|
|
|
* waiting for the fences. Used by the suballocator.
|
|
|
|
* Returns 0 if any fence has passed, error for all other cases.
|
|
|
|
*/
|
2012-05-09 07:34:55 -06:00
|
|
|
int radeon_fence_wait_any(struct radeon_device *rdev,
|
|
|
|
struct radeon_fence **fences,
|
|
|
|
bool intr)
|
|
|
|
{
|
|
|
|
uint64_t seq[RADEON_NUM_RINGS];
|
|
|
|
unsigned i;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
for (i = 0; i < RADEON_NUM_RINGS; ++i) {
|
|
|
|
seq[i] = 0;
|
|
|
|
|
|
|
|
if (!fences[i]) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (fences[i]->seq == RADEON_FENCE_SIGNALED_SEQ) {
|
|
|
|
/* something was allready signaled */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-05-08 06:24:01 -06:00
|
|
|
seq[i] = fences[i]->seq;
|
2012-05-09 07:34:55 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
r = radeon_fence_wait_any_seq(rdev, seq, intr);
|
|
|
|
if (r) {
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:37 -06:00
|
|
|
/**
|
|
|
|
* radeon_fence_wait_next_locked - wait for the next fence to signal
|
|
|
|
*
|
|
|
|
* @rdev: radeon device pointer
|
|
|
|
* @ring: ring index the fence is associated with
|
|
|
|
*
|
|
|
|
* Wait for the next fence on the requested ring to signal (all asics).
|
|
|
|
* Returns 0 if the next fence has passed, error for all other cases.
|
|
|
|
* Caller must hold ring lock.
|
|
|
|
*/
|
2012-05-09 07:34:48 -06:00
|
|
|
int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring)
|
2009-06-05 06:42:42 -06:00
|
|
|
{
|
2012-05-09 07:34:47 -06:00
|
|
|
uint64_t seq;
|
2009-06-05 06:42:42 -06:00
|
|
|
|
2012-05-09 07:34:47 -06:00
|
|
|
seq = atomic64_read(&rdev->fence_drv[ring].last_seq) + 1ULL;
|
2012-05-10 07:57:31 -06:00
|
|
|
if (seq >= rdev->fence_drv[ring].sync_seq[ring]) {
|
2012-05-09 07:34:48 -06:00
|
|
|
/* nothing to wait for, last_seq is
|
|
|
|
already the last emited fence */
|
|
|
|
return -ENOENT;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
2012-05-09 07:34:48 -06:00
|
|
|
return radeon_fence_wait_seq(rdev, seq, ring, false, false);
|
2012-05-09 07:34:47 -06:00
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:37 -06:00
|
|
|
/**
|
|
|
|
* radeon_fence_wait_empty_locked - wait for all fences to signal
|
|
|
|
*
|
|
|
|
* @rdev: radeon device pointer
|
|
|
|
* @ring: ring index the fence is associated with
|
|
|
|
*
|
|
|
|
* Wait for all fences on the requested ring to signal (all asics).
|
|
|
|
* Returns 0 if the fences have passed, error for all other cases.
|
|
|
|
* Caller must hold ring lock.
|
|
|
|
*/
|
2012-12-17 09:04:32 -07:00
|
|
|
int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring)
|
2012-05-09 07:34:47 -06:00
|
|
|
{
|
2012-06-29 03:33:12 -06:00
|
|
|
uint64_t seq = rdev->fence_drv[ring].sync_seq[ring];
|
2012-12-17 09:04:32 -07:00
|
|
|
int r;
|
2012-06-29 03:33:12 -06:00
|
|
|
|
2012-12-17 09:04:32 -07:00
|
|
|
r = radeon_fence_wait_seq(rdev, seq, ring, false, false);
|
|
|
|
if (r) {
|
2012-06-29 03:33:12 -06:00
|
|
|
if (r == -EDEADLK) {
|
2012-12-17 09:04:32 -07:00
|
|
|
return -EDEADLK;
|
2012-06-29 03:33:12 -06:00
|
|
|
}
|
2012-12-17 09:04:32 -07:00
|
|
|
dev_err(rdev->dev, "error waiting for ring[%d] to become idle (%d)\n",
|
|
|
|
ring, r);
|
2012-06-29 03:33:12 -06:00
|
|
|
}
|
2012-12-17 09:04:32 -07:00
|
|
|
return 0;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:37 -06:00
|
|
|
/**
|
|
|
|
* radeon_fence_ref - take a ref on a fence
|
|
|
|
*
|
|
|
|
* @fence: radeon fence object
|
|
|
|
*
|
|
|
|
* Take a reference on a fence (all asics).
|
|
|
|
* Returns the fence.
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
|
|
|
|
{
|
|
|
|
kref_get(&fence->kref);
|
|
|
|
return fence;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:37 -06:00
|
|
|
/**
|
|
|
|
* radeon_fence_unref - remove a ref on a fence
|
|
|
|
*
|
|
|
|
* @fence: radeon fence object
|
|
|
|
*
|
|
|
|
* Remove a reference on a fence (all asics).
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
void radeon_fence_unref(struct radeon_fence **fence)
|
|
|
|
{
|
|
|
|
struct radeon_fence *tmp = *fence;
|
|
|
|
|
|
|
|
*fence = NULL;
|
|
|
|
if (tmp) {
|
2011-02-26 17:34:08 -07:00
|
|
|
kref_put(&tmp->kref, radeon_fence_destroy);
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:37 -06:00
|
|
|
/**
|
|
|
|
* radeon_fence_count_emitted - get the count of emitted fences
|
|
|
|
*
|
|
|
|
* @rdev: radeon device pointer
|
|
|
|
* @ring: ring index the fence is associated with
|
|
|
|
*
|
|
|
|
* Get the number of fences emitted on the requested ring (all asics).
|
|
|
|
* Returns the number of emitted fences on the ring. Used by the
|
|
|
|
* dynpm code to ring track activity.
|
|
|
|
*/
|
2012-05-09 07:34:47 -06:00
|
|
|
unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring)
|
2009-06-05 06:42:42 -06:00
|
|
|
{
|
2012-05-09 07:34:47 -06:00
|
|
|
uint64_t emitted;
|
2009-06-05 06:42:42 -06:00
|
|
|
|
2012-05-09 07:34:47 -06:00
|
|
|
/* We are not protected by ring lock when reading the last sequence
|
|
|
|
* but it's ok to report slightly wrong fence count here.
|
|
|
|
*/
|
2012-05-09 07:34:55 -06:00
|
|
|
radeon_fence_process(rdev, ring);
|
2012-05-10 07:57:31 -06:00
|
|
|
emitted = rdev->fence_drv[ring].sync_seq[ring]
|
|
|
|
- atomic64_read(&rdev->fence_drv[ring].last_seq);
|
2012-05-09 07:34:47 -06:00
|
|
|
/* to avoid 32bits warp around */
|
|
|
|
if (emitted > 0x10000000) {
|
|
|
|
emitted = 0x10000000;
|
2011-10-20 04:38:09 -06:00
|
|
|
}
|
2012-05-09 07:34:47 -06:00
|
|
|
return (unsigned)emitted;
|
2011-10-20 04:38:09 -06:00
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:37 -06:00
|
|
|
/**
|
|
|
|
* radeon_fence_need_sync - do we need a semaphore
|
|
|
|
*
|
|
|
|
* @fence: radeon fence object
|
|
|
|
* @dst_ring: which ring to check against
|
|
|
|
*
|
|
|
|
* Check if the fence needs to be synced against another ring
|
|
|
|
* (all asics). If so, we need to emit a semaphore.
|
|
|
|
* Returns true if we need to sync with another ring, false if
|
|
|
|
* not.
|
|
|
|
*/
|
2012-05-10 07:57:31 -06:00
|
|
|
bool radeon_fence_need_sync(struct radeon_fence *fence, int dst_ring)
|
|
|
|
{
|
|
|
|
struct radeon_fence_driver *fdrv;
|
|
|
|
|
|
|
|
if (!fence) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (fence->ring == dst_ring) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* we are protected by the ring mutex */
|
|
|
|
fdrv = &fence->rdev->fence_drv[dst_ring];
|
|
|
|
if (fence->seq <= fdrv->sync_seq[fence->ring]) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:37 -06:00
|
|
|
/**
|
|
|
|
* radeon_fence_note_sync - record the sync point
|
|
|
|
*
|
|
|
|
* @fence: radeon fence object
|
|
|
|
* @dst_ring: which ring to check against
|
|
|
|
*
|
|
|
|
* Note the sequence number at which point the fence will
|
|
|
|
* be synced with the requested ring (all asics).
|
|
|
|
*/
|
2012-05-10 07:57:31 -06:00
|
|
|
void radeon_fence_note_sync(struct radeon_fence *fence, int dst_ring)
|
|
|
|
{
|
|
|
|
struct radeon_fence_driver *dst, *src;
|
|
|
|
unsigned i;
|
|
|
|
|
|
|
|
if (!fence) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (fence->ring == dst_ring) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* we are protected by the ring mutex */
|
|
|
|
src = &fence->rdev->fence_drv[fence->ring];
|
|
|
|
dst = &fence->rdev->fence_drv[dst_ring];
|
|
|
|
for (i = 0; i < RADEON_NUM_RINGS; ++i) {
|
|
|
|
if (i == dst_ring) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:37 -06:00
|
|
|
/**
|
|
|
|
* radeon_fence_driver_start_ring - make the fence driver
|
|
|
|
* ready for use on the requested ring.
|
|
|
|
*
|
|
|
|
* @rdev: radeon device pointer
|
|
|
|
* @ring: ring index to start the fence driver on
|
|
|
|
*
|
|
|
|
* Make the fence driver ready for processing (all asics).
|
|
|
|
* Not all asics have all rings, so each asic will only
|
|
|
|
* start the fence driver on the rings it has.
|
|
|
|
* Returns 0 for success, errors for failure.
|
|
|
|
*/
|
2011-11-20 13:45:34 -07:00
|
|
|
int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
|
2009-06-05 06:42:42 -06:00
|
|
|
{
|
2011-11-20 13:45:34 -07:00
|
|
|
uint64_t index;
|
|
|
|
int r;
|
2009-06-05 06:42:42 -06:00
|
|
|
|
2011-11-20 13:45:34 -07:00
|
|
|
radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
|
2012-12-12 14:43:15 -07:00
|
|
|
if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) {
|
2013-04-24 06:11:09 -06:00
|
|
|
rdev->fence_drv[ring].scratch_reg = 0;
|
2013-04-08 04:41:29 -06:00
|
|
|
if (ring != R600_RING_TYPE_UVD_INDEX) {
|
|
|
|
index = R600_WB_EVENT_OFFSET + ring * 4;
|
|
|
|
rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
|
|
|
|
rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr +
|
|
|
|
index;
|
|
|
|
|
|
|
|
} else {
|
|
|
|
/* put fence directly behind firmware */
|
2013-04-14 04:47:59 -06:00
|
|
|
index = ALIGN(rdev->uvd_fw->size, 8);
|
|
|
|
rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr + index;
|
|
|
|
rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index;
|
2013-04-08 04:41:29 -06:00
|
|
|
}
|
|
|
|
|
2011-11-20 13:45:34 -07:00
|
|
|
} else {
|
2011-08-25 11:39:48 -06:00
|
|
|
r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
|
|
|
|
if (r) {
|
|
|
|
dev_err(rdev->dev, "fence failed to get scratch register\n");
|
|
|
|
return r;
|
|
|
|
}
|
2011-11-20 13:45:34 -07:00
|
|
|
index = RADEON_WB_SCRATCH_OFFSET +
|
|
|
|
rdev->fence_drv[ring].scratch_reg -
|
|
|
|
rdev->scratch.reg_base;
|
2013-04-08 04:41:29 -06:00
|
|
|
rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
|
|
|
|
rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
|
2011-08-25 11:39:48 -06:00
|
|
|
}
|
2012-07-07 05:10:39 -06:00
|
|
|
radeon_fence_write(rdev, atomic64_read(&rdev->fence_drv[ring].last_seq), ring);
|
2011-11-20 13:45:34 -07:00
|
|
|
rdev->fence_drv[ring].initialized = true;
|
2012-05-09 07:34:47 -06:00
|
|
|
dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016llx and cpu addr 0x%p\n",
|
2011-11-20 13:45:34 -07:00
|
|
|
ring, rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:37 -06:00
|
|
|
/**
|
|
|
|
* radeon_fence_driver_init_ring - init the fence driver
|
|
|
|
* for the requested ring.
|
|
|
|
*
|
|
|
|
* @rdev: radeon device pointer
|
|
|
|
* @ring: ring index to start the fence driver on
|
|
|
|
*
|
|
|
|
* Init the fence driver for the requested ring (all asics).
|
|
|
|
* Helper function for radeon_fence_driver_init().
|
|
|
|
*/
|
2011-11-20 13:45:34 -07:00
|
|
|
static void radeon_fence_driver_init_ring(struct radeon_device *rdev, int ring)
|
|
|
|
{
|
2012-05-10 07:57:31 -06:00
|
|
|
int i;
|
|
|
|
|
2011-11-20 13:45:34 -07:00
|
|
|
rdev->fence_drv[ring].scratch_reg = -1;
|
|
|
|
rdev->fence_drv[ring].cpu_addr = NULL;
|
|
|
|
rdev->fence_drv[ring].gpu_addr = 0;
|
2012-05-10 07:57:31 -06:00
|
|
|
for (i = 0; i < RADEON_NUM_RINGS; ++i)
|
|
|
|
rdev->fence_drv[ring].sync_seq[i] = 0;
|
2012-05-09 07:34:46 -06:00
|
|
|
atomic64_set(&rdev->fence_drv[ring].last_seq, 0);
|
2012-05-09 07:34:47 -06:00
|
|
|
rdev->fence_drv[ring].last_activity = jiffies;
|
2011-11-20 13:45:34 -07:00
|
|
|
rdev->fence_drv[ring].initialized = false;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:37 -06:00
|
|
|
/**
|
|
|
|
* radeon_fence_driver_init - init the fence driver
|
|
|
|
* for all possible rings.
|
|
|
|
*
|
|
|
|
* @rdev: radeon device pointer
|
|
|
|
*
|
|
|
|
* Init the fence driver for all possible rings (all asics).
|
|
|
|
* Not all asics have all rings, so each asic will only
|
|
|
|
* start the fence driver on the rings it has using
|
|
|
|
* radeon_fence_driver_start_ring().
|
|
|
|
* Returns 0 for success.
|
|
|
|
*/
|
2011-11-20 13:45:34 -07:00
|
|
|
int radeon_fence_driver_init(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
int ring;
|
|
|
|
|
2012-05-09 07:34:55 -06:00
|
|
|
init_waitqueue_head(&rdev->fence_queue);
|
2011-11-20 13:45:34 -07:00
|
|
|
for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
|
|
|
|
radeon_fence_driver_init_ring(rdev, ring);
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
if (radeon_debugfs_fence_init(rdev)) {
|
2009-12-11 12:36:19 -07:00
|
|
|
dev_err(rdev->dev, "fence debugfs file creation failed\n");
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:37 -06:00
|
|
|
/**
|
|
|
|
* radeon_fence_driver_fini - tear down the fence driver
|
|
|
|
* for all possible rings.
|
|
|
|
*
|
|
|
|
* @rdev: radeon device pointer
|
|
|
|
*
|
|
|
|
* Tear down the fence driver for all possible rings (all asics).
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
void radeon_fence_driver_fini(struct radeon_device *rdev)
|
|
|
|
{
|
2012-12-17 09:04:32 -07:00
|
|
|
int ring, r;
|
2011-08-25 11:39:48 -06:00
|
|
|
|
2012-05-09 07:34:48 -06:00
|
|
|
mutex_lock(&rdev->ring_lock);
|
2011-08-25 11:39:48 -06:00
|
|
|
for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
|
|
|
|
if (!rdev->fence_drv[ring].initialized)
|
|
|
|
continue;
|
2012-12-17 09:04:32 -07:00
|
|
|
r = radeon_fence_wait_empty_locked(rdev, ring);
|
|
|
|
if (r) {
|
|
|
|
/* no need to trigger GPU reset as we are unloading */
|
|
|
|
radeon_fence_driver_force_completion(rdev);
|
|
|
|
}
|
2012-05-09 07:34:55 -06:00
|
|
|
wake_up_all(&rdev->fence_queue);
|
2011-08-25 11:39:48 -06:00
|
|
|
radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
|
|
|
|
rdev->fence_drv[ring].initialized = false;
|
|
|
|
}
|
2012-05-09 07:34:48 -06:00
|
|
|
mutex_unlock(&rdev->ring_lock);
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
2012-12-17 08:29:06 -07:00
|
|
|
/**
|
|
|
|
* radeon_fence_driver_force_completion - force all fence waiter to complete
|
|
|
|
*
|
|
|
|
* @rdev: radeon device pointer
|
|
|
|
*
|
|
|
|
* In case of GPU reset failure make sure no process keep waiting on fence
|
|
|
|
* that will never complete.
|
|
|
|
*/
|
|
|
|
void radeon_fence_driver_force_completion(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
int ring;
|
|
|
|
|
|
|
|
for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
|
|
|
|
if (!rdev->fence_drv[ring].initialized)
|
|
|
|
continue;
|
|
|
|
radeon_fence_write(rdev, rdev->fence_drv[ring].sync_seq[ring], ring);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-06-05 06:42:42 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Fence debugfs
|
|
|
|
*/
|
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = (struct drm_info_node *)m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
2012-05-10 07:57:31 -06:00
|
|
|
int i, j;
|
2011-08-25 11:39:48 -06:00
|
|
|
|
|
|
|
for (i = 0; i < RADEON_NUM_RINGS; ++i) {
|
|
|
|
if (!rdev->fence_drv[i].initialized)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
seq_printf(m, "--- ring %d ---\n", i);
|
2012-05-09 10:27:29 -06:00
|
|
|
seq_printf(m, "Last signaled fence 0x%016llx\n",
|
|
|
|
(unsigned long long)atomic64_read(&rdev->fence_drv[i].last_seq));
|
2012-05-10 07:57:31 -06:00
|
|
|
seq_printf(m, "Last emitted 0x%016llx\n",
|
|
|
|
rdev->fence_drv[i].sync_seq[i]);
|
|
|
|
|
|
|
|
for (j = 0; j < RADEON_NUM_RINGS; ++j) {
|
|
|
|
if (i != j && rdev->fence_drv[j].initialized)
|
|
|
|
seq_printf(m, "Last sync to ring %d 0x%016llx\n",
|
|
|
|
j, rdev->fence_drv[i].sync_seq[j]);
|
|
|
|
}
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct drm_info_list radeon_debugfs_fence_list[] = {
|
|
|
|
{"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
int radeon_debugfs_fence_init(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
|
|
|
|
#else
|
|
|
|
return 0;
|
|
|
|
#endif
|
|
|
|
}
|