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Merge remote-tracking branch 'origin/dts/qoriq' into dts/next 

* origin/dts/qoriq: (105 commits)
  arm64: dts: fsl: ls1028a: Disable eno3 and make swp5 the Felix CPU port
  arm64: dts: fsl: ls1028a: Specify that the Felix port 4 runs at 2.5Gbps
  arm64: dts: fsl: Drop "compatible" string from Felix switch
  arm64: dts: fsl: Specify phy-mode for CPU ports
  arm64: dts: ls1028a: Add DP DT nodes
  ...
5.4-rM2-2.2.x-imx-squashed
Dong Aisheng 2019-12-02 18:01:17 +08:00
parent b62cc9d2c6 243f4bdb2b
commit 3c1f476273
156 changed files with 8097 additions and 459 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt
View File

@ -8,7 +8,7 @@ Required properties:
- compatible: Should contain a chip-specific compatible string,
Chip-specific strings are of the form "fsl,<chip>-dcfg",
The following <chip>s are known to be supported:
ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
ls1012a, ls1021a, ls1043a, ls1046a, ls2080a, lx2160a
- reg : should contain base address and length of DCFG memory-mapped registers

8
Documentation/devicetree/bindings/arm/fsl.yaml
View File

@ -287,6 +287,7 @@ properties:
- ebs-systart,oxalis
- fsl,ls1012a-rdb
- fsl,ls1012a-frdm
- fsl,ls1012a-frwy
- fsl,ls1012a-qds
- const: fsl,ls1012a
@ -335,4 +336,11 @@ properties:
- fsl,ls2088a-rdb
- const: fsl,ls2088a
- description: LX2160A based Boards
items:
- enum:
- fsl,lx2160a-qds
- fsl,lx2160a-rdb
- const: fsl,lx2160a
...

1
Documentation/devicetree/bindings/clock/qoriq-clock.txt
View File

@ -44,6 +44,7 @@ Required properties:
* "fsl,ls1046a-clockgen"
* "fsl,ls1088a-clockgen"
* "fsl,ls2080a-clockgen"
* "fsl,lx2160a-clockgen"
Chassis-version clock strings include:
* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks

46
Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
View File

@ -12,9 +12,42 @@ Required properties:
- reg : Offset and length of the register set for this device
- interrupts : Interrupt tuple for this device
Optional properties:
Clocking information is must for flexcan. please refer below info for
understanding clocking in flexcan:
- clock-frequency : The oscillator frequency driving the flexcan device
• The FLEXCAN module is divided into two blocks. Controller host interface
("CHI") and Protocol Engine ("PE")
• Both these blocks require clock.
• CHI is responsible for registers read write including MB read/write.
While PE is responsible for Transfer/receive data on CAN bus.
• The clocks feeding to these two blocks can be synchronous (i.e. same clock)
or asynchronous (i.e. separate clocks).
• Selection is made in the CLK_SRC bit (bit 13) of Control 1 Register.
- CLK_SRC = 0, asynchronous i.e. separate clocks for CHI and PE
- CLK_SRC = 1, synchronous i.e. CHI clock is used for PE and PE
clock is not used.
• If this bit is not implemented in SOC, then SOC only supports asynchronous
clocks.
• Either of the clock can be generated by any of the clock source.
• When the two clocks are asynchronous, then following restrictions apply to
PE clock.
- PE clock must be less than CHI clock.
• If low jitter is required on CAN bus, dedicated oscillator can be used to
provide PE clock, but it must be less than CHI clock.
Base on above information clocking info in flexcan can be defined in two ways:
Method 1(Preferred):
- clocks: phandle to the clocks feeding the flexcan. Two can be given:
- "ipg": Protocol Engine clock
- "per": Controller host interface clock
- clock-names: Must contain the clock names described just above.
Method 2(Not Preferred):
- clock-frequency : The synchronous clock frequency supplied to both
Controller host interface and Protocol Engine
Optional properties:
- xceiver-supply: Regulator that powers the CAN transceiver
@ -51,3 +84,12 @@ Example:
clock-frequency = <200000000>; // filled in by bootloader
fsl,clk-source = <0>; // select clock source 0 for PE
};
can@2180000 {
compatible = "fsl,lx2160ar1-flexcan";
reg = <0x0 0x2180000 0x0 0x10000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysclk>, <&clockgen 4 7>;
clock-names = "ipg", "per";
status = "disabled";
};

1
Documentation/devicetree/bindings/pci/layerscape-pci.txt
View File

@ -21,6 +21,7 @@ Required properties:
"fsl,ls1046a-pcie"
"fsl,ls1043a-pcie"
"fsl,ls1012a-pcie"
"fsl,ls1028a-pcie"
EP mode:
"fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
- reg: base addresses and lengths of the PCIe controller register blocks.

19
arch/arm/boot/dts/ls1021a-qds.dts
View File

@ -126,6 +126,21 @@
};
};
&qspi {
num-cs = <2>;
status = "okay";
qflash0: s25fl128s@0 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
reg = <0>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
};
&enet0 {
tbi-handle = <&tbi0>;
phy-handle = <&sgmii_phy1c>;
@ -150,6 +165,10 @@
status = "okay";
};
&esdhc {
status = "okay";
};
&i2c0 {
status = "okay";

15
arch/arm/boot/dts/ls1021a-twr.dts
View File

@ -144,6 +144,21 @@
};
};
&qspi {
num-cs = <2>;
status = "okay";
qflash0: n25q128a13@0 {
compatible = "n25q128a13", "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
reg = <0>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
};
&enet0 {
tbi-handle = <&tbi0>;
phy-handle = <&sgmii_phy2>;

40
arch/arm/boot/dts/ls1021a.dtsi
View File

@ -66,6 +66,7 @@
serial4 = &lpuart4;
serial5 = &lpuart5;
sysclk = &sysclk;
rtc1 = &ftm_alarm0;
};
cpus {
@ -167,12 +168,13 @@
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x1530000 0x0 0x10000>;
big-endian;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
};
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1021a-dcfg", "syscon";
reg = <0x0 0x1ee0000 0x0 0x10000>;
reg = <0x0 0x1ee0000 0x0 0x1000>;
big-endian;
};
@ -371,7 +373,7 @@
};
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
@ -380,11 +382,12 @@
clocks = <&clockgen 4 1>;
dma-names = "tx", "rx";
dmas = <&edma0 1 39>, <&edma0 1 38>;
fsl-scl-gpio = <&gpio3 23 0>;
status = "disabled";
};
i2c1: i2c@2190000 {
compatible = "fsl,vf610-i2c";
compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2190000 0x0 0x10000>;
@ -393,6 +396,7 @@
clocks = <&clockgen 4 1>;
dma-names = "tx", "rx";
dmas = <&edma0 1 37>, <&edma0 1 36>;
fsl-scl-gpio = <&gpio3 23 0>;
status = "disabled";
};
@ -861,7 +865,10 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
snps,host-vbus-glitches;
};
pcie@3400000 {
@ -869,7 +876,9 @@
reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "pme", "aer";
fsl,pcie-scfg = <&scfg 0>;
#address-cells = <3>;
#size-cells = <2>;
@ -893,7 +902,9 @@
reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
0x48 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "pme", "aer";
fsl,pcie-scfg = <&scfg 1>;
#address-cells = <3>;
#size-cells = <2>;
@ -983,5 +994,24 @@
big-endian;
};
rcpm: rcpm@1ee2140 {
compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
reg = <0x0 0x1ee2140 0x0 0x8>;
#fsl,rcpm-wakeup-cells = <2>;
/*
* The second and third entry compose an alt offset
* address for IPPDEXPCR1(SCFG_SPARECR8)
*/
fsl,ippdexpcr1-alt-addr = <&scfg 0x0 0x51c>;
};
ftm_alarm0: timer0@29d0000 {
compatible = "fsl,ls1021a-ftm-alarm";
reg = <0x0 0x29d0000 0x0 0x10000>;
fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
big-endian;
};
};
};

10
arch/arm64/boot/dts/freescale/Makefile
View File

@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-2g5rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb
@ -7,14 +8,23 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy-sdk.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy-usdpaa.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-sdk.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb

89
arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts 100644
View File

@ -0,0 +1,89 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for NXP LS1012A 2G5RDB Board.
*
* Copyright 2017 NXP
*
* Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
*/
/dts-v1/;
#include "fsl-ls1012a.dtsi"
/ {
model = "LS1012A 2G5RDB Board";
compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
aliases {
ethernet0 = &pfe_mac0;
ethernet1 = &pfe_mac1;
};
};
&duart0 {
status = "okay";
};
&i2c0 {
status = "okay";
};
&qspi {
num-cs = <2>;
bus-num = <0>;
status = "okay";
qflash0: s25fs512s@0 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
m25p,fast-read;
reg = <0>;
};
};
&sata {
status = "okay";
};
&pfe {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
pfe_mac0: ethernet@0 {
compatible = "fsl,pfe-gemac-port";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>; /* GEM_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "sgmii-2500";
phy-handle = <&sgmii_phy1>;
};
pfe_mac1: ethernet@1 {
compatible = "fsl,pfe-gemac-port";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>; /* GEM_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "sgmii-2500";
phy-handle = <&sgmii_phy2>;
};
mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
sgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
sgmii_phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x2>;
};
};
};

59
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
View File

@ -13,6 +13,11 @@
model = "LS1012A Freedom Board";
compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
aliases {
ethernet0 = &pfe_mac0;
ethernet1 = &pfe_mac1;
};
sys_mclk: clock-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -74,6 +79,45 @@
};
};
&pfe {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
pfe_mac0: ethernet@0 {
compatible = "fsl,pfe-gemac-port";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>; /* GEM_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "sgmii";
phy-handle = <&sgmii_phy1>;
};
pfe_mac1: ethernet@1 {
compatible = "fsl,pfe-gemac-port";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>; /* GEM_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "sgmii";
phy-handle = <&sgmii_phy2>;
};
mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
sgmii_phy1: ethernet-phy@2 {
reg = <0x2>;
};
sgmii_phy2: ethernet-phy@1 {
reg = <0x1>;
};
};
};
&sai2 {
status = "okay";
};
@ -81,3 +125,18 @@
&sata {
status = "okay";
};
&qspi {
status = "okay";
qflash0: s25fs512s@0 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
m25p,fast-read;
reg = <0>;
spi-rx-bus-width = <2>;
spi-tx-bus-width = <2>;
};
};

120
arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
View File

@ -14,6 +14,58 @@
/ {
model = "LS1012A FRWY Board";
compatible = "fsl,ls1012a-frwy", "fsl,ls1012a";
aliases {
ethernet0 = &pfe_mac0;
ethernet1 = &pfe_mac1;
};
sys_mclk: clock-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Speaker", "Speaker Ext",
"Line", "Line In Jack";
simple-audio-card,routing =
"MIC_IN", "Microphone Jack",
"Microphone Jack", "Mic Bias",
"LINE_IN", "Line In Jack",
"Headphone Jack", "HP_OUT",
"Speaker Ext", "LINE_OUT";
simple-audio-card,cpu {
sound-dai = <&sai2>;
frame-master;
bitclock-master;
};
simple-audio-card,codec {
sound-dai = <&codec>;
frame-master;
bitclock-master;
system-clock-frequency = <25000000>;
};
};
};
&pcie {
status = "okay";
};
&duart0 {
@ -22,4 +74,72 @@
&i2c0 {
status = "okay";
codec: sgtl5000@a {
compatible = "fsl,sgtl5000";
#sound-dai-cells = <0>;
reg = <0xa>;
VDDA-supply = <&reg_1p8v>;
VDDIO-supply = <&reg_1p8v>;
clocks = <&sys_mclk>;
};
};
&qspi {
num-cs = <1>;
bus-num = <0>;
status = "okay";
qflash0: w25q16dw@0 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
m25p,fast-read;
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&pfe {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
pfe_mac0: ethernet@0 {
compatible = "fsl,pfe-gemac-port";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>; /* GEM_ID */
fsl,gemac-bus-id = <0x0>; /* BUS_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "sgmii";
phy-handle = <&sgmii_phy1>;
};
pfe_mac1: ethernet@1 {
compatible = "fsl,pfe-gemac-port";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>; /* GEM_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "sgmii";
phy-handle = <&sgmii_phy2>;
};
mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
sgmii_phy1: ethernet-phy@2 {
reg = <0x2>;
};
sgmii_phy2: ethernet-phy@1 {
reg = <0x1>;
};
};
};
&sai2 {
status = "okay";
};

65
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
View File

@ -13,6 +13,11 @@
model = "LS1012A QDS Board";
compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
aliases {
ethernet0 = &pfe_mac0;
ethernet1 = &pfe_mac1;
};
sys_mclk: clock-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -57,6 +62,10 @@
};
};
&pcie {
status = "okay";
};
&dspi {
bus-num = <0>;
status = "okay";
@ -128,6 +137,47 @@
};
};
&pfe {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
pfe_mac0: ethernet@0 {
compatible = "fsl,pfe-gemac-port";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>; /* GEM_ID */
fsl,mdio-mux-val = <0x2>;
phy-mode = "sgmii-2500";
phy-handle = <&sgmii_phy1>;
};
pfe_mac1: ethernet@1 {
compatible = "fsl,pfe-gemac-port";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>; /* GEM_ID */
fsl,mdio-mux-val = <0x3>;
phy-mode = "sgmii-2500";
phy-handle = <&sgmii_phy2>;
};
mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
sgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
sgmii_phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x2>;
};
};
};
&sai2 {
status = "okay";
};
@ -135,3 +185,18 @@
&sata {
status = "okay";
};
&qspi {
status = "okay";
qflash0: s25fs512s@0 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
m25p,fast-read;
reg = <0>;
spi-rx-bus-width = <2>;
spi-tx-bus-width = <2>;
};
};

62
arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
View File

@ -12,6 +12,15 @@
/ {
model = "LS1012A RDB Board";
compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
aliases {
ethernet0 = &pfe_mac0;
ethernet1 = &pfe_mac1;
};
};
&pcie {
status = "okay";
};
&duart0 {
@ -38,3 +47,56 @@
&sata {
status = "okay";
};
&pfe {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
pfe_mac0: ethernet@0 {
compatible = "fsl,pfe-gemac-port";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>; /* GEM_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "sgmii";
phy-handle = <&sgmii_phy>;
};
pfe_mac1: ethernet@1 {
compatible = "fsl,pfe-gemac-port";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>; /* GEM_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "rgmii-txid";
phy-handle = <&rgmii_phy>;
};
mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
sgmii_phy: ethernet-phy@2 {
reg = <0x2>;
};
rgmii_phy: ethernet-phy@1 {
reg = <0x1>;
};
};
};
&qspi {
status = "okay";
qflash0: s25fs512s@0 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
m25p,fast-read;
reg = <0>;
spi-rx-bus-width = <2>;
spi-tx-bus-width = <2>;
};
};

105
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
View File

@ -3,6 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1012A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
*
*/
@ -22,13 +23,14 @@
rtic-c = &rtic_c;
rtic-d = &rtic_d;
sec-mon = &sec_mon;
rtc1 = &ftm_alarm0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
cooling_map0: cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
@ -100,36 +102,7 @@
mask = <0x02>;
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 0>;
trips {
cpu_alert: cpu-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
};
#include "fsl-tmu.dtsi"
soc {
compatible = "simple-bus";
@ -260,7 +233,7 @@
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1012a-dcfg",
"syscon";
reg = <0x0 0x1ee0000 0x0 0x10000>;
reg = <0x0 0x1ee0000 0x0 0x1000>;
big-endian;
};
@ -317,13 +290,29 @@
#thermal-sensor-cells = <1>;
};
rcpm: rcpm@1ee2140 {
compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+";
reg = <0x0 0x1ee2140 0x0 0x4>;
#fsl,rcpm-wakeup-cells = <1>;
};
ftm_alarm0: timer@29d0000 {
compatible = "fsl,ls1012a-ftm-alarm";
reg = <0x0 0x29d0000 0x0 0x10000>;
fsl,rcpm-wakeup = <&rcpm 0x20000>;
interrupts = <0 86 0x4>;
big-endian;
};
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
compatible = "fsl,vf610-i2c", "fsl,ls1012a-vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>;
scl-gpios = <&gpio0 13 0>;
status = "disabled";
};
@ -395,6 +384,20 @@
big-endian;
};
qspi: spi@1550000 {
compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x1550000 0x0 0x10000>,
<0x0 0x40000000 0x0 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "qspi_en", "qspi";
clocks = <&clockgen 4 0>, <&clockgen 4 0>;
big-endian;
status = "disabled";
};
sai1: sai@2b50000 {
#sound-dai-cells = <0>;
compatible = "fsl,vf610-sai";
@ -447,6 +450,7 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
snps,host-vbus-glitches;
};
sata: sata@3200000 {
@ -501,6 +505,35 @@
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
pfe_reserved: packetbuffer@83400000 {
reg = <0 0x83400000 0 0xc00000>;
};
};
pfe: pfe@4000000 {
compatible = "fsl,pfe";
reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
<0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
reg-names = "pfe", "pfe-ddr";
fsl,pfe-num-interfaces = <0x2>;
interrupts = <0 172 0x4>, /* HIF interrupt */
<0 173 0x4>, /*HIF_NOCPY interrupt */
<0 174 0x4>; /* WoL interrupt */
interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
memory-region = <&pfe_reserved>;
fsl,pfe-scfg = <&scfg 0>;
fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
clocks = <&clockgen 4 0>;
clock-names = "pfe";
status = "okay";
};
firmware {
optee {
compatible = "linaro,optee-tz";
@ -508,3 +541,9 @@
};
};
};
&thermal_zones {
thermal-zone0 {
status = "okay";
};
};

20
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-1xxx.dtsi 100644
View File

@ -0,0 +1,20 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for LS1028A QDS board, serdes 1xxx
*
* Copyright 2019 NXP
*
*/
&mdio_slot1 {
slot1_sgmii: ethernet-phy@2 {
/* AQR112 */
reg = <0x2>;
compatible = "ethernet-phy-ieee802.3-c45";
};
};
&enetc_port0 {
phy-handle = <&slot1_sgmii>;
phy-connection-type = "usxgmii";
};

20
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-6xxx.dtsi 100644
View File

@ -0,0 +1,20 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for LS1028A QDS board, serdes 6xxx
*
* Copyright 2019 NXP
*
*/
&mdio_slot1 {
slot1_sgmii: ethernet-phy@2 {
/* AQR112 */
reg = <0x2>;
compatible = "ethernet-phy-ieee802.3-c45";
};
};
&enetc_port0 {
phy-handle = <&slot1_sgmii>;
phy-connection-type = "2500base-x";
};

56
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi 100644
View File

@ -0,0 +1,56 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for LS1028A QDS board, serdes 9999
*
* Copyright 2019 NXP
*
*/
&mdio_slot1 {
/* two ports on AQR412 */
slot1_sxgmii2: ethernet-phy@2 {
reg = <0x2>;
compatible = "ethernet-phy-ieee802.3-c45";
};
slot1_sxgmii3: ethernet-phy@3 {
reg = <0x3>;
compatible = "ethernet-phy-ieee802.3-c45";
};
};
&mdio_slot2 {
slot2_sxgmii0: ethernet-phy@2 {
/* AQR112 */
reg = <0x2>;
compatible = "ethernet-phy-ieee802.3-c45";
};
};
&mdio_slot3 {
slot3_sxgmii0: ethernet-phy@2 {
/* AQR112 */
reg = <0x2>;
compatible = "ethernet-phy-ieee802.3-c45";
};
};
/* l2switch ports */
&switch_port0 {
phy-handle = <&slot1_sxgmii2>;
phy-connection-type = "2500base-x";
};
&switch_port1 {
phy-handle = <&slot2_sxgmii0>;
phy-connection-type = "2500base-x";
};
&switch_port2 {
phy-handle = <&slot3_sxgmii0>;
phy-connection-type = "2500base-x";
};
&switch_port3 {
phy-handle = <&slot1_sxgmii3>;
phy-connection-type = "2500base-x";
};

19
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-8xxx.dtsi 100644
View File

@ -0,0 +1,19 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for LS1028A QDS board, serdes 8xxx
*
* Copyright 2019 NXP
*
*/
&mdio_slot1 {
slot1_sgmii: ethernet-phy@1c {
/* 1st port on VSC8234 */
reg = <0x1c>;
};
};
&enetc_port0 {
phy-handle = <&slot1_sgmii>;
phy-connection-type = "sgmii";
};

60
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi 100644
View File

@ -0,0 +1,60 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for LS1028A QDS board, serdes 9999
*
* Copyright 2019 NXP
*
*/
&mdio_slot1 {
/* VSC8234 */
slot1_sgmii0: ethernet-phy@1c {
reg = <0x1c>;
};
slot1_sgmii1: ethernet-phy@1d {
reg = <0x1d>;
};
slot1_sgmii2: ethernet-phy@1e {
reg = <0x1e>;
};
slot1_sgmii3: ethernet-phy@1f {
reg = <0x1f>;
};
};
&mdio_slot2 {
/* VSC8234 */
slot2_sgmii0: ethernet-phy@1c {
reg = <0x1c>;
};
slot2_sgmii1: ethernet-phy@1d {
reg = <0x1d>;
};
slot2_sgmii2: ethernet-phy@1e {
reg = <0x1e>;
};
slot2_sgmii3: ethernet-phy@1f {
reg = <0x1f>;
};
};
/* l2switch ports */
&switch_port0 {
phy-handle = <&slot1_sgmii0>;
phy-connection-type = "sgmii";
};
&switch_port1 {
phy-handle = <&slot2_sgmii0>;
phy-connection-type = "sgmii";
};
&switch_port2 {
phy-handle = <&slot1_sgmii2>;
phy-connection-type = "sgmii";
};
&switch_port3 {
phy-handle = <&slot1_sgmii3>;
phy-connection-type = "sgmii";
};

48
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi 100644
View File

@ -0,0 +1,48 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for LS1028A QDS board, serdes x3xx
*
* Copyright 2019 NXP
*
*/
&mdio_slot2 {
/* 4 ports on AQR412 */
slot2_qsgmii0: ethernet-phy@0 {
reg = <0x0>;
compatible = "ethernet-phy-ieee802.3-c45";
};
slot2_qsgmii1: ethernet-phy@1 {
reg = <0x1>;
compatible = "ethernet-phy-ieee802.3-c45";
};
slot2_qsgmii2: ethernet-phy@2 {
reg = <0x2>;
compatible = "ethernet-phy-ieee802.3-c45";
};
slot2_qsgmii3: ethernet-phy@3 {
reg = <0x3>;
compatible = "ethernet-phy-ieee802.3-c45";
};
};
/* l2switch ports */
&switch_port0 {
phy-handle = <&slot2_qsgmii0>;
phy-connection-type = "usxgmii";
};
&switch_port1 {
phy-handle = <&slot2_qsgmii1>;
phy-connection-type = "usxgmii";
};
&switch_port2 {
phy-handle = <&slot2_qsgmii2>;
phy-connection-type = "usxgmii";
};
&switch_port3 {
phy-handle = <&slot2_qsgmii3>;
phy-connection-type = "usxgmii";
};

44
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi 100644
View File

@ -0,0 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for LS1028A QDS board, serdes x5xx
*
* Copyright 2019 NXP
*
*/
&mdio_slot2 {
/* 4 ports on VSC8514 */
slot2_qsgmii0: ethernet-phy@8 {
reg = <0x8>;
};
slot2_qsgmii1: ethernet-phy@9 {
reg = <0x9>;
};
slot2_qsgmii2: ethernet-phy@a {
reg = <0xa>;
};
slot2_qsgmii3: ethernet-phy@b {
reg = <0xb>;
};
};
/* l2switch ports */
&switch_port0 {
phy-handle = <&slot2_qsgmii0>;
phy-connection-type = "qsgmii";
};
&switch_port1 {
phy-handle = <&slot2_qsgmii1>;
phy-connection-type = "qsgmii";
};
&switch_port2 {
phy-handle = <&slot2_qsgmii2>;
phy-connection-type = "qsgmii";
};
&switch_port3 {
phy-handle = <&slot2_qsgmii3>;
phy-connection-type = "qsgmii";
};

70
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
View File

@ -2,7 +2,7 @@
/*
* Device Tree file for NXP LS1028A QDS Board.
*
* Copyright 2018 NXP
* Copyright 2018-2019 NXP
*
* Harninder Rai <harninder.rai@nxp.com>
*
@ -104,9 +104,41 @@
reg = <5>;
};
};
mdio_slot1: mdio@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
mdio_slot2: mdio@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
mdio_slot3: mdio@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
mdio_slot4: mdio@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
&can0 {
status = "okay";
};
&can1 {
status = "okay";
};
&duart0 {
status = "okay";
};
@ -161,11 +193,6 @@
vcc-supply = <&sb_3v3>;
};
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
};
eeprom@56 {
compatible = "atmel,24c512";
reg = <0x56>;
@ -209,11 +236,34 @@
};
&i2c1 {
status = "okay";
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
};
};
&enetc_port1 {
phy-handle = <&qds_phy1>;
phy-connection-type = "rgmii-id";
};
&fspi {
status = "okay";
mt35xu02g: flash@0 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
m25p,fast-read;
spi-max-frequency = <20000000>;
reg = <0>;
/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
spi-tx-bus-width = <1>; /* 1 SPI Tx line */
};
};
&sai1 {
status = "okay";
};
@ -221,3 +271,11 @@
&sata {
status = "okay";
};
&hdptx0 {
lane-mapping = <0x4e>;
status = "okay";
};
#include "fsl-ls1028a-qds-8xxx.dtsi"
#include "fsl-ls1028a-qds-x5xx.dtsi"

93
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
View File

@ -2,7 +2,7 @@
/*
* Device Tree file for NXP LS1028A RDB Board.
*
* Copyright 2018 NXP
* Copyright 2018-2019 NXP
*
* Harninder Rai <harninder.rai@nxp.com>
*
@ -93,9 +93,15 @@
&esdhc1 {
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
status = "okay";
};
&usb1 {
dr_mode = "otg";
};
&i2c0 {
status = "okay";
@ -152,6 +158,37 @@
};
};
&can0 {
status = "okay";
can-transceiver {
max-bitrate = <5000000>;
};
};
&can1 {
status = "okay";
can-transceiver {
max-bitrate = <5000000>;
};
};
&fspi {
status = "okay";
mt35xu02g: flash@0 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
m25p,fast-read;
spi-max-frequency = <20000000>;
reg = <0>;
/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
spi-tx-bus-width = <1>; /* 1 SPI Tx line */
};
};
&duart0 {
status = "okay";
};
@ -169,6 +206,8 @@
#size-cells = <0>;
sgmii_phy0: ethernet-phy@2 {
reg = <0x2>;
interrupt-parent = <&gpio1>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};
};
};
@ -177,6 +216,53 @@
status = "disabled";
};
&enetc_mdio_pf3 {
qsgmii_phy1: ethernet-phy@4 {
reg = <0x10>;
interrupt-parent = <&gpio1>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};
qsgmii_phy2: ethernet-phy@5 {
reg = <0x11>;
interrupt-parent = <&gpio1>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};
qsgmii_phy3: ethernet-phy@6 {
reg = <0x12>;
interrupt-parent = <&gpio1>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};
qsgmii_phy4: ethernet-phy@7 {
reg = <0x13>;
interrupt-parent = <&gpio1>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};
};
/* l2switch ports */
&switch_port0 {
phy-handle = <&qsgmii_phy1>;
phy-connection-type = "qsgmii";
};
&switch_port1 {
phy-handle = <&qsgmii_phy2>;
phy-connection-type = "qsgmii";
};
&switch_port2 {
phy-handle = <&qsgmii_phy3>;
phy-connection-type = "qsgmii";
};
&switch_port3 {
phy-handle = <&qsgmii_phy4>;
phy-connection-type = "qsgmii";
};
&sai4 {
status = "okay";
};
@ -184,3 +270,8 @@
&sata {
status = "okay";
};
&hdptx0 {
lane-mapping = <0x4e>;
status = "okay";
};

225
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View File

@ -2,7 +2,7 @@
/*
* Device Tree Include file for NXP Layerscape-1028A family SoC.
*
* Copyright 2018 NXP
* Copyright 2018-2019 NXP
*
* Harninder Rai <harninder.rai@nxp.com>
*
@ -17,6 +17,10 @@
#address-cells = <2>;
#size-cells = <2>;
aliases {
rtc1 = &ftm_alarm0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -82,24 +86,10 @@
dpclk: clock-controller@f1f0000 {
compatible = "fsl,ls1028a-plldig";
reg = <0x0 0xf1f0000 0x0 0xffff>;
#clock-cells = <1>;
#clock-cells = <0>;
clocks = <&osc_27m>;
};
aclk: clock-axi {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <650000000>;
clock-output-names= "aclk";
};
pclk: clock-apb {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <650000000>;
clock-output-names= "pclk";
};
reboot {
compatible ="syscon-reboot";
regmap = <&dcfg>;
@ -158,7 +148,7 @@
dcfg: syscon@1e00000 {
compatible = "fsl,ls1028a-dcfg", "syscon";
reg = <0x0 0x1e00000 0x0 0x10000>;
big-endian;
little-endian;
};
scfg: syscon@1fc0000 {
@ -174,6 +164,18 @@
clocks = <&sysclk>;
};
fspi: spi@20c0000 {
compatible = "nxp,lx2160a-fspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c0000 0x0 0x10000>,
<0x0 0x20000000 0x0 0x10000000>;
reg-names = "fspi_base", "fspi_mmap";
interrupts = <0 25 0x4>; /* Level high type */
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "fspi_en", "fspi";
};
i2c0: i2c@2000000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
@ -281,6 +283,26 @@
status = "disabled";
};
can0: can@2180000 {
compatible = "fsl,ls1028ar1-flexcan",
"fsl,lx2160ar1-flexcan";
reg = <0x0 0x2180000 0x0 0x10000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysclk>, <&clockgen 4 1>;
clock-names = "ipg", "per";
status = "disabled";
};
can1: can@2190000 {
compatible = "fsl,ls1028ar1-flexcan",
"fsl,lx2160ar1-flexcan";
reg = <0x0 0x2190000 0x0 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysclk>, <&clockgen 4 1>;
clock-names = "ipg", "per";
status = "disabled";
};
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0500 0x0 0x100>;
@ -500,6 +522,16 @@
clock-names = "apb_pclk", "wdog_clk";
};
gpu@f0c0000 {
compatible = "fsl,ls1028a-gpu";
reg = <0x0 0x0f0c0000 0x0 0x10000>,
<0x0 0x80000000 0x0 0x80000000>,
<0x0 0x0 0x0 0x3000000>;
reg-names = "base", "phys_baseaddr",
"contiguous_mem";
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
};
sai1: audio-controller@f100000 {
#sound-dai-cells = <0>;
compatible = "fsl,vf610-sai";
@ -625,12 +657,63 @@
};
};
pcie@3400000 {
compatible = "fsl,ls1028a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x80 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "pme", "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
pcie@3500000 {
compatible = "fsl,ls1028a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x88 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pme", "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
pcie@1f0000000 { /* Integrated Endpoint Root Complex */
compatible = "pci-host-ecam-generic";
reg = <0x01 0xf0000000 0x0 0x100000>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
msi-parent = <&its>;
device_type = "pci";
bus-range = <0x0 0x0>;
@ -648,7 +731,9 @@
/* PF1: VF0-1 BAR0 - non-prefetchable memory */
0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000
/* PF1: VF0-1 BAR2 - prefetchable memory */
0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>;
0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000
/* BAR4 (PF5) - non-prefetchable memory */
0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>;
enetc_port0: ethernet@0,0 {
compatible = "fsl,enetc";
@ -664,12 +749,95 @@
#address-cells = <1>;
#size-cells = <0>;
};
enetc_port2: ethernet@0,2 {
compatible = "fsl,enetc";
reg = <0x000200 0 0 0 0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
ethernet@0,4 {
compatible = "fsl,enetc-ptp";
reg = <0x000400 0 0 0 0>;
clocks = <&clockgen 4 0>;
little-endian;
};
switch@0,5 {
reg = <0x000500 0 0 0 0>;
/* IEP INT_B */
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
/* external ports */
switch_port0: port@0 {
reg = <0>;
};
switch_port1: port@1 {
reg = <1>;
};
switch_port2: port@2 {
reg = <2>;
};
switch_port3: port@3 {
reg = <3>;
};
/* internal to-cpu ports */
port@4 {
reg = <4>;
ethernet = <&enetc_port2>;
phy-mode = "gmii";
fixed-link {
speed = <2500>;
full-duplex;
};
};
port@5 {
reg = <5>;
phy-mode = "gmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
enetc_port3: ethernet@0,6 {
compatible = "fsl,enetc";
reg = <0x000600 0 0 0 0>;
status = "disabled";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
rcpm: rcpm@1e34040 {
compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+";
reg = <0x0 0x1e34040 0x0 0x1c>;
#fsl,rcpm-wakeup-cells = <7>;
little-endian;
};
ftm_alarm0: timer@2800000 {
compatible = "fsl,ls1028a-ftm-alarm";
reg = <0x0 0x2800000 0x0 0x10000>;
fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
};
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
@ -679,14 +847,31 @@
interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
<0 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "DE", "SE";
clocks = <&dpclk 0>, <&aclk>, <&aclk>, <&pclk>;
clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>,
<&clockgen 2 2>;
clock-names = "pxlclk", "mclk", "aclk", "pclk";
arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
arm,malidp-arqos-value = <0xd000d000>;
port {
dp0_out: endpoint {
remote-endpoint = <&dp1_out>;
};
};
};
hdptx0: display@f200000 {
compatible = "cdn,ls1028a-dp";
reg = <0x0 0xf200000 0x0 0xfffff>;
interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 2 2>, <&clockgen 2 2>, <&clockgen 2 2>,
<&clockgen 2 2>, <&clockgen 2 2>, <&dpclk>;
clock-names = "clk_core", "pclk", "sclk",
"cclk", "clk_vif", "clk_pxl";
port {
dp1_out: endpoint {
remote-endpoint = <&dp0_out>;
};
};
};

263
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts 100644
View File

@ -0,0 +1,263 @@
/*
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "fsl-ls1043a-qds.dts"
#include "qoriq-qman-portals-sdk.dtsi"
#include "qoriq-bman-portals-sdk.dtsi"
&bman_fbpr {
compatible = "fsl,bman-fbpr";
alloc-ranges = <0 0 0x10000 0>;
};
&qman_fqd {
compatible = "fsl,qman-fqd";
alloc-ranges = <0 0 0x10000 0>;
};
&qman_pfdr {
compatible = "fsl,qman-pfdr";
alloc-ranges = <0 0 0x10000 0>;
};
&soc {
/delete-property/ dma-coherent;
#include "qoriq-dpaa-eth.dtsi"
#include "qoriq-fman3-0-6oh.dtsi"
pcie@3400000 {
/delete-property/ iommu-map;
dma-coherent;
};
pcie@3500000 {
/delete-property/ iommu-map;
dma-coherent;
};
pcie@3600000 {
/delete-property/ iommu-map;
dma-coherent;
};
/delete-node/ iommu@9000000;
};
&fman0 {
compatible = "fsl,fman", "simple-bus";
dma-coherent;
};
&clockgen {
dma-coherent;
};
&scfg {
dma-coherent;
};
&crypto {
dma-coherent;
};
&dcfg {
dma-coherent;
};
&ifc {
dma-coherent;
};
&qspi {
dma-coherent;
};
&esdhc {
dma-coherent;
};
&ddr {
dma-coherent;
};
&tmu {
dma-coherent;
};
&qman {
dma-coherent;
};
&bman {
dma-coherent;
};
&bportals {
dma-coherent;
};
&qportals {
dma-coherent;
};
&dspi0 {
dma-coherent;
};
&dspi1 {
dma-coherent;
};
&i2c0 {
dma-coherent;
};
&i2c1 {
dma-coherent;
};
&i2c2 {
dma-coherent;
};
&i2c3 {
dma-coherent;
};
&duart0 {
dma-coherent;
};
&duart1 {
dma-coherent;
};
&duart2 {
dma-coherent;
};
&duart3 {
dma-coherent;
};
&gpio1 {
dma-coherent;
};
&gpio2 {
dma-coherent;
};
&gpio3 {
dma-coherent;
};
&gpio4 {
dma-coherent;
};
&uqe {
dma-coherent;
};
&lpuart0 {
dma-coherent;
};
&lpuart1 {
dma-coherent;
};
&lpuart2 {
dma-coherent;
};
&lpuart3 {
dma-coherent;
};
&lpuart4 {
dma-coherent;
};
&lpuart5 {
dma-coherent;
};
&ftm_alarm0 {
dma-coherent;
};
&wdog0 {
dma-coherent;
};
&edma0 {
dma-coherent;
};
&qdma {
dma-coherent;
};
&msi1 {
dma-coherent;
};
&msi2 {
dma-coherent;
};
&msi3 {
dma-coherent;
};
&ptp_timer0 {
dma-coherent;
};
&fsldpaa {
dma-coherent;
};

167
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
View File

@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
* Copyright 2018-2019 NXP
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*/
@ -24,6 +24,22 @@
serial1 = &duart1;
serial2 = &duart2;
serial3 = &duart3;
sgmii-riser-s1-p1 = &sgmii_phy_s1_p1;
sgmii-riser-s2-p1 = &sgmii_phy_s2_p1;
sgmii-riser-s3-p1 = &sgmii_phy_s3_p1;
sgmii-riser-s4-p1 = &sgmii_phy_s4_p1;
qsgmii-s1-p1 = &qsgmii_phy_s1_p1;
qsgmii-s1-p2 = &qsgmii_phy_s1_p2;
qsgmii-s1-p3 = &qsgmii_phy_s1_p3;
qsgmii-s1-p4 = &qsgmii_phy_s1_p4;
qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
emi1-slot1 = &ls1043mdio_s1;
emi1-slot2 = &ls1043mdio_s2;
emi1-slot3 = &ls1043mdio_s3;
emi1-slot4 = &ls1043mdio_s4;
};
chosen {
@ -62,8 +78,11 @@
};
fpga: board-control@2,0 {
compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-bus";
reg = <0x2 0x0 0x0000100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 2 0 0x100>;
};
};
@ -149,3 +168,147 @@
};
#include "fsl-ls1043-post.dtsi"
&fman0 {
ethernet@e0000 {
phy-handle = <&qsgmii_phy_s2_p1>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&qsgmii_phy_s2_p2>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
};
ethernet@e6000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&qsgmii_phy_s2_p3>;
phy-connection-type = "sgmii";
};
ethernet@ea000 {
phy-handle = <&qsgmii_phy_s2_p4>;
phy-connection-type = "sgmii";
};
ethernet@f0000 { /* DTSEC9/10GEC1 */
fixed-link = <1 1 10000 0 0>;
phy-connection-type = "xgmii";
};
};
&fpga {
mdio-mux-emi1 {
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x54 1>; /* BRDCFG4 */
mux-mask = <0xe0>; /* EMI1 */
/* On-board RGMII1 PHY */
ls1043mdio0: mdio@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
rgmii_phy1: ethernet-phy@1 { /* MAC3 */
reg = <0x1>;
};
};
/* On-board RGMII2 PHY */
ls1043mdio1: mdio@1 {
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
rgmii_phy2: ethernet-phy@2 { /* MAC4 */
reg = <0x2>;
};
};
/* Slot 1 */
ls1043mdio_s1: mdio@2 {
reg = <0x40>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
qsgmii_phy_s1_p1: ethernet-phy@4 {
reg = <0x4>;
};
qsgmii_phy_s1_p2: ethernet-phy@5 {
reg = <0x5>;
};
qsgmii_phy_s1_p3: ethernet-phy@6 {
reg = <0x6>;
};
qsgmii_phy_s1_p4: ethernet-phy@7 {
reg = <0x7>;
};
sgmii_phy_s1_p1: ethernet-phy@1c {
reg = <0x1c>;
};
};
/* Slot 2 */
ls1043mdio_s2: mdio@3 {
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
qsgmii_phy_s2_p1: ethernet-phy@8 {
reg = <0x8>;
};
qsgmii_phy_s2_p2: ethernet-phy@9 {
reg = <0x9>;
};
qsgmii_phy_s2_p3: ethernet-phy@a {
reg = <0xa>;
};
qsgmii_phy_s2_p4: ethernet-phy@b {
reg = <0xb>;
};
sgmii_phy_s2_p1: ethernet-phy@1c {
reg = <0x1c>;
};
};
/* Slot 3 */
ls1043mdio_s3: mdio@4 {
reg = <0x80>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sgmii_phy_s3_p1: ethernet-phy@1c {
reg = <0x1c>;
};
};
/* Slot 4 */
ls1043mdio_s4: mdio@5 {
reg = <0xa0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sgmii_phy_s4_p1: ethernet-phy@1c {
reg = <0x1c>;
};
};
};
};

262
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts 100644
View File

@ -0,0 +1,262 @@
/*
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "fsl-ls1043a-rdb.dts"
#include "qoriq-qman-portals-sdk.dtsi"
#include "qoriq-bman-portals-sdk.dtsi"
&bman_fbpr {
compatible = "fsl,bman-fbpr";
alloc-ranges = <0 0 0x10000 0>;
};
&qman_fqd {
compatible = "fsl,qman-fqd";
alloc-ranges = <0 0 0x10000 0>;
};
&qman_pfdr {
compatible = "fsl,qman-pfdr";
alloc-ranges = <0 0 0x10000 0>;
};
&soc {
/delete-property/ dma-coherent;
#include "qoriq-dpaa-eth.dtsi"
#include "qoriq-fman3-0-6oh.dtsi"
pcie@3400000 {
/delete-property/ iommu-map;
dma-coherent;
};
pcie@3500000 {
/delete-property/ iommu-map;
dma-coherent;
};
pcie@3600000 {
/delete-property/ iommu-map;
dma-coherent;
};
/delete-node/ iommu@9000000;
};
&fman0 {
compatible = "fsl,fman", "simple-bus";
};
&clockgen {
dma-coherent;
};
&scfg {
dma-coherent;
};
&crypto {
dma-coherent;
};
&dcfg {
dma-coherent;
};
&ifc {
dma-coherent;
};
&qspi {
dma-coherent;
};
&esdhc {
dma-coherent;
};
&ddr {
dma-coherent;
};
&tmu {
dma-coherent;
};
&qman {
dma-coherent;
};
&bman {
dma-coherent;
};
&bportals {
dma-coherent;
};
&qportals {
dma-coherent;
};
&dspi0 {
dma-coherent;
};
&dspi1 {
dma-coherent;
};
&i2c0 {
dma-coherent;
};
&i2c1 {
dma-coherent;
};
&i2c2 {
dma-coherent;
};
&i2c3 {
dma-coherent;
};
&duart0 {
dma-coherent;
};
&duart1 {
dma-coherent;
};
&duart2 {
dma-coherent;
};
&duart3 {
dma-coherent;
};
&gpio1 {
dma-coherent;
};
&gpio2 {
dma-coherent;
};
&gpio3 {
dma-coherent;
};
&gpio4 {
dma-coherent;
};
&lpuart0 {
dma-coherent;
};
&lpuart1 {
dma-coherent;
};
&lpuart2 {
dma-coherent;
};
&lpuart3 {
dma-coherent;
};
&lpuart4 {
dma-coherent;
};
&lpuart5 {
dma-coherent;
};
&ftm_alarm0 {
dma-coherent;
};
&wdog0 {
dma-coherent;
};
&edma0 {
dma-coherent;
};
&qdma {
dma-coherent;
};
&msi1 {
dma-coherent;
};
&msi2 {
dma-coherent;
};
&msi3 {
dma-coherent;
};
&fman0 {
dma-coherent;
};
&ptp_timer0 {
dma-coherent;
};
&fsldpaa {
dma-coherent;
};

140
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts 100644
View File

@ -0,0 +1,140 @@
/*
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright (C) 2014-2015, Freescale Semiconductor
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include "fsl-ls1043a-rdb-sdk.dts"
&soc {
bp7: buffer-pool@7 {
compatible = "fsl,p4080-bpool", "fsl,bpool";
fsl,bpid = <7>;
fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
dma-coherent;
};
bp8: buffer-pool@8 {
compatible = "fsl,p4080-bpool", "fsl,bpool";
fsl,bpid = <8>;
fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
dma-coherent;
};
bp9: buffer-pool@9 {
compatible = "fsl,p4080-bpool", "fsl,bpool";
fsl,bpid = <9>;
fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
dma-coherent;
};
fsl,dpaa {
compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus";
dma-coherent;
ethernet@0 {
compatible = "fsl,dpa-ethernet-init";
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
fsl,qman-frame-queues-rx = <0x50 1 0x51 1>;
fsl,qman-frame-queues-tx = <0x70 1 0x71 1>;
};
ethernet@1 {
compatible = "fsl,dpa-ethernet-init";
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
};
ethernet@2 {
compatible = "fsl,dpa-ethernet-init";
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
};
ethernet@3 {
compatible = "fsl,dpa-ethernet-init";
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
};
ethernet@4 {
compatible = "fsl,dpa-ethernet-init";
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
};
ethernet@5 {
compatible = "fsl,dpa-ethernet-init";
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
fsl,qman-frame-queues-rx = <0x60 1 0x61 1>;
fsl,qman-frame-queues-tx = <0x80 1 0x81 1>;
};
ethernet@8 {
compatible = "fsl,dpa-ethernet-init";
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
};
dpa-fman0-oh@2 {
compatible = "fsl,dpa-oh";
/* Define frame queues for the OH port*/
/* <OH Rx error, OH Rx default> */
fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>;
fsl,fman-oh-port = <&fman0_oh2>;
};
};
pcie@3400000 {
/delete-property/ iommu-map;
};
pcie@3500000 {
/delete-property/ iommu-map;
};
pcie@3600000 {
/delete-property/ iommu-map;
};
/delete-node/ iommu@9000000;
};
/ {
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* For legacy usdpaa based use-cases, update the size and
alignment parameters. e.g. to allocate 256 MB memory:
size = <0 0x10000000>;
alignment = <0 0x10000000>;
*/
usdpaa_mem: usdpaa_mem {
compatible = "fsl,usdpaa-mem";
alloc-ranges = <0 0 0x10000 0>;
size = <0 0x1000>;
alignment = <0 0x1000>;
};
};
};
&fman0 {
fman0_oh2: port@83000 {
cell-index = <1>;
compatible = "fsl,fman-port-oh";
reg = <0x83000 0x1000>;
};
};

36
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
View File

@ -49,6 +49,10 @@
compatible = "pericom,pt7c4338";
reg = <0x68>;
};
rtc@51 {
compatible = "nxp,pcf85263";
reg = <0x51>;
};
};
&ifc {
@ -94,6 +98,38 @@
reg = <0>;
spi-max-frequency = <1000000>; /* input clock */
};
slic@2 {
compatible = "maxim,ds26522";
reg = <2>;
spi-max-frequency = <2000000>;
fsl,spi-cs-sck-delay = <100>;
fsl,spi-sck-cs-delay = <50>;
};
slic@3 {
compatible = "maxim,ds26522";
reg = <3>;
spi-max-frequency = <2000000>;
fsl,spi-cs-sck-delay = <100>;
fsl,spi-sck-cs-delay = <50>;
};
};
&uqe {
ucc_hdlc: ucc@2000 {
compatible = "fsl,ucc-hdlc";
rx-clock-name = "clk8";
tx-clock-name = "clk9";
fsl,rx-sync-clock = "rsync_pin";
fsl,tx-sync-clock = "tsync_pin";
fsl,tx-timeslot-mask = <0xfffffffe>;
fsl,rx-timeslot-mask = <0xfffffffe>;
fsl,tdm-framer-type = "e1";
fsl,tdm-id = <0>;
fsl,siram-entry-id = <0>;
fsl,tdm-interface;
};
};
&duart0 {

304
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View File

@ -27,6 +27,7 @@
ethernet4 = &enet4;
ethernet5 = &enet5;
ethernet6 = &enet6;
rtc1 = &ftm_alarm0;
};
cpus {
@ -39,7 +40,7 @@
*
* Currently supported enable-method is psci v0.2
*/
cpu0: cpu@0 {
cooling_map0: cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
@ -148,38 +149,7 @@
mask = <0x02>;
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 3>;
trips {
cpu_alert: cpu-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
#include "fsl-tmu.dtsi"
timer {
compatible = "arm,armv8-timer";
@ -218,6 +188,8 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
dma-coherent;
clockgen: clocking@1ee1000 {
compatible = "fsl,ls1043a-clockgen";
@ -226,6 +198,49 @@
clocks = <&sysclk>;
};
smmu: iommu@9000000 {
compatible = "arm,mmu-500";
reg = <0 0x9000000 0 0x400000>;
dma-coherent;
stream-match-mask = <0x7f00>;
#global-interrupts = <2>;
#iommu-cells = <1>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
};
scfg: scfg@1570000 {
compatible = "fsl,ls1043a-scfg", "syscon";
reg = <0x0 0x1570000 0x0 0x10000>;
@ -277,7 +292,7 @@
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1043a-dcfg", "syscon";
reg = <0x0 0x1ee0000 0x0 0x10000>;
reg = <0x0 0x1ee0000 0x0 0x1000>;
big-endian;
};
@ -411,7 +426,7 @@
};
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
compatible = "fsl,vf610-i2c", "fsl,ls1043a-vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
@ -421,6 +436,7 @@
dmas = <&edma0 1 39>,
<&edma0 1 38>;
dma-names = "tx", "rx";
scl-gpios = <&gpio4 12 0>;
status = "disabled";
};
@ -525,6 +541,72 @@
#interrupt-cells = <2>;
};
uqe: uqe@2400000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "qe";
compatible = "fsl,qe", "simple-bus";
ranges = <0x0 0x0 0x2400000 0x40000>;
reg = <0x0 0x2400000 0x0 0x480>;
brg-frequency = <100000000>;
bus-frequency = <200000000>;
fsl,qe-num-riscs = <1>;
fsl,qe-num-snums = <28>;
qeic: qeic@80 {
compatible = "fsl,qe-ic";
reg = <0x80 0x80>;
#address-cells = <0>;
interrupt-controller;
#interrupt-cells = <1>;
interrupts = <0 77 0x04 0 77 0x04>;
};
si1: si@700 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,ls1043-qe-si",
"fsl,t1040-qe-si";
reg = <0x700 0x80>;
};
siram1: siram@1000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,ls1043-qe-siram",
"fsl,t1040-qe-siram";
reg = <0x1000 0x800>;
};
ucc@2000 {
cell-index = <1>;
reg = <0x2000 0x200>;
interrupts = <32>;
interrupt-parent = <&qeic>;
};
ucc@2200 {
cell-index = <3>;
reg = <0x2200 0x200>;
interrupts = <34>;
interrupt-parent = <&qeic>;
};
muram@10000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0x0 0x10000 0x6000>;
data-only@0 {
compatible = "fsl,qe-muram-data",
"fsl,cpm-muram-data";
reg = <0x0 0x6000>;
};
};
};
lpuart0: serial@2950000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2950000 0x0 0x1000>;
@ -604,44 +686,63 @@
<&clockgen 4 0>;
};
usb0: usb3@2f00000 {
compatible = "snps,dwc3";
reg = <0x0 0x2f00000 0x0 0x10000>;
interrupts = <0 60 0x4>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
aux_bus: aux_bus {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
usb1: usb3@3000000 {
compatible = "snps,dwc3";
reg = <0x0 0x3000000 0x0 0x10000>;
interrupts = <0 61 0x4>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
usb0: usb3@2f00000 {
compatible = "snps,dwc3";
reg = <0x0 0x2f00000 0x0 0x10000>;
interrupts = <0 60 0x4>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
snps,host-vbus-glitches;
configure-gfladj;
};
usb2: usb3@3100000 {
compatible = "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <0 63 0x4>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
usb1: usb3@3000000 {
compatible = "snps,dwc3";
reg = <0x0 0x3000000 0x0 0x10000>;
interrupts = <0 61 0x4>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
snps,host-vbus-glitches;
configure-gfladj;
};
sata: sata@3200000 {
compatible = "fsl,ls1043a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>,
<0x0 0x20140520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <0 69 0x4>;
clocks = <&clockgen 4 0>;
dma-coherent;
usb2: usb3@3100000 {
compatible = "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <0 63 0x4>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
snps,host-vbus-glitches;
configure-gfladj;
};
sata: sata@3200000 {
compatible = "fsl,ls1043a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>,
<0x0 0x20140520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <0 69 0x4>;
clocks = <&clockgen 4 0>;
};
};
msi1: msi-controller1@1571000 {
@ -670,13 +771,13 @@
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 118 0x4>, /* controller interrupt */
<0 117 0x4>; /* PME interrupt */
interrupt-names = "intr", "pme";
interrupts = <0 117 0x4>, /* PME interrupt */
<0 118 0x4>; /* aer interrupt */
interrupt-names = "pme", "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
iommu-map = <0 &smmu 0 1>; /* update by bootloader */
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
@ -696,13 +797,13 @@
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x48 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 128 0x4>,
<0 127 0x4>;
interrupt-names = "intr", "pme";
interrupts = <0 127 0x4>,
<0 128 0x4>;
interrupt-names = "pme", "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
iommu-map = <0 &smmu 0 1>; /* update by bootloader */
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
@ -722,13 +823,13 @@
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x50 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 162 0x4>,
<0 161 0x4>;
interrupt-names = "intr", "pme";
interrupts = <0 161 0x4>,
<0 162 0x4>;
interrupt-names = "pme", "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
iommu-map = <0 &smmu 0 1>; /* update by bootloader */
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
@ -764,6 +865,19 @@
big-endian;
};
rcpm: rcpm@1ee2140 {
compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+";
reg = <0x0 0x1ee2140 0x0 0x4>;
#fsl,rcpm-wakeup-cells = <1>;
};
ftm_alarm0: timer@29d0000 {
compatible = "fsl,ls1043a-ftm-alarm";
reg = <0x0 0x29d0000 0x0 0x10000>;
fsl,rcpm-wakeup = <&rcpm 0x20000>;
interrupts = <0 86 0x4>;
big-endian;
};
};
firmware {
@ -777,3 +891,29 @@
#include "qoriq-qman-portals.dtsi"
#include "qoriq-bman-portals.dtsi"
&thermal_zones {
thermal-zone0 {
status = "okay";
};
thermal-zone1 {
status = "okay";
};
thermal-zone2 {
status = "okay";
};
thermal-zone3 {
status = "okay";
};
thermal-zone4 {
status = "okay";
};
thermal-zone5 {
status = "okay";
};
};

241
arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts 100644
View File

@ -0,0 +1,241 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2019 NXP.
*
*/
#include "fsl-ls1046a-frwy.dts"
#include "qoriq-qman-portals-sdk.dtsi"
#include "qoriq-bman-portals-sdk.dtsi"
&bman_fbpr {
compatible = "fsl,bman-fbpr";
alloc-ranges = <0 0 0x10000 0>;
};
&qman_fqd {
compatible = "fsl,qman-fqd";
alloc-ranges = <0 0 0x10000 0>;
};
&qman_pfdr {
compatible = "fsl,qman-pfdr";
alloc-ranges = <0 0 0x10000 0>;
};
&soc {
/delete-property/ dma-coherent;
#include "qoriq-dpaa-eth.dtsi"
#include "qoriq-fman3-0-6oh.dtsi"
pcie@3400000 {
/delete-property/ iommu-map;
};
pcie@3500000 {
/delete-property/ iommu-map;
};
pcie@3600000 {
/delete-property/ iommu-map;
};
/delete-node/ iommu@9000000;
};
&fsldpaa {
ethernet@1 {
status = "disabled";
};
ethernet@2 {
status = "disabled";
};
ethernet@3 {
status = "disabled";
};
ethernet@6 {
status = "disabled";
};
ethernet@9 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet7>;
dma-coherent;
};
};
&fman0 {
compatible = "fsl,fman", "simple-bus";
};
&clockgen {
dma-coherent;
};
&scfg {
dma-coherent;
};
&crypto {
dma-coherent;
};
&dcfg {
dma-coherent;
};
&ifc {
dma-coherent;
};
&qspi {
dma-coherent;
};
&esdhc {
dma-coherent;
};
&ddr {
dma-coherent;
};
&tmu {
dma-coherent;
};
&qman {
dma-coherent;
};
&bman {
dma-coherent;
};
&bportals {
dma-coherent;
};
&qportals {
dma-coherent;
};
&dspi {
dma-coherent;
};
&i2c0 {
dma-coherent;
};
&i2c1 {
dma-coherent;
};
&i2c2 {
dma-coherent;
};
&i2c3 {
dma-coherent;
};
&duart0 {
dma-coherent;
};
&duart1 {
dma-coherent;
};
&duart2 {
dma-coherent;
};
&duart3 {
dma-coherent;
};
&gpio0 {
dma-coherent;
};
&gpio1 {
dma-coherent;
};
&gpio2 {
dma-coherent;
};
&gpio3 {
dma-coherent;
};
&lpuart0 {
dma-coherent;
};
&lpuart1 {
dma-coherent;
};
&lpuart2 {
dma-coherent;
};
&lpuart3 {
dma-coherent;
};
&lpuart4 {
dma-coherent;
};
&lpuart5 {
dma-coherent;
};
&ftm_alarm0 {
dma-coherent;
};
&wdog0 {
dma-coherent;
};
&edma0 {
dma-coherent;
};
&sata {
dma-coherent;
};
&qdma {
dma-coherent;
};
&msi1 {
dma-coherent;
};
&msi2 {
dma-coherent;
};
&msi3 {
dma-coherent;
};
&fman0 {
dma-coherent;
};
&ptp_timer0 {
dma-coherent;
};
&fsldpaa {
dma-coherent;
};

117
arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts 100644
View File

@ -0,0 +1,117 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2019 NXP.
*
*/
#include "fsl-ls1046a-frwy-sdk.dts"
&soc {
bp7: buffer-pool@7 {
compatible = "fsl,ls1046a-bpool", "fsl,bpool";
fsl,bpid = <7>;
fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
dma-coherent;
};
bp8: buffer-pool@8 {
compatible = "fsl,ls1046a-bpool", "fsl,bpool";
fsl,bpid = <8>;
fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
dma-coherent;
};
bp9: buffer-pool@9 {
compatible = "fsl,ls1046a-bpool", "fsl,bpool";
fsl,bpid = <9>;
fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
dma-coherent;
};
fsl,dpaa {
compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus";
dma-coherent;
ethernet@0 {
compatible = "fsl,dpa-ethernet-init";
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
fsl,qman-frame-queues-rx = <0x50 1 0x51 1>;
fsl,qman-frame-queues-tx = <0x70 1 0x71 1>;
};
ethernet@4 {
compatible = "fsl,dpa-ethernet-init";
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
};
ethernet@5 {
compatible = "fsl,dpa-ethernet-init";
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
};
ethernet@9 {
compatible = "fsl,dpa-ethernet-init";
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
};
dpa-fman0-oh@2 {
compatible = "fsl,dpa-oh";
/* Define frame queues for the OH port*/
/* <OH Rx error, OH Rx default> */
fsl,qman-frame-queues-oh = <0x60 1 0x61 1>;
fsl,fman-oh-port = <&fman0_oh2>;
};
};
pcie@3400000 {
/delete-property/ iommu-map;
};
pcie@3500000 {
/delete-property/ iommu-map;
};
pcie@3600000 {
/delete-property/ iommu-map;
};
/delete-node/ iommu@9000000;
};
/ {
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* For legacy usdpaa based use-cases, update the size and
alignment parameters. e.g. to allocate 256 MB memory:
size = <0 0x10000000>;
alignment = <0 0x10000000>;
*/
usdpaa_mem: usdpaa_mem {
compatible = "fsl,usdpaa-mem";
alloc-ranges = <0 0 0x10000 0>;
size = <0 0x1000>;
alignment = <0 0x1000>;
};
};
};
&fman0 {
fman0_oh2: port@83000 {
cell-index = <1>;
compatible = "fsl,fman-port-oh";
reg = <0x83000 0x1000>;
};
};

17
arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts
View File

@ -112,6 +112,23 @@
};
&qspi {
num-cs = <1>;
bus-num = <0>;
status = "okay";
qflash0: flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
};
#include "fsl-ls1046-post.dtsi"
&fman0 {

264
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts 100644
View File

@ -0,0 +1,264 @@
/*
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "fsl-ls1046a-qds.dts"
#include "qoriq-qman-portals-sdk.dtsi"
#include "qoriq-bman-portals-sdk.dtsi"
&bman_fbpr {
compatible = "fsl,bman-fbpr";
alloc-ranges = <0 0 0x10000 0>;
};
&qman_fqd {
compatible = "fsl,qman-fqd";
alloc-ranges = <0 0 0x10000 0>;
};
&qman_pfdr {
compatible = "fsl,qman-pfdr";
alloc-ranges = <0 0 0x10000 0>;
};
&soc {
/delete-property/ dma-coherent;
#include "qoriq-dpaa-eth.dtsi"
#include "qoriq-fman3-0-6oh.dtsi"
pcie@3400000 {
/delete-property/ iommu-map;
};
pcie@3500000 {
/delete-property/ iommu-map;
};
pcie@3600000 {
/delete-property/ iommu-map;
};
/delete-node/ iommu@9000000;
};
&fsldpaa {
ethernet@9 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet7>;
dma-coherent;
};
};
&fman0 {
compatible = "fsl,fman", "simple-bus";
dma-coherent;
};
&clockgen {
dma-coherent;
};
&scfg {
dma-coherent;
};
&crypto {
dma-coherent;
};
&dcfg {
dma-coherent;
};
&ifc {
dma-coherent;
};
&qspi {
dma-coherent;
};
&esdhc {
dma-coherent;
};
&ddr {
dma-coherent;
};
&tmu {
dma-coherent;
};
&qman {
dma-coherent;
};
&bman {
dma-coherent;
};
&bportals {
dma-coherent;
};
&qportals {
dma-coherent;
};
&dspi {
dma-coherent;
};
&i2c0 {
dma-coherent;
};
&i2c1 {
dma-coherent;
};
&i2c2 {
dma-coherent;
};
&i2c3 {
dma-coherent;
};
&duart0 {
dma-coherent;
};
&duart1 {
dma-coherent;
};
&duart2 {
dma-coherent;
};
&duart3 {
dma-coherent;
};
&gpio0 {
dma-coherent;
};
&gpio1 {
dma-coherent;
};
&gpio2 {
dma-coherent;
};
&gpio3 {
dma-coherent;
};
&lpuart0 {
dma-coherent;
};
&lpuart1 {
dma-coherent;
};
&lpuart2 {
dma-coherent;
};
&lpuart3 {
dma-coherent;
};
&lpuart4 {
dma-coherent;
};
&lpuart5 {
dma-coherent;
};
&ftm_alarm0 {
dma-coherent;
};
&wdog0 {
dma-coherent;
};
&edma0 {
dma-coherent;
};
&sata {
dma-coherent;
};
&qdma {
dma-coherent;
};
&msi1 {
dma-coherent;
};
&msi2 {
dma-coherent;
};
&msi3 {
dma-coherent;
};
&ptp_timer0 {
dma-coherent;
};
&fsldpaa {
dma-coherent;
};

155
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
View File

@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
* Copyright 2018-2019 NXP
*
* Shaohui Xie <Shaohui.Xie@nxp.com>
*/
@ -25,6 +25,20 @@
serial1 = &duart1;
serial2 = &duart2;
serial3 = &duart3;
emi1-slot1 = &ls1046mdio_s1;
emi1-slot2 = &ls1046mdio_s2;
emi1-slot4 = &ls1046mdio_s4;
sgmii-s1-p1 = &sgmii_phy_s1_p1;
sgmii-s1-p2 = &sgmii_phy_s1_p2;
sgmii-s1-p3 = &sgmii_phy_s1_p3;
sgmii-s1-p4 = &sgmii_phy_s1_p4;
sgmii-s4-p1 = &sgmii_phy_s4_p1;
qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
};
chosen {
@ -153,8 +167,9 @@
};
fpga: board-control@2,0 {
compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis";
compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-bus";
reg = <0x2 0x0 0x0000100>;
ranges = <0 2 0 0x100>;
};
};
@ -169,7 +184,7 @@
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
reg = <0>;
@ -177,3 +192,137 @@
};
#include "fsl-ls1046-post.dtsi"
&fman0 {
ethernet@e0000 {
phy-handle = <&qsgmii_phy_s2_p1>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&sgmii_phy_s4_p1>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
};
ethernet@e6000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&sgmii_phy_s1_p3>;
phy-connection-type = "sgmii";
};
ethernet@ea000 {
phy-handle = <&sgmii_phy_s1_p4>;
phy-connection-type = "sgmii";
};
ethernet@f0000 { /* DTSEC9/10GEC1 */
phy-handle = <&sgmii_phy_s1_p1>;
phy-connection-type = "xgmii";
};
ethernet@f2000 { /* DTSEC10/10GEC2 */
phy-handle = <&sgmii_phy_s1_p2>;
phy-connection-type = "xgmii";
};
};
&fpga {
#address-cells = <1>;
#size-cells = <1>;
mdio-mux-emi1 {
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x54 1>; /* BRDCFG4 */
mux-mask = <0xe0>; /* EMI1 */
/* On-board RGMII1 PHY */
ls1046mdio0: mdio@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
rgmii_phy1: ethernet-phy@1 { /* MAC3 */
reg = <0x1>;
};
};
/* On-board RGMII2 PHY */
ls1046mdio1: mdio@1 {
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
rgmii_phy2: ethernet-phy@2 { /* MAC4 */
reg = <0x2>;
};
};
/* Slot 1 */
ls1046mdio_s1: mdio@2 {
reg = <0x40>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sgmii_phy_s1_p1: ethernet-phy@1c {
reg = <0x1c>;
};
sgmii_phy_s1_p2: ethernet-phy@1d {
reg = <0x1d>;
};
sgmii_phy_s1_p3: ethernet-phy@1e {
reg = <0x1e>;
};
sgmii_phy_s1_p4: ethernet-phy@1f {
reg = <0x1f>;
};
};
/* Slot 2 */
ls1046mdio_s2: mdio@3 {
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
qsgmii_phy_s2_p1: ethernet-phy@8 {
reg = <0x8>;
};
qsgmii_phy_s2_p2: ethernet-phy@9 {
reg = <0x9>;
};
qsgmii_phy_s2_p3: ethernet-phy@a {
reg = <0xa>;
};
qsgmii_phy_s2_p4: ethernet-phy@b {
reg = <0xb>;
};
};
/* Slot 4 */
ls1046mdio_s4: mdio@5 {
reg = <0x80>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sgmii_phy_s4_p1: ethernet-phy@1c {
reg = <0x1c>;
};
};
};
};

273
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts 100644
View File

@ -0,0 +1,273 @@
/*
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "fsl-ls1046a-rdb.dts"
#include "qoriq-qman-portals-sdk.dtsi"
#include "qoriq-bman-portals-sdk.dtsi"
&bman_fbpr {
compatible = "fsl,bman-fbpr";
alloc-ranges = <0 0 0x10000 0>;
};
&qman_fqd {
compatible = "fsl,qman-fqd";
alloc-ranges = <0 0 0x10000 0>;
};
&qman_pfdr {
compatible = "fsl,qman-pfdr";
alloc-ranges = <0 0 0x10000 0>;
};
&soc {
/delete-property/ dma-coherent;
#include "qoriq-dpaa-eth.dtsi"
#include "qoriq-fman3-0-6oh.dtsi"
pcie@3400000 {
/delete-property/ iommu-map;
};
pcie@3500000 {
/delete-property/ iommu-map;
};
pcie@3600000 {
/delete-property/ iommu-map;
};
/delete-node/ iommu@9000000;
};
&fsldpaa {
ethernet@0 {
status = "disabled";
};
ethernet@1 {
status = "disabled";
};
ethernet@9 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet7>;
dma-coherent;
};
};
&fman0 {
compatible = "fsl,fman", "simple-bus";
};
&clockgen {
dma-coherent;
};
&scfg {
dma-coherent;
};
&crypto {
dma-coherent;
};
&dcfg {
dma-coherent;
};
&ifc {
dma-coherent;
};
&qspi {
dma-coherent;
};
&esdhc {
dma-coherent;
};
&ddr {
dma-coherent;
};
&tmu {
dma-coherent;
};
&qman {
dma-coherent;
};
&bman {
dma-coherent;
};
&bportals {
dma-coherent;
};
&qportals {
dma-coherent;
};
&dspi {
dma-coherent;
};
&i2c0 {
dma-coherent;
};
&i2c1 {
dma-coherent;
};
&i2c2 {
dma-coherent;
};
&i2c3 {
dma-coherent;
};
&duart0 {
dma-coherent;
};
&duart1 {
dma-coherent;
};
&duart2 {
dma-coherent;
};
&duart3 {
dma-coherent;
};
&gpio0 {
dma-coherent;
};
&gpio1 {
dma-coherent;
};
&gpio2 {
dma-coherent;
};
&gpio3 {
dma-coherent;
};
&lpuart0 {
dma-coherent;
};
&lpuart1 {
dma-coherent;
};
&lpuart2 {
dma-coherent;
};
&lpuart3 {
dma-coherent;
};
&lpuart4 {
dma-coherent;
};
&lpuart5 {
dma-coherent;
};
&ftm_alarm0 {
dma-coherent;
};
&wdog0 {
dma-coherent;
};
&edma0 {
dma-coherent;
};
&sata {
dma-coherent;
};
&qdma {
dma-coherent;
};
&msi1 {
dma-coherent;
};
&msi2 {
dma-coherent;
};
&msi3 {
dma-coherent;
};
&fman0 {
dma-coherent;
};
&ptp_timer0 {
dma-coherent;
};
&fsldpaa {
dma-coherent;
};

133
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts 100644
View File

@ -0,0 +1,133 @@
/*
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright (C) 2016, Freescale Semiconductor
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include "fsl-ls1046a-rdb-sdk.dts"
&soc {
bp7: buffer-pool@7 {
compatible = "fsl,ls1046a-bpool", "fsl,bpool";
fsl,bpid = <7>;
fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
dma-coherent;
};
bp8: buffer-pool@8 {
compatible = "fsl,ls1046a-bpool", "fsl,bpool";
fsl,bpid = <8>;
fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
dma-coherent;
};
bp9: buffer-pool@9 {
compatible = "fsl,ls1046a-bpool", "fsl,bpool";
fsl,bpid = <9>;
fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
dma-coherent;
};
fsl,dpaa {
compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus";
dma-coherent;
ethernet@2 {
compatible = "fsl,dpa-ethernet-init";
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
};
ethernet@3 {
compatible = "fsl,dpa-ethernet-init";
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
};
ethernet@4 {
compatible = "fsl,dpa-ethernet-init";
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
};
ethernet@5 {
compatible = "fsl,dpa-ethernet-init";
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>;
fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>;
};
ethernet@8 {
compatible = "fsl,dpa-ethernet-init";
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
};
ethernet@9 {
compatible = "fsl,dpa-ethernet-init";
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>;
fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>;
};
dpa-fman0-oh@2 {
compatible = "fsl,dpa-oh";
/* Define frame queues for the OH port*/
/* <OH Rx error, OH Rx default> */
fsl,qman-frame-queues-oh = <0x60 1 0x61 1>;
fsl,fman-oh-port = <&fman0_oh2>;
};
};
pcie@3400000 {
/delete-property/ iommu-map;
};
pcie@3500000 {
/delete-property/ iommu-map;
};
pcie@3600000 {
/delete-property/ iommu-map;
};
/delete-node/ iommu@9000000;
};
/ {
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* For legacy usdpaa based use-cases, update the size and
alignment parameters. e.g. to allocate 256 MB memory:
size = <0 0x10000000>;
alignment = <0 0x10000000>;
*/
usdpaa_mem: usdpaa_mem {
compatible = "fsl,usdpaa-mem";
alloc-ranges = <0 0 0x10000 0>;
size = <0 0x1000>;
alignment = <0 0x1000>;
};
};
};
&fman0 {
fman0_oh2: port@83000 {
cell-index = <1>;
compatible = "fsl,fman-port-oh";
reg = <0x83000 0x1000>;
};
};

10
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
View File

@ -3,6 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
*
* Mingkai Hu <mingkai.hu@nxp.com>
*/
@ -43,6 +44,10 @@
sd-uhs-sdr12;
};
&usb1 {
dr_mode = "otg";
};
&i2c0 {
status = "okay";
@ -100,12 +105,13 @@
&qspi {
status = "okay";
fsl,qspi-has-second-chip;
qflash0: flash@0 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
reg = <0>;
@ -115,7 +121,7 @@
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
reg = <1>;

213
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View File

@ -28,13 +28,14 @@
ethernet5 = &enet5;
ethernet6 = &enet6;
ethernet7 = &enet7;
rtc1 = &ftm_alarm0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
cooling_map0: cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0>;
@ -116,38 +117,7 @@
mask = <0x02>;
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 3>;
trips {
cpu_alert: cpu-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
#include "fsl-tmu.dtsi"
timer {
compatible = "arm,armv8-timer";
@ -190,6 +160,8 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
dma-coherent;
ddr: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
@ -229,6 +201,49 @@
bus-width = <4>;
};
smmu: iommu@9000000 {
compatible = "arm,mmu-500";
reg = <0 0x9000000 0 0x400000>;
dma-coherent;
stream-match-mask = <0x7f00>;
#global-interrupts = <2>;
#iommu-cells = <1>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
};
scfg: scfg@1570000 {
compatible = "fsl,ls1046a-scfg", "syscon";
reg = <0x0 0x1570000 0x0 0x10000>;
@ -304,7 +319,7 @@
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1046a-dcfg", "syscon";
reg = <0x0 0x1ee0000 0x0 0x10000>;
reg = <0x0 0x1ee0000 0x0 0x1000>;
big-endian;
};
@ -376,7 +391,7 @@
};
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
@ -385,6 +400,7 @@
dmas = <&edma0 1 39>,
<&edma0 1 38>;
dma-names = "tx", "rx";
scl-gpios = <&gpio3 12 0>;
status = "disabled";
};
@ -409,12 +425,13 @@
};
i2c3: i2c@21b0000 {
compatible = "fsl,vf610-i2c";
compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21b0000 0x0 0x10000>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
scl-gpios = <&gpio3 12 0>;
status = "disabled";
};
@ -568,43 +585,60 @@
<&clockgen 4 1>;
};
usb0: usb@2f00000 {
compatible = "snps,dwc3";
reg = <0x0 0x2f00000 0x0 0x10000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
aux_bus: aux_bus {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
usb1: usb@3000000 {
compatible = "snps,dwc3";
reg = <0x0 0x3000000 0x0 0x10000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
usb0: usb@2f00000 {
compatible = "snps,dwc3";
reg = <0x0 0x2f00000 0x0 0x10000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
snps,host-vbus-glitches;
};
usb2: usb@3100000 {
compatible = "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
usb1: usb@3000000 {
compatible = "snps,dwc3";
reg = <0x0 0x3000000 0x0 0x10000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
snps,host-vbus-glitches;
};
sata: sata@3200000 {
compatible = "fsl,ls1046a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>,
<0x0 0x20140520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
usb2: usb@3100000 {
compatible = "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
snps,host-vbus-glitches;
};
sata: sata@3200000 {
compatible = "fsl,ls1046a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>,
<0x0 0x20140520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
};
};
msi1: msi-controller@1580000 {
@ -649,6 +683,7 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
iommu-map = <0 &smmu 0 1>; /* update by bootloader */
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
@ -685,6 +720,7 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
iommu-map = <0 &smmu 0 1>; /* update by bootloader */
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
@ -721,6 +757,7 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
iommu-map = <0 &smmu 0 1>; /* update by bootloader */
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
@ -765,6 +802,20 @@
queue-sizes = <64 64>;
big-endian;
};
rcpm: rcpm@1ee208c {
compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+";
reg = <0x0 0x1ee208c 0x0 0x4>;
#fsl,rcpm-wakeup-cells = <1>;
};
ftm_alarm0: timer@29d0000 {
compatible = "fsl,ls1046a-ftm-alarm";
reg = <0x0 0x29d0000 0x0 0x10000>;
fsl,rcpm-wakeup = <&rcpm 0x20000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
big-endian;
};
};
reserved-memory {
@ -804,3 +855,25 @@
#include "qoriq-qman-portals.dtsi"
#include "qoriq-bman-portals.dtsi"
&thermal_zones {
thermal-zone0 {
status = "okay";
};
thermal-zone1 {
status = "okay";
};
thermal-zone2 {
status = "okay";
};
thermal-zone3 {
status = "okay";
};
thermal-zone4 {
status = "okay";
};
};

24
arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
View File

@ -131,6 +131,30 @@
};
};
&qspi {
status = "okay";
fsl,qspi-has-second-chip;
qflash0: s25fs512s@0 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
reg = <0>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
qflash1: s25fs512s@1 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
reg = <1>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
};
&duart0 {
status = "okay";
};

105
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
View File

@ -74,6 +74,31 @@
};
};
&qspi {
status = "okay";
fsl,qspi-has-second-chip;
qflash0: s25fs512s@0 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
reg = <0>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
qflash1: s25fs512s@1 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
reg = <1>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
};
&duart0 {
status = "okay";
};
@ -95,5 +120,85 @@
};
&usb1 {
dr_mode = "otg";
status = "okay";
};
&emdio1 {
/* Freescale F104 PHY1 */
mdio1_phy1: emdio1_phy@1 {
reg = <0x1c>;
phy-connection-type = "qsgmii";
};
mdio1_phy2: emdio1_phy@2 {
reg = <0x1d>;
phy-connection-type = "qsgmii";
};
mdio1_phy3: emdio1_phy@3 {
reg = <0x1e>;
phy-connection-type = "qsgmii";
};
mdio1_phy4: emdio1_phy@4 {
reg = <0x1f>;
phy-connection-type = "qsgmii";
};
/* F104 PHY2 */
mdio1_phy5: emdio1_phy@5 {
reg = <0x0c>;
phy-connection-type = "qsgmii";
};
mdio1_phy6: emdio1_phy@6 {
reg = <0x0d>;
phy-connection-type = "qsgmii";
};
mdio1_phy7: emdio1_phy@7 {
reg = <0x0e>;
phy-connection-type = "qsgmii";
};
mdio1_phy8: emdio1_phy@8 {
reg = <0x0f>;
phy-connection-type = "qsgmii";
};
};
&emdio2 {
/* Aquantia AQR105 10G PHY */
mdio2_phy1: emdio2_phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
interrupts = <0 2 0x4>;
reg = <0x0>;
phy-connection-type = "xfi";
};
};
/* DPMAC connections to external PHYs
* based on LS1088A RM RevC - $24.1.2 SerDes Options
*/
/* DPMAC1 is 10G SFP+, fixed link */
&dpmac2 {
phy-handle = <&mdio2_phy1>;
};
&dpmac3 {
phy-handle = <&mdio1_phy5>;
};
&dpmac4 {
phy-handle = <&mdio1_phy6>;
};
&dpmac5 {
phy-handle = <&mdio1_phy7>;
};
&dpmac6 {
phy-handle = <&mdio1_phy8>;
};
&dpmac7 {
phy-handle = <&mdio1_phy1>;
};
&dpmac8 {
phy-handle = <&mdio1_phy2>;
};
&dpmac9 {
phy-handle = <&mdio1_phy3>;
};
&dpmac10 {
phy-handle = <&mdio1_phy4>;
};

129
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
View File

@ -2,7 +2,7 @@
/*
* Device Tree Include file for NXP Layerscape-1088A family SoC.
*
* Copyright 2017 NXP
* Copyright 2017-2019 NXP
*
* Harninder Rai <harninder.rai@nxp.com>
*
@ -18,6 +18,7 @@
aliases {
crypto = &crypto;
rtc1 = &ftm_alarm0;
};
cpus {
@ -25,7 +26,7 @@
#size-cells = <0>;
/* We have 2 clusters having 4 Cortex-A53 cores each */
cpu0: cpu@0 {
cooling_map0: cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
@ -61,7 +62,7 @@
#cooling-cells = <2>;
};
cpu4: cpu@100 {
cooling_map1: cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x100>;
@ -128,42 +129,7 @@
};
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 0>;
trips {
cpu_alert: cpu-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
#include "fsl-tmu.dtsi"
timer {
compatible = "arm,armv8-timer";
@ -185,6 +151,19 @@
clock-output-names = "sysclk";
};
rstcr: syscon@1e60000 {
compatible = "fsl,ls1088a-rstcr", "syscon";
reg = <0x0 0x1e60000 0x0 0x4>;
};
reboot {
compatible = "syscon-reboot";
regmap = <&rstcr>;
offset = <0x0>;
mask = <0x02>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
@ -325,6 +304,32 @@
#interrupt-cells = <2>;
};
/* TODO: WRIOP (CCSR?) */
emdio1: mdio@8B96000 { /* WRIOP0: 0x8B8_0000,
* E-MDIO1: 0x1_6000
*/
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8B96000 0x0 0x1000>;
device_type = "mdio";
little-endian; /* force the driver in LE mode */
/* Not necessary on the QDS, but needed on the RDB */
#address-cells = <1>;
#size-cells = <0>;
};
emdio2: mdio@8B97000 { /* WRIOP0: 0x8B8_0000,
* E-MDIO2: 0x1_7000
*/
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8B97000 0x0 0x1000>;
device_type = "mdio";
little-endian; /* force the driver in LE mode */
#address-cells = <1>;
#size-cells = <0>;
};
ifc: ifc@2240000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x2240000 0x0 0x20000>;
@ -336,12 +341,13 @@
};
i2c0: i2c@2000000 {
compatible = "fsl,vf610-i2c";
compatible = "fsl,vf610-i2c", "fsl,ls1088a-vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 7>;
scl-gpios = <&gpio3 30 0>;
status = "disabled";
};
@ -395,6 +401,7 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
snps,host-vbus-glitches;
status = "disabled";
};
@ -405,6 +412,8 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
snps,host-vbus-glitches;
status = "disabled";
};
@ -418,6 +427,17 @@
dma-coherent;
status = "disabled";
};
qspi: spi@20c0000 {
compatible = "fsl,ls2080a-qspi", "fsl,ls1088a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c0000 0x0 0x10000>,
<0x0 0x20000000 0x0 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <0 25 0x4>; /* Level high type */
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "qspi_en", "qspi";
};
crypto: crypto@8000000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
@ -474,6 +494,7 @@
ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
@ -499,6 +520,7 @@
ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
@ -524,6 +546,7 @@
ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
@ -764,6 +787,20 @@
};
};
};
rcpm: rcpm@1e34040 {
compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
reg = <0x0 0x1e34040 0x0 0x18>;
#fsl,rcpm-wakeup-cells = <6>;
little-endian;
};
ftm_alarm0: timer@2800000 {
compatible = "fsl,ls1088a-ftm-alarm";
reg = <0x0 0x2800000 0x0 0x10000>;
fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
interrupts = <0 44 4>;
};
};
firmware {
@ -773,3 +810,15 @@
};
};
};
#include "fsl-tmu-map1.dtsi"
&thermal_zones {
thermal-zone0 {
status = "okay";
};
thermal-zone1 {
status = "okay";
};
};

62
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
View File

@ -23,3 +23,65 @@
stdout-path = "serial0:115200n8";
};
};
&ifc {
boardctrl: board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
reg = <3 0 0x300>; /* TODO check address */
ranges = <0 3 0 0x300>;
mdio_mux_emi1 {
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&emdio1>;
reg = <0x54 1>; /* BRDCFG4 */
mux-mask = <0xe0>; /* EMI1_MDIO */
#address-cells=<1>;
#size-cells = <0>;
/* Child MDIO buses, one for each riser card:
* reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
* VSC8234 PHYs on the riser cards.
*/
mdio_mux3: mdio@60 {
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
mdio0_phy12: mdio_phy0@1c {
reg = <0x1c>;
phy-connection-type = "sgmii";
};
mdio0_phy13: mdio_phy1@1d {
reg = <0x1d>;
phy-connection-type = "sgmii";
};
mdio0_phy14: mdio_phy2@1e {
reg = <0x1e>;
phy-connection-type = "sgmii";
};
mdio0_phy15: mdio_phy3@1f {
reg = <0x1f>;
phy-connection-type = "sgmii";
};
};
};
};
};
/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
&dpmac9 {
phy-handle = <&mdio0_phy12>;
};
&dpmac10 {
phy-handle = <&mdio0_phy13>;
};
&dpmac11 {
phy-handle = <&mdio0_phy14>;
};
&dpmac12 {
phy-handle = <&mdio0_phy15>;
};

80
arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
View File

@ -23,3 +23,83 @@
stdout-path = "serial1:115200n8";
};
};
&emdio1 {
status = "disabled";
/* CS4340 PHYs */
mdio1_phy1: emdio1_phy@1 {
reg = <0x10>;
phy-connection-type = "xfi";
};
mdio1_phy2: emdio1_phy@2 {
reg = <0x11>;
phy-connection-type = "xfi";
};
mdio1_phy3: emdio1_phy@3 {
reg = <0x12>;
phy-connection-type = "xfi";
};
mdio1_phy4: emdio1_phy@4 {
reg = <0x13>;
phy-connection-type = "xfi";
};
};
&emdio2 {
/* AQR405 PHYs */
mdio2_phy1: emdio2_phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
interrupts = <0 1 0x4>; /* Level high type */
reg = <0x0>;
phy-connection-type = "xfi";
};
mdio2_phy2: emdio2_phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
interrupts = <0 2 0x4>; /* Level high type */
reg = <0x1>;
phy-connection-type = "xfi";
};
mdio2_phy3: emdio2_phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
interrupts = <0 4 0x4>; /* Level high type */
reg = <0x2>;
phy-connection-type = "xfi";
};
mdio2_phy4: emdio2_phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
interrupts = <0 5 0x4>; /* Level high type */
reg = <0x3>;
phy-connection-type = "xfi";
};
};
/* Update DPMAC connections to external PHYs, under the assumption of
* SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
*/
/* Leave Cortina nodes commented out until driver is integrated
*&dpmac1 {
* phy-handle = <&mdio1_phy1>;
*};
*&dpmac2 {
* phy-handle = <&mdio1_phy2>;
*};
*&dpmac3 {
* phy-handle = <&mdio1_phy3>;
*};
*&dpmac4 {
* phy-handle = <&mdio1_phy4>;
*};
*/
&dpmac5 {
phy-handle = <&mdio2_phy1>;
};
&dpmac6 {
phy-handle = <&mdio2_phy2>;
};
&dpmac7 {
phy-handle = <&mdio2_phy3>;
};
&dpmac8 {
phy-handle = <&mdio2_phy4>;
};

20
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
View File

@ -12,7 +12,7 @@
#include "fsl-ls208xa.dtsi"
&cpu {
cpu0: cpu@0 {
cooling_map0: cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0>;
@ -32,7 +32,7 @@
#cooling-cells = <2>;
};
cpu2: cpu@100 {
cooling_map1: cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x100>;
@ -52,7 +52,7 @@
#cooling-cells = <2>;
};
cpu4: cpu@200 {
cooling_map2: cpu4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x200>;
@ -72,7 +72,7 @@
#cooling-cells = <2>;
};
cpu6: cpu@300 {
cooling_map3: cpu6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x300>;
@ -118,6 +118,18 @@
};
};
&timer {
fsl,erratum-a008585;
};
&usb0 {
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
&usb1 {
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
&pcie1 {
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x10 0x00000000 0x0 0x00002000>; /* configuration space */

127
arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts 100644
View File

@ -0,0 +1,127 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for NXP LS2081A RDB Board.
*
* Copyright 2017 NXP
*
* Priyanka Jain <priyanka.jain@nxp.com>
*
*/
/dts-v1/;
#include "fsl-ls2088a.dtsi"
/ {
model = "NXP Layerscape 2081A RDB Board";
compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
aliases {
serial0 = &serial0;
serial1 = &serial1;
};
chosen {
stdout-path = "serial1:115200n8";
};
};
&esdhc {
status = "okay";
};
&ifc {
status = "disabled";
};
&i2c0 {
status = "okay";
pca9547@75 {
compatible = "nxp,pca9547";
reg = <0x75>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x01>;
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x02>;
ina220@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <500>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
adt7481@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
};
};
};
&dspi {
status = "okay";
dflash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <3000000>;
reg = <0>;
};
};
&qspi {
status = "okay";
fsl,qspi-has-second-chip;
flash0: s25fs512s@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,m25p80";
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
spi-max-frequency = <20000000>;
reg = <0>;
};
flash1: s25fs512s@1 {
#address-cells = <1>;
#size-cells = <1>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
compatible = "spansion,m25p80";
spi-max-frequency = <20000000>;
reg = <1>;
};
};
&sata0 {
status = "okay";
};
&sata1 {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};

62
arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
View File

@ -22,3 +22,65 @@
stdout-path = "serial0:115200n8";
};
};
&ifc {
boardctrl: board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
reg = <3 0 0x300>; /* TODO check address */
ranges = <0 3 0 0x300>;
mdio_mux_emi1 {
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&emdio1>;
reg = <0x54 1>; /* BRDCFG4 */
mux-mask = <0xe0>; /* EMI1_MDIO */
#address-cells=<1>;
#size-cells = <0>;
/* Child MDIO buses, one for each riser card:
* reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
* VSC8234 PHYs on the riser cards.
*/
mdio_mux3: mdio@60 {
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
mdio0_phy12: mdio_phy0@1c {
reg = <0x1c>;
phy-connection-type = "sgmii";
};
mdio0_phy13: mdio_phy1@1d {
reg = <0x1d>;
phy-connection-type = "sgmii";
};
mdio0_phy14: mdio_phy2@1e {
reg = <0x1e>;
phy-connection-type = "sgmii";
};
mdio0_phy15: mdio_phy3@1f {
reg = <0x1f>;
phy-connection-type = "sgmii";
};
};
};
};
};
/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
&dpmac9 {
phy-handle = <&mdio0_phy12>;
};
&dpmac10 {
phy-handle = <&mdio0_phy13>;
};
&dpmac11 {
phy-handle = <&mdio0_phy14>;
};
&dpmac12 {
phy-handle = <&mdio0_phy15>;
};

80
arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
View File

@ -22,3 +22,83 @@
stdout-path = "serial1:115200n8";
};
};
&emdio1 {
status = "disabled";
/* CS4340 PHYs */
mdio1_phy1: emdio1_phy@1 {
reg = <0x10>;
phy-connection-type = "xfi";
};
mdio1_phy2: emdio1_phy@2 {
reg = <0x11>;
phy-connection-type = "xfi";
};
mdio1_phy3: emdio1_phy@3 {
reg = <0x12>;
phy-connection-type = "xfi";
};
mdio1_phy4: emdio1_phy@4 {
reg = <0x13>;
phy-connection-type = "xfi";
};
};
&emdio2 {
/* AQR405 PHYs */
mdio2_phy1: emdio2_phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
interrupts = <0 1 0x4>; /* Level high type */
reg = <0x0>;
phy-connection-type = "xfi";
};
mdio2_phy2: emdio2_phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
interrupts = <0 2 0x4>; /* Level high type */
reg = <0x1>;
phy-connection-type = "xfi";
};
mdio2_phy3: emdio2_phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
interrupts = <0 4 0x4>; /* Level high type */
reg = <0x2>;
phy-connection-type = "xfi";
};
mdio2_phy4: emdio2_phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
interrupts = <0 5 0x4>; /* Level high type */
reg = <0x3>;
phy-connection-type = "xfi";
};
};
/* Update DPMAC connections to external PHYs, under the assumption of
* SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
*/
/* Leave Cortina PHYs commented out until proper driver is integrated
*&dpmac1 {
* phy-handle = <&mdio1_phy1>;
*};
*&dpmac2 {
* phy-handle = <&mdio1_phy2>;
*};
*&dpmac3 {
* phy-handle = <&mdio1_phy3>;
*};
*&dpmac4 {
* phy-handle = <&mdio1_phy4>;
*};
*/
&dpmac5 {
phy-handle = <&mdio2_phy1>;
};
&dpmac6 {
phy-handle = <&mdio2_phy2>;
};
&dpmac7 {
phy-handle = <&mdio2_phy3>;
};
&dpmac8 {
phy-handle = <&mdio2_phy4>;
};

8
arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
View File

@ -12,7 +12,7 @@
#include "fsl-ls208xa.dtsi"
&cpu {
cpu0: cpu@0 {
cooling_map0: cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0>;
@ -32,7 +32,7 @@
#cooling-cells = <2>;
};
cpu2: cpu@100 {
cooling_map1: cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x100>;
@ -52,7 +52,7 @@
#cooling-cells = <2>;
};
cpu4: cpu@200 {
cooling_map2: cpu4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x200>;
@ -72,7 +72,7 @@
#cooling-cells = <2>;
};
cpu6: cpu@300 {
cooling_map3: cpu6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x300>;

1
arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
View File

@ -129,6 +129,7 @@
&qspi {
status = "okay";
fsl,qspi-has-second-chip;
flash0: s25fl256s1@0 {
#address-cells = <1>;
#size-cells = <1>;

11
arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
View File

@ -49,6 +49,7 @@
reg = <0x75>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-never-disable;
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
@ -108,7 +109,15 @@
};
&qspi {
status = "disabled";
status = "okay";
flash0: s25fs512s@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,m25p80";
m25p,fast-read;
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&sata0 {

149
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
View File

@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-2080A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017-2019 NXP
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*
@ -24,6 +24,7 @@
serial1 = &serial1;
serial2 = &serial2;
serial3 = &serial3;
rtc1 = &ftm_alarm0;
};
cpu: cpus {
@ -77,50 +78,14 @@
mask = <0x2>;
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
#include "fsl-tmu.dtsi"
thermal-sensors = <&tmu 4>;
trips {
cpu_alert: cpu-alert {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <85000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
timer {
timer: timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
<1 14 4>, /* Physical Non-Secure PPI, active-low */
<1 11 4>, /* Virtual PPI, active-low */
<1 10 4>; /* Hypervisor PPI, active-low */
fsl,erratum-a008585;
};
pmu {
@ -560,15 +525,42 @@
#interrupt-cells = <2>;
};
/* TODO: WRIOP (CCSR?) */
emdio1: mdio@8B96000 { /* WRIOP0: 0x8B8_0000,
* E-MDIO1: 0x1_6000
*/
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8B96000 0x0 0x1000>;
device_type = "mdio"; /* TODO: is this necessary? */
little-endian; /* force the driver in LE mode */
/* Not necessary on the QDS, but needed on the RDB */
#address-cells = <1>;
#size-cells = <0>;
};
emdio2: mdio@8B97000 { /* WRIOP0: 0x8B8_0000,
* E-MDIO2: 0x1_7000
*/
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8B97000 0x0 0x1000>;
device_type = "mdio"; /* TODO: is this necessary? */
little-endian; /* force the driver in LE mode */
#address-cells = <1>;
#size-cells = <0>;
};
i2c0: i2c@2000000 {
status = "disabled";
compatible = "fsl,vf610-i2c";
compatible = "fsl,vf610-i2c", "fsl,ls208xa-vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <0 34 0x4>; /* Level high type */
clock-names = "i2c";
clocks = <&clockgen 4 3>;
clocks = <&clockgen 4 1>;
scl-gpios = <&gpio3 10 0>;
};
i2c1: i2c@2010000 {
@ -579,7 +571,7 @@
reg = <0x0 0x2010000 0x0 0x10000>;
interrupts = <0 34 0x4>; /* Level high type */
clock-names = "i2c";
clocks = <&clockgen 4 3>;
clocks = <&clockgen 4 1>;
};
i2c2: i2c@2020000 {
@ -590,7 +582,7 @@
reg = <0x0 0x2020000 0x0 0x10000>;
interrupts = <0 35 0x4>; /* Level high type */
clock-names = "i2c";
clocks = <&clockgen 4 3>;
clocks = <&clockgen 4 1>;
};
i2c3: i2c@2030000 {
@ -601,7 +593,7 @@
reg = <0x0 0x2030000 0x0 0x10000>;
interrupts = <0 35 0x4>; /* Level high type */
clock-names = "i2c";
clocks = <&clockgen 4 3>;
clocks = <&clockgen 4 1>;
};
ifc: ifc@2240000 {
@ -633,8 +625,8 @@
pcie1: pcie@3400000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
reg-names = "regs", "config";
interrupts = <0 108 0x4>; /* Level high type */
interrupt-names = "intr";
interrupts = <0 108 0x4>; /* aer interrupt */
interrupt-names = "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@ -642,6 +634,7 @@
num-viewport = <6>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
@ -654,8 +647,8 @@
pcie2: pcie@3500000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
reg-names = "regs", "config";
interrupts = <0 113 0x4>; /* Level high type */
interrupt-names = "intr";
interrupts = <0 113 0x4>; /* aer interrupt */
interrupt-names = "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@ -663,6 +656,7 @@
num-viewport = <6>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
@ -675,8 +669,8 @@
pcie3: pcie@3600000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
reg-names = "regs", "config";
interrupts = <0 118 0x4>; /* Level high type */
interrupt-names = "intr";
interrupts = <0 118 0x4>; /* aer interrupt */
interrupt-names = "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@ -684,6 +678,7 @@
num-viewport = <256>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
@ -696,8 +691,8 @@
pcie4: pcie@3700000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
reg-names = "regs", "config";
interrupts = <0 123 0x4>; /* Level high type */
interrupt-names = "intr";
interrupts = <0 123 0x4>; /* aer interrupt */
interrupt-names = "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@ -705,6 +700,7 @@
num-viewport = <6>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
@ -741,6 +737,7 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
snps,host-vbus-glitches;
};
usb1: usb3@3110000 {
@ -752,6 +749,7 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
snps,host-vbus-glitches;
};
ccn@4000000 {
@ -759,6 +757,20 @@
reg = <0x0 0x04000000 0x0 0x01000000>;
interrupts = <0 12 4>;
};
rcpm: rcpm@1e34040 {
compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";
reg = <0x0 0x1e34040 0x0 0x18>;
#fsl,rcpm-wakeup-cells = <6>;
little-endian;
};
ftm_alarm0: timer@2800000 {
compatible = "fsl,ls208xa-ftm-alarm";
reg = <0x0 0x2800000 0x0 0x10000>;
fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
interrupts = <0 44 4>;
};
};
ddr1: memory-controller@1080000 {
@ -782,3 +794,36 @@
};
};
};
#include "fsl-tmu-map1.dtsi"
#include "fsl-tmu-map2.dtsi"
#include "fsl-tmu-map3.dtsi"
&thermal_zones {
thermal-zone1 {
status = "okay";
};
thermal-zone2{
status = "okay";
};
thermal-zone3{
status = "okay";
};
thermal-zone4{
status = "okay";
};
thermal-zone5{
status = "okay";
};
thermal-zone6{
status = "okay";
};
thermal-zone7 {
status = "okay";
};
};

207
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
View File

@ -2,7 +2,7 @@
//
// Device Tree file for LX2160AQDS
//
// Copyright 2018 NXP
// Copyright 2018-2019 NXP
/dts-v1/;
@ -29,12 +29,188 @@
regulator-boot-on;
regulator-always-on;
};
mdio-mux-1 {
compatible = "mdio-mux-multiplexer";
mux-controls = <&mux 0>;
mdio-parent-bus = <&emdio1>;
#address-cells=<1>;
#size-cells = <0>;
mdio@0 { /* On-board PHY #1 RGMI1*/
reg = <0x00>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio@8 { /* On-board PHY #2 RGMI2*/
reg = <0x8>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio@18 { /* Slot #1 */
reg = <0x18>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio@19 { /* Slot #2 */
reg = <0x19>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio@1a { /* Slot #3 */
reg = <0x1a>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio@1b { /* Slot #4 */
reg = <0x1b>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio@1c { /* Slot #5 */
reg = <0x1c>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio@1d { /* Slot #6 */
reg = <0x1d>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio@1e { /* Slot #7 */
reg = <0x1e>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio@1f { /* Slot #8 */
reg = <0x1f>;
#address-cells = <1>;
#size-cells = <0>;
};
};
mdio-mux-2 {
compatible = "mdio-mux-multiplexer";
mux-controls = <&mux 1>;
mdio-parent-bus = <&emdio2>;
#address-cells=<1>;
#size-cells = <0>;
mdio@0 { /* Slot #1 (secondary EMI) */
reg = <0x00>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio@1 { /* Slot #2 (secondary EMI) */
reg = <0x01>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio@2 { /* Slot #3 (secondary EMI) */
reg = <0x02>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio@3 { /* Slot #4 (secondary EMI) */
reg = <0x03>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio@4 { /* Slot #5 (secondary EMI) */
reg = <0x04>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio@5 { /* Slot #6 (secondary EMI) */
reg = <0x05>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio@6 { /* Slot #7 (secondary EMI) */
reg = <0x06>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio@7 { /* Slot #8 (secondary EMI) */
reg = <0x07>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&can0 {
status = "okay";
};
&can1 {
status = "okay";
};
&crypto {
status = "okay";
};
&dspi0 {
status = "okay";
dflash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
&dspi1 {
status = "okay";
dflash1: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
&dspi2 {
status = "okay";
dflash2: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
&emdio1 {
status = "okay";
};
&emdio2 {
status = "okay";
};
&esdhc0 {
status = "okay";
};
@ -46,6 +222,19 @@
&i2c0 {
status = "okay";
fpga@66 {
compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
"simple-mfd";
reg = <0x66>;
mux: mux-controller {
compatible = "reg-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
<0x54 0x07>; /* 1: reg 0x54, bit 2:0 */
};
};
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
@ -126,3 +315,19 @@
&usb1 {
status = "okay";
};
&sata0 {
status = "okay";
};
&sata1 {
status = "okay";
};
&sata2 {
status = "okay";
};
&sata3 {
status = "okay";
};

88
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
View File

@ -2,7 +2,7 @@
//
// Device Tree file for LX2160ARDB
//
// Copyright 2018 NXP
// Copyright 2018-2019 NXP
/dts-v1/;
@ -31,10 +31,34 @@
};
};
&can0 {
status = "okay";
can-transceiver {
max-bitrate = <5000000>;
};
};
&can1 {
status = "okay";
can-transceiver {
max-bitrate = <5000000>;
};
};
&crypto {
status = "okay";
};
&emdio1 {
status = "okay";
};
&emdio2 {
status = "okay";
};
&esdhc0 {
sd-uhs-sdr104;
sd-uhs-sdr50;
@ -159,3 +183,65 @@
&usb1 {
status = "okay";
};
&emdio1 {
rgmii_phy1: ethernet-phy@1 {
/* AR8035 PHY - "compatible" property not strictly needed */
compatible = "ethernet-phy-id004d.d072";
reg = <0x1>;
/* Poll mode - no "interrupts" property defined */
};
rgmii_phy2: ethernet-phy@2 {
/* AR8035 PHY - "compatible" property not strictly needed */
compatible = "ethernet-phy-id004d.d072";
reg = <0x2>;
/* Poll mode - no "interrupts" property defined */
};
aquantia_phy1: ethernet-phy@4 {
/* AQR107 PHY - "compatible" property not strictly needed */
compatible = "ethernet-phy-ieee802.3-c45";
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x4>;
};
aquantia_phy2: ethernet-phy@5 {
/* AQR107 PHY - "compatible" property not strictly needed */
compatible = "ethernet-phy-ieee802.3-c45";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5>;
};
};
&emdio2 {
inphi_phy: ethernet-phy@0 {
compatible = "ethernet-phy-id0210.7440";
reg = <0x0>;
};
};
&dpmac3 {
phy-handle = <&aquantia_phy1>;
phy-connection-type = "usxgmii";
};
&dpmac4 {
phy-handle = <&aquantia_phy2>;
phy-connection-type = "usxgmii";
};
&dpmac5 {
phy-handle = <&inphi_phy>;
};
&dpmac6 {
phy-handle = <&inphi_phy>;
};
&dpmac17 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii-id";
};
&dpmac18 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii-id";
};

442
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View File

@ -2,10 +2,11 @@
//
// Device Tree Include file for Layerscape-LX2160A family SoC.
//
// Copyright 2018 NXP
// Copyright 2018-2019 NXP
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
/memreserve/ 0x80000000 0x00010000;
@ -15,12 +16,16 @@
#address-cells = <2>;
#size-cells = <2>;
aliases {
rtc1 = &ftm_alarm0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
// 8 clusters having 2 Cortex-A72 cores each
cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@ -34,9 +39,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster0_l2>;
cpu-idle-states = <&cpu_pw15>;
#cooling-cells = <2>;
};
cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@ -50,9 +56,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster0_l2>;
cpu-idle-states = <&cpu_pw15>;
#cooling-cells = <2>;
};
cpu@100 {
cpu100: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@ -66,9 +73,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster1_l2>;
cpu-idle-states = <&cpu_pw15>;
#cooling-cells = <2>;
};
cpu@101 {
cpu101: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@ -82,9 +90,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster1_l2>;
cpu-idle-states = <&cpu_pw15>;
#cooling-cells = <2>;
};
cpu@200 {
cpu200: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@ -98,9 +107,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster2_l2>;
cpu-idle-states = <&cpu_pw15>;
#cooling-cells = <2>;
};
cpu@201 {
cpu201: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@ -114,9 +124,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster2_l2>;
cpu-idle-states = <&cpu_pw15>;
#cooling-cells = <2>;
};
cpu@300 {
cpu300: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@ -130,9 +141,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster3_l2>;
cpu-idle-states = <&cpu_pw15>;
#cooling-cells = <2>;
};
cpu@301 {
cpu301: cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@ -146,9 +158,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster3_l2>;
cpu-idle-states = <&cpu_pw15>;
#cooling-cells = <2>;
};
cpu@400 {
cpu400: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@ -162,9 +175,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster4_l2>;
cpu-idle-states = <&cpu_pw15>;
#cooling-cells = <2>;
};
cpu@401 {
cpu401: cpu@401 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@ -178,9 +192,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster4_l2>;
cpu-idle-states = <&cpu_pw15>;
#cooling-cells = <2>;
};
cpu@500 {
cpu500: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@ -194,9 +209,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster5_l2>;
cpu-idle-states = <&cpu_pw15>;
#cooling-cells = <2>;
};
cpu@501 {
cpu501: cpu@501 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@ -210,9 +226,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster5_l2>;
cpu-idle-states = <&cpu_pw15>;
#cooling-cells = <2>;
};
cpu@600 {
cpu600: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@ -226,9 +243,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster6_l2>;
cpu-idle-states = <&cpu_pw15>;
#cooling-cells = <2>;
};
cpu@601 {
cpu601: cpu@601 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@ -242,9 +260,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster6_l2>;
cpu-idle-states = <&cpu_pw15>;
#cooling-cells = <2>;
};
cpu@700 {
cpu700: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@ -258,9 +277,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster7_l2>;
cpu-idle-states = <&cpu_pw15>;
#cooling-cells = <2>;
};
cpu@701 {
cpu701: cpu@701 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@ -274,6 +294,7 @@
i-cache-sets = <192>;
next-level-cache = <&cluster7_l2>;
cpu-idle-states = <&cpu_pw15>;
#cooling-cells = <2>;
};
cluster0_l2: l2-cache0 {
@ -418,6 +439,51 @@
clock-output-names = "sysclk";
};
thermal-zones {
core_thermal1: core-thermal1 {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 0>;
trips {
core_cluster_alert: core-cluster-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
core_cluster_crit: core-cluster-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&core_cluster_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
@ -478,6 +544,28 @@
little-endian;
};
/* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
emdio1: mdio@8b96000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8b96000 0x0 0x1000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
little-endian; /* force the driver in LE mode */
status = "disabled";
};
/* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */
emdio2: mdio@8b97000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8b97000 0x0 0x1000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
little-endian; /* force the driver in LE mode */
status = "disabled";
};
i2c0: i2c@2000000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
@ -486,7 +574,7 @@
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 15>;
scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
@ -531,7 +619,7 @@
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 15>;
scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
@ -581,6 +669,45 @@
status = "disabled";
};
dspi0: spi@2100000 {
compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 7>;
clock-names = "dspi";
spi-num-chipselects = <5>;
bus-num = <0>;
status = "disabled";
};
dspi1: spi@2110000 {
compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2110000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 7>;
clock-names = "dspi";
spi-num-chipselects = <5>;
bus-num = <1>;
status = "disabled";
};
dspi2: spi@2120000 {
compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2120000 0x0 0x10000>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 7>;
clock-names = "dspi";
spi-num-chipselects = <5>;
bus-num = <2>;
status = "disabled";
};
esdhc0: esdhc@2140000 {
compatible = "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;
@ -606,6 +733,38 @@
status = "disabled";
};
can0: can@2180000 {
compatible = "fsl,lx2160ar1-flexcan";
reg = <0x0 0x2180000 0x0 0x10000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysclk>, <&clockgen 4 7>;
clock-names = "ipg", "per";
status = "disabled";
};
can1: can@2190000 {
compatible = "fsl,lx2160ar1-flexcan";
reg = <0x0 0x2190000 0x0 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysclk>, <&clockgen 4 7>;
clock-names = "ipg", "per";
status = "disabled";
};
tmu: tmu@1f80000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f80000 0x0 0x10000>;
interrupts = <0 23 0x4>;
fsl,tmu-range = <0x800000E6 0x8001017D>;
fsl,tmu-calibration =
/* Calibration data group 1 */
<0x00000000 0x00000035
/* Calibration data group 2 */
0x00010001 0x00000154>;
little-endian;
#thermal-sensor-cells = <1>;
};
uart0: serial@21c0000 {
compatible = "arm,sbsa-uart","arm,pl011";
reg = <0x0 0x21c0000 0x0 0x1000>;
@ -690,14 +849,31 @@
timeout-sec = <30>;
};
rcpm: rcpm@1e34040 {
compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+";
reg = <0x0 0x1e34040 0x0 0x1c>;
#fsl,rcpm-wakeup-cells = <7>;
little-endian;
};
ftm_alarm0: timer@2800000 {
compatible = "fsl,lx2160a-ftm-alarm";
reg = <0x0 0x2800000 0x0 0x10000>;
fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
interrupts = <0 44 4>;
};
usb0: usb@3100000 {
compatible = "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
snps,host-vbus-glitches;
status = "disabled";
};
@ -707,8 +883,11 @@
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
snps,host-vbus-glitches;
status = "disabled";
};
@ -756,6 +935,224 @@
status = "disabled";
};
pcie@3400000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x80 0x00000000 0x0 0x00001000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "aer", "pme", "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
apio-wins = <8>;
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
pcie_ep@3400000 {
compatible = "fsl,lx2160a-pcie-ep";
reg = <0x00 0x03400000 0x0 0x00100000
0x80 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <256>;
status = "disabled";
};
pcie@3500000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x88 0x00000000 0x0 0x00001000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "aer", "pme", "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
apio-wins = <8>;
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
pcie_ep@3500000 {
compatible = "fsl,lx2160a-pcie-ep";
reg = <0x00 0x03500000 0x0 0x00100000
0x88 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <256>;
status = "disabled";
};
pcie@3600000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x90 0x00000000 0x0 0x00001000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "aer", "pme", "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
apio-wins = <8>;
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
pcie_ep@3600000 {
compatible = "fsl,lx2160a-pcie-ep";
reg = <0x00 0x03600000 0x0 0x00100000
0x90 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <256>;
max-functions = <2>;
status = "disabled";
};
pcie@3700000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
0x98 0x00000000 0x0 0x00001000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "aer", "pme", "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
apio-wins = <8>;
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
pcie_ep@3700000 {
compatible = "fsl,lx2160a-pcie-ep";
reg = <0x00 0x03700000 0x0 0x00100000
0x98 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <256>;
status = "disabled";
};
pcie@3800000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
0xa0 0x00000000 0x0 0x00001000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "aer", "pme", "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
apio-wins = <8>;
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
pcie_ep@3800000 {
compatible = "fsl,lx2160a-pcie-ep";
reg = <0x00 0x03800000 0x0 0x00100000
0xa0 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <256>;
max-functions = <2>;
status = "disabled";
};
pcie@3900000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
0xa8 0x00000000 0x0 0x00001000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "aer", "pme", "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
apio-wins = <8>;
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
pcie_ep@3900000 {
compatible = "fsl,lx2160a-pcie-ep";
reg = <0x00 0x03900000 0x0 0x00100000
0xa8 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <256>;
status = "disabled";
};
smmu: iommu@5000000 {
compatible = "arm,mmu-500";
reg = <0 0x5000000 0 0x800000>;
@ -978,4 +1375,11 @@
};
};
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};

99
arch/arm64/boot/dts/freescale/fsl-tmu-map1.dtsi 100644
View File

@ -0,0 +1,99 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Thermal Monitor Unit.
*
* Copyright 2018 NXP
*
* Tang Yuantian <andy.tang@nxp.com>
*
*/
&thermal_zones {
thermal-zone0 {
cooling-maps {
map1 {
trip = <&alert0>;
cooling-device =
<&cooling_map1 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone1 {
cooling-maps {
map1 {
trip = <&alert1>;
cooling-device =
<&cooling_map1 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone2 {
cooling-maps {
map1 {
trip = <&alert2>;
cooling-device =
<&cooling_map1 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone3 {
cooling-maps {
map1 {
trip = <&alert3>;
cooling-device =
<&cooling_map1 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone4 {
cooling-maps {
map1 {
trip = <&alert4>;
cooling-device =
<&cooling_map1 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone5 {
cooling-maps {
map1 {
trip = <&alert5>;
cooling-device =
<&cooling_map1 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone6 {
cooling-maps {
map1 {
trip = <&alert6>;
cooling-device =
<&cooling_map1 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone7 {
cooling-maps {
map1 {
trip = <&alert7>;
cooling-device =
<&cooling_map1 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
};

99
arch/arm64/boot/dts/freescale/fsl-tmu-map2.dtsi 100644
View File

@ -0,0 +1,99 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Thermal Monitor Unit.
*
* Copyright 2018 NXP
*
* Tang Yuantian <andy.tang@nxp.com>
*
*/
&thermal_zones {
thermal-zone0 {
cooling-maps {
map2 {
trip = <&alert0>;
cooling-device =
<&cooling_map2 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone1 {
cooling-maps {
map2 {
trip = <&alert1>;
cooling-device =
<&cooling_map2 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone2 {
cooling-maps {
map2 {
trip = <&alert2>;
cooling-device =
<&cooling_map2 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone3 {
cooling-maps {
map2 {
trip = <&alert3>;
cooling-device =
<&cooling_map2 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone4 {
cooling-maps {
map2 {
trip = <&alert4>;
cooling-device =
<&cooling_map2 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone5 {
cooling-maps {
map2 {
trip = <&alert5>;
cooling-device =
<&cooling_map2 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone6 {
cooling-maps {
map2 {
trip = <&alert6>;
cooling-device =
<&cooling_map2 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone7 {
cooling-maps {
map2 {
trip = <&alert7>;
cooling-device =
<&cooling_map2 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
};

99
arch/arm64/boot/dts/freescale/fsl-tmu-map3.dtsi 100644
View File

@ -0,0 +1,99 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Thermal Monitor Unit.
*
* Copyright 2018 NXP
*
* Tang Yuantian <andy.tang@nxp.com>
*
*/
&thermal_zones {
thermal-zone0 {
cooling-maps {
map3 {
trip = <&alert0>;
cooling-device =
<&cooling_map3 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone1 {
cooling-maps {
map3 {
trip = <&alert1>;
cooling-device =
<&cooling_map3 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone2 {
cooling-maps {
map3 {
trip = <&alert2>;
cooling-device =
<&cooling_map3 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone3 {
cooling-maps {
map3 {
trip = <&alert3>;
cooling-device =
<&cooling_map3 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone4 {
cooling-maps {
map3 {
trip = <&alert4>;
cooling-device =
<&cooling_map3 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone5 {
cooling-maps {
map3 {
trip = <&alert5>;
cooling-device =
<&cooling_map3 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone6 {
cooling-maps {
map3 {
trip = <&alert6>;
cooling-device =
<&cooling_map3 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone7 {
cooling-maps {
map3 {
trip = <&alert7>;
cooling-device =
<&cooling_map3 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
};

251
arch/arm64/boot/dts/freescale/fsl-tmu.dtsi 100644
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@ -0,0 +1,251 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Thermal Monitor Unit.
*
* Copyright 2018 NXP
*
* Tang Yuantian <andy.tang@nxp.com>
*
*/
thermal_zones: thermal-zones {
thermal_zone0: thermal-zone0 {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 0>;
status = "disabled";
trips {
alert0: alert0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
crit0: crit0 {
temperature = <85000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&alert0>;
cooling-device =
<&cooling_map0 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone1 {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 1>;
status = "disabled";
trips {
alert1: alert1 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
crit1: crit1 {
temperature = <85000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&alert1>;
cooling-device =
<&cooling_map0 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone2 {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 2>;
status = "disabled";
trips {
alert2: alert2 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
crit2: crit2 {
temperature = <85000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&alert2>;
cooling-device =
<&cooling_map0 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone3 {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 3>;
status = "disabled";
trips {
alert3: alert3 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
crit3: crit3 {
temperature = <85000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&alert3>;
cooling-device =
<&cooling_map0 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone4 {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 4>;
status = "disabled";
trips {
alert4: alert4 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
crit4: crit4 {
temperature = <85000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&alert4>;
cooling-device =
<&cooling_map0 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone5 {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 5>;
status = "disabled";
trips {
alert5: alert5 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
crit5: crit5 {
temperature = <85000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&alert5>;
cooling-device =
<&cooling_map0 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone6 {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 6>;
status = "disabled";
trips {
alert6: alert6 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
crit6: crit6 {
temperature = <85000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&alert6>;
cooling-device =
<&cooling_map0 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
thermal-zone7 {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 7>;
status = "disabled";
trips {
alert7: alert7 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
crit7: crit7 {
temperature = <85000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&alert7>;
cooling-device =
<&cooling_map0 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
};

55
arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi 100644
View File

@ -0,0 +1,55 @@
/*
* QorIQ BMan SDK Portals device tree nodes
*
* Copyright 2011-2016 Freescale Semiconductor Inc.
* Copyright 2017 NXP
*
* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
*/
&bportals {
bman-portal@0 {
cell-index = <0>;
};
bman-portal@10000 {
cell-index = <1>;
};
bman-portal@20000 {
cell-index = <2>;
};
bman-portal@30000 {
cell-index = <3>;
};
bman-portal@40000 {
cell-index = <4>;
};
bman-portal@50000 {
cell-index = <5>;
};
bman-portal@60000 {
cell-index = <6>;
};
bman-portal@70000 {
cell-index = <7>;
};
bman-portal@80000 {
cell-index = <8>;
};
bman-portal@90000 {
cell-index = <9>;
};
bman-bpids@0 {
compatible = "fsl,bpid-range";
fsl,bpid-range = <32 32>;
};
};

72
arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi 100644
View File

@ -0,0 +1,72 @@
/*
* QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
fsldpaa: fsl,dpaa {
compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa";
ethernet@0 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet0>;
dma-coherent;
};
ethernet@1 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet1>;
dma-coherent;
};
ethernet@2 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet2>;
dma-coherent;
};
ethernet@3 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet3>;
dma-coherent;
};
ethernet@4 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet4>;
dma-coherent;
};
ethernet@5 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet5>;
dma-coherent;
};
ethernet@8 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet6>;
dma-coherent;
};
};

5
arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
View File

@ -9,16 +9,17 @@
fman@1a00000 {
fman0_rx_0x10: port@90000 {
cell-index = <0x10>;
compatible = "fsl,fman-v3-port-rx";
compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
reg = <0x90000 0x1000>;
fsl,fman-10g-port;
};
fman0_tx_0x30: port@b0000 {
cell-index = <0x30>;
compatible = "fsl,fman-v3-port-tx";
compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
reg = <0xb0000 0x1000>;
fsl,fman-10g-port;
fsl,qman-channel-id = <0x800>;
};
ethernet@f0000 {

5
arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
View File

@ -9,16 +9,17 @@
fman@1a00000 {
fman0_rx_0x11: port@91000 {
cell-index = <0x11>;
compatible = "fsl,fman-v3-port-rx";
compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
reg = <0x91000 0x1000>;
fsl,fman-10g-port;
};
fman0_tx_0x31: port@b1000 {
cell-index = <0x31>;
compatible = "fsl,fman-v3-port-tx";
compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
reg = <0xb1000 0x1000>;
fsl,fman-10g-port;
fsl,qman-channel-id = <0x801>;
};
ethernet@f2000 {

5
arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
View File

@ -9,14 +9,15 @@
fman@1a00000 {
fman0_rx_0x08: port@88000 {
cell-index = <0x8>;
compatible = "fsl,fman-v3-port-rx";
compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
reg = <0x88000 0x1000>;
};
fman0_tx_0x28: port@a8000 {
cell-index = <0x28>;
compatible = "fsl,fman-v3-port-tx";
compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
reg = <0xa8000 0x1000>;
fsl,qman-channel-id = <0x802>;
};
ethernet@e0000 {

5
arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
View File

@ -9,14 +9,15 @@
fman@1a00000 {
fman0_rx_0x09: port@89000 {
cell-index = <0x9>;
compatible = "fsl,fman-v3-port-rx";
compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
reg = <0x89000 0x1000>;
};
fman0_tx_0x29: port@a9000 {
cell-index = <0x29>;
compatible = "fsl,fman-v3-port-tx";
compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
reg = <0xa9000 0x1000>;
fsl,qman-channel-id = <0x803>;
};
ethernet@e2000 {

5
arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
View File

@ -9,14 +9,15 @@
fman@1a00000 {
fman0_rx_0x0a: port@8a000 {
cell-index = <0xa>;
compatible = "fsl,fman-v3-port-rx";
compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
reg = <0x8a000 0x1000>;
};
fman0_tx_0x2a: port@aa000 {
cell-index = <0x2a>;
compatible = "fsl,fman-v3-port-tx";
compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
reg = <0xaa000 0x1000>;
fsl,qman-channel-id = <0x804>;
};
ethernet@e4000 {

5
arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
View File

@ -9,14 +9,15 @@
fman@1a00000 {
fman0_rx_0x0b: port@8b000 {
cell-index = <0xb>;
compatible = "fsl,fman-v3-port-rx";
compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
reg = <0x8b000 0x1000>;
};
fman0_tx_0x2b: port@ab000 {
cell-index = <0x2b>;
compatible = "fsl,fman-v3-port-tx";
compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
reg = <0xab000 0x1000>;
fsl,qman-channel-id = <0x805>;
};
ethernet@e6000 {

5
arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
View File

@ -9,14 +9,15 @@
fman@1a00000 {
fman0_rx_0x0c: port@8c000 {
cell-index = <0xc>;
compatible = "fsl,fman-v3-port-rx";
compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
reg = <0x8c000 0x1000>;
};
fman0_tx_0x2c: port@ac000 {
cell-index = <0x2c>;
compatible = "fsl,fman-v3-port-tx";
compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
reg = <0xac000 0x1000>;
fsl,qman-channel-id = <0x806>;
};
ethernet@e8000 {

5
arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
View File

@ -9,14 +9,15 @@
fman@1a00000 {
fman0_rx_0x0d: port@8d000 {
cell-index = <0xd>;
compatible = "fsl,fman-v3-port-rx";
compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
reg = <0x8d000 0x1000>;
};
fman0_tx_0x2d: port@ad000 {
cell-index = <0x2d>;
compatible = "fsl,fman-v3-port-tx";
compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
reg = <0xad000 0x1000>;
fsl,qman-channel-id = <0x807>;
};
ethernet@ea000 {

47
arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi 100644
View File

@ -0,0 +1,47 @@
/*
* QorIQ FMan v3 OH ports device tree
*
* Copyright 2012-2015 Freescale Semiconductor Inc.
*
* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
*/
fman@1a00000 {
fman0_oh1: port@82000 {
cell-index = <0>;
compatible = "fsl,fman-port-oh";
reg = <0x82000 0x1000>;
};
fman0_oh2: port@83000 {
cell-index = <1>;
compatible = "fsl,fman-port-oh";
reg = <0x83000 0x1000>;
};
fman0_oh3: port@84000 {
cell-index = <2>;
compatible = "fsl,fman-port-oh";
reg = <0x84000 0x1000>;
};
fman0_oh4: port@85000 {
cell-index = <3>;
compatible = "fsl,fman-port-oh";
reg = <0x85000 0x1000>;
};
fman0_oh5: port@86000 {
cell-index = <4>;
compatible = "fsl,fman-port-oh";
reg = <0x86000 0x1000>;
};
fman0_oh6: port@87000 {
cell-index = <5>;
compatible = "fsl,fman-port-oh";
reg = <0x87000 0x1000>;
};
};

52
arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
View File

@ -20,45 +20,95 @@ fman0: fman@1a00000 {
fsl,qman-channel-range = <0x800 0x10>;
ptimer-handle = <&ptp_timer0>;
cc {
compatible = "fsl,fman-cc";
};
muram@0 {
compatible = "fsl,fman-muram";
reg = <0x0 0x60000>;
};
bmi@80000 {
compatible = "fsl,fman-bmi";
reg = <0x80000 0x400>;
};
qmi@80400 {
compatible = "fsl,fman-qmi";
reg = <0x80400 0x400>;
};
fman0_oh_0x2: port@82000 {
cell-index = <0x2>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x82000 0x1000>;
fsl,qman-channel-id = <0x809>;
};
fman0_oh_0x3: port@83000 {
cell-index = <0x3>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x83000 0x1000>;
fsl,qman-channel-id = <0x80a>;
};
fman0_oh_0x4: port@84000 {
cell-index = <0x4>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x84000 0x1000>;
fsl,qman-channel-id = <0x80b>;
};
fman0_oh_0x5: port@85000 {
cell-index = <0x5>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x85000 0x1000>;
fsl,qman-channel-id = <0x80c>;
};
fman0_oh_0x6: port@86000 {
cell-index = <0x6>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x86000 0x1000>;
fsl,qman-channel-id = <0x80d>;
};
fman0_oh_0x7: port@87000 {
cell-index = <0x7>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x87000 0x1000>;
fsl,qman-channel-id = <0x80e>;
};
policer@c0000 {
compatible = "fsl,fman-policer";
reg = <0xc0000 0x1000>;
};
keygen@c1000 {
compatible = "fsl,fman-keygen";
reg = <0xc1000 0x1000>;
};
dma@c2000 {
compatible = "fsl,fman-dma";
reg = <0xc2000 0x1000>;
};
fpm@c3000 {
compatible = "fsl,fman-fpm";
reg = <0xc3000 0x1000>;
};
parser@c7000 {
compatible = "fsl,fman-parser";
reg = <0xc7000 0x1000>;
};
vsps@dc000 {
compatible = "fsl,fman-vsps";
reg = <0xdc000 0x1000>;
};
mdio0: mdio@fc000 {
@ -77,7 +127,7 @@ fman0: fman@1a00000 {
};
ptp_timer0: ptp-timer@1afe000 {
compatible = "fsl,fman-ptp-timer";
compatible = "fsl,fman-ptp-timer", "fsl,fman-rtc";
reg = <0x0 0x1afe000 0x0 0x1000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 3 0>;

38
arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi 100644
View File

@ -0,0 +1,38 @@
/*
* QorIQ QMan SDK Portals device tree nodes
*
* Copyright 2011-2016 Freescale Semiconductor Inc.
* Copyright 2017 NXP
*
* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
*/
&qportals {
qman-fqids@0 {
compatible = "fsl,fqid-range";
fsl,fqid-range = <256 256>;
};
qman-fqids@1 {
compatible = "fsl,fqid-range";
fsl,fqid-range = <32768 32768>;
};
qman-pools@0 {
compatible = "fsl,pool-channel-range";
fsl,pool-channel-range = <0x401 0xf>;
};
qman-cgrids@0 {
compatible = "fsl,cgrid-range";
fsl,cgrid-range = <0 256>;
};
qman-ceetm@0 {
compatible = "fsl,qman-ceetm";
fsl,ceetm-lfqid-range = <0xf00000 0x1000>;
fsl,ceetm-sp-range = <0 16>;
fsl,ceetm-lni-range = <0 8>;
fsl,ceetm-channel-range = <0 32>;
};
};

6
arch/powerpc/boot/dts/fsl/b4420qds-sdk.dts 100644
View File

@ -0,0 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright 2017-2018 NXP
*/
/include/ "b4420qds.dts"

6
arch/powerpc/boot/dts/fsl/b4860qds-sdk.dts 100644
View File

@ -0,0 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright 2017-2018 NXP
*/
/include/ "b4860qds.dts"

14
arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
View File

@ -199,6 +199,10 @@
/include/ "pq3-dma-0.dtsi"
/include/ "pq3-etsec1-0.dtsi"
enet0: ethernet@24000 {
fsl,wake-on-filer;
fsl,pmc-handle = <&etsec1_clk>;
};
/include/ "pq3-etsec1-timer-0.dtsi"
usb@22000 {
@ -222,9 +226,10 @@
};
/include/ "pq3-etsec1-2.dtsi"
ethernet@26000 {
enet2: ethernet@26000 {
cell-index = <1>;
fsl,wake-on-filer;
fsl,pmc-handle = <&etsec3_clk>;
};
usb@2b000 {
@ -249,4 +254,9 @@
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
/include/ "pq3-power.dtsi"
power@e0070 {
compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
};
};

2
arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi
View File

@ -188,4 +188,6 @@
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
/include/ "pq3-power.dtsi"
};

2
arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
View File

@ -156,4 +156,6 @@
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
/include/ "pq3-power.dtsi"
};

2
arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi
View File

@ -193,4 +193,6 @@
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
/include/ "pq3-power.dtsi"
};

16
arch/powerpc/boot/dts/fsl/p1010rdb-pb.dts
View File

@ -29,3 +29,19 @@
};
/include/ "p1010si-post.dtsi"
&pci0 {
pcie@0 {
interrupt-map = <
/* IDSEL 0x0 */
/*
*irq[4:5] are active-high
*irq[6:7] are active-low
*/
0000 0x0 0x0 0x1 &mpic 0x4 0x2 0x0 0x0
0000 0x0 0x0 0x2 &mpic 0x5 0x2 0x0 0x0
0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
>;
};
};

16
arch/powerpc/boot/dts/fsl/p1010rdb-pb_36b.dts
View File

@ -56,3 +56,19 @@
};
/include/ "p1010si-post.dtsi"
&pci0 {
pcie@0 {
interrupt-map = <
/* IDSEL 0x0 */
/*
*irq[4:5] are active-high
*irq[6:7] are active-low
*/
0000 0x0 0x0 0x1 &mpic 0x4 0x2 0x0 0x0
0000 0x0 0x0 0x2 &mpic 0x5 0x2 0x0 0x0
0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
>;
};
};

16
arch/powerpc/boot/dts/fsl/p1010rdb.dtsi
View File

@ -215,19 +215,3 @@
phy-connection-type = "sgmii";
};
};
&pci0 {
pcie@0 {
interrupt-map = <
/* IDSEL 0x0 */
/*
*irq[4:5] are active-high
*irq[6:7] are active-low
*/
0000 0x0 0x0 0x1 &mpic 0x4 0x2 0x0 0x0
0000 0x0 0x0 0x2 &mpic 0x5 0x2 0x0 0x0
0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
>;
};
};

8
arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
View File

@ -173,6 +173,8 @@
/include/ "pq3-etsec2-0.dtsi"
enet0: ethernet@b0000 {
fsl,pmc-handle = <&etsec1_clk>;
queue-group@b0000 {
fsl,rx-bit-map = <0xff>;
fsl,tx-bit-map = <0xff>;
@ -181,6 +183,8 @@
/include/ "pq3-etsec2-1.dtsi"
enet1: ethernet@b1000 {
fsl,pmc-handle = <&etsec2_clk>;
queue-group@b1000 {
fsl,rx-bit-map = <0xff>;
fsl,tx-bit-map = <0xff>;
@ -189,6 +193,8 @@
/include/ "pq3-etsec2-2.dtsi"
enet2: ethernet@b2000 {
fsl,pmc-handle = <&etsec3_clk>;
queue-group@b2000 {
fsl,rx-bit-map = <0xff>;
fsl,tx-bit-map = <0xff>;
@ -201,4 +207,6 @@
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
/include/ "pq3-power.dtsi"
};

5
arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
View File

@ -163,14 +163,17 @@
/include/ "pq3-etsec2-0.dtsi"
enet0: enet0_grp2: ethernet@b0000 {
fsl,pmc-handle = <&etsec1_clk>;
};
/include/ "pq3-etsec2-1.dtsi"
enet1: enet1_grp2: ethernet@b1000 {
fsl,pmc-handle = <&etsec2_clk>;
};
/include/ "pq3-etsec2-2.dtsi"
enet2: enet2_grp2: ethernet@b2000 {
fsl,pmc-handle = <&etsec3_clk>;
};
global-utilities@e0000 {
@ -178,6 +181,8 @@
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
/include/ "pq3-power.dtsi"
};
/include/ "pq3-etsec2-grp2-0.dtsi"

5
arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
View File

@ -159,14 +159,17 @@
/include/ "pq3-etsec2-0.dtsi"
enet0: enet0_grp2: ethernet@b0000 {
fsl,pmc-handle = <&etsec1_clk>;
};
/include/ "pq3-etsec2-1.dtsi"
enet1: enet1_grp2: ethernet@b1000 {
fsl,pmc-handle = <&etsec2_clk>;
};
/include/ "pq3-etsec2-2.dtsi"
enet2: enet2_grp2: ethernet@b2000 {
fsl,pmc-handle = <&etsec3_clk>;
};
global-utilities@e0000 {
@ -174,6 +177,8 @@
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
/include/ "pq3-power.dtsi"
};
&qe {

9
arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
View File

@ -225,11 +225,13 @@
/include/ "pq3-etsec2-0.dtsi"
enet0: enet0_grp2: ethernet@b0000 {
fsl,wake-on-filer;
fsl,pmc-handle = <&etsec1_clk>;
};
/include/ "pq3-etsec2-1.dtsi"
enet1: enet1_grp2: ethernet@b1000 {
fsl,wake-on-filer;
fsl,pmc-handle = <&etsec2_clk>;
};
global-utilities@e0000 {
@ -238,9 +240,10 @@
fsl,has-rstcr;
};
power@e0070{
compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
reg = <0xe0070 0x20>;
/include/ "pq3-power.dtsi"
power@e0070 {
compatible = "fsl,p1022-pmc", "fsl,mpc8536-pmc",
"fsl,mpc8548-pmc";
};
};

126
arch/powerpc/boot/dts/fsl/p1023rdb-sdk.dts 100644
View File

@ -0,0 +1,126 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright 2017-2018 NXP
*/
/include/ "p1023rdb.dts"
&soc {
fman0: fman@100000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
compatible = "fsl,fman", "simple-bus";
ranges = <0 0x100000 0x100000>;
reg = <0x100000 0x100000>;
clock-frequency = <0>;
interrupts = <
24 2 0 0
16 2 0 0>;
cc@0 {
compatible = "fsl,fman-cc";
};
muram@0 {
compatible = "fsl,fman-muram";
reg = <0x0 0x10000>;
};
bmi@80000 {
compatible = "fsl,fman-bmi";
reg = <0x80000 0x400>;
};
qmi@80400 {
compatible = "fsl,fman-qmi";
reg = <0x80400 0x400>;
};
policer@c0000 {
compatible = "fsl,fman-policer";
reg = <0xc0000 0x1000>;
};
keygen@c1000 {
compatible = "fsl,fman-keygen";
reg = <0xc1000 0x1000>;
};
dma@c2000 {
compatible = "fsl,fman-dma";
reg = <0xc2000 0x1000>;
};
fpm@c3000 {
compatible = "fsl,fman-fpm";
reg = <0xc3000 0x1000>;
};
parser@c7000 {
compatible = "fsl,fman-parser";
reg = <0xc7000 0x1000>;
};
fman0_rx0: port@88000 {
cell-index = <0>;
compatible = "fsl,fman-port-1g-rx";
reg = <0x88000 0x1000>;
};
fman0_rx1: port@89000 {
cell-index = <1>;
compatible = "fsl,fman-port-1g-rx";
reg = <0x89000 0x1000>;
};
fman0_tx0: port@a8000 {
cell-index = <0>;
compatible = "fsl,fman-port-1g-tx";
reg = <0xa8000 0x1000>;
fsl,qman-channel-id = <0x40>;
};
fman0_tx1: port@a9000 {
cell-index = <1>;
compatible = "fsl,fman-port-1g-tx";
reg = <0xa9000 0x1000>;
fsl,qman-channel-id = <0x41>;
};
fman0_oh1: port@82000 {
cell-index = <1>;
compatible = "fsl,fman-port-oh";
reg = <0x82000 0x1000>;
fsl,qman-channel-id = <0x43>;
};
fman0_oh2: port@83000 {
cell-index = <2>;
compatible = "fsl,fman-port-oh";
reg = <0x83000 0x1000>;
fsl,qman-channel-id = <0x44>;
};
fman0_oh3: port@84000 {
cell-index = <3>;
compatible = "fsl,fman-port-oh";
reg = <0x84000 0x1000>;
fsl,qman-channel-id = <0x45>;
};
fman0_oh4: port@85000 {
cell-index = <4>;
compatible = "fsl,fman-port-oh";
reg = <0x85000 0x1000>;
fsl,qman-channel-id = <0x46>;
};
enet0: ethernet@e0000 {
cell-index = <0>;
compatible = "fsl,fman-dtsec";
reg = <0xe0000 0x1000>;
fsl,port-handles = <&fman0_rx0 &fman0_tx0>;
};
enet1: ethernet@e2000 {
cell-index = <1>;
compatible = "fsl,fman-dtsec";
reg = <0xe2000 0x1000>;
fsl,port-handles = <&fman0_rx1 &fman0_tx1>;
};
mdio0: mdio@e1120 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-mdio";
reg = <0xe1120 0xee0>;
interrupts = <26 1 0 0>;
};
};
};
&bportals {
compatible = "fsl,bpid-range";
fsl,bpid-range = <32 32>;
};

14
arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
View File

@ -175,6 +175,10 @@
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
};
/include/ "pq3-etsec1-0.dtsi"
enet0: ethernet@24000 {
fsl,pmc-handle = <&etsec1_clk>;
};
/include/ "pq3-etsec1-timer-0.dtsi"
ptp_clock@24e00 {
@ -183,7 +187,15 @@
/include/ "pq3-etsec1-1.dtsi"
enet1: ethernet@25000 {
fsl,pmc-handle = <&etsec2_clk>;
};
/include/ "pq3-etsec1-2.dtsi"
enet2: ethernet@26000 {
fsl,pmc-handle = <&etsec3_clk>;
};
/include/ "pq3-esdhc-0.dtsi"
sdhc@2e000 {
compatible = "fsl,p2020-esdhc", "fsl,esdhc";
@ -198,4 +210,6 @@
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
/include/ "pq3-power.dtsi"
};

11
arch/powerpc/boot/dts/fsl/p2041rdb-sdk.dts 100644
View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright 2017-2018 NXP
*/
/include/ "p2041rdb.dts"
/include/ "qoriq-fman-0-sdk.dtsi"
/include/ "qoriq-dpaa-eth.dtsi"
/include/ "qoriq-bman-portals-sdk.dtsi"
/include/ "qoriq-qman1-portals-sdk.dtsi"

21
arch/powerpc/boot/dts/fsl/p3041ds-sdk.dts 100644
View File

@ -0,0 +1,21 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright 2017-2018 NXP
*/
/include/ "p3041ds.dts"
/include/ "qoriq-fman-0-sdk.dtsi"
/include/ "qoriq-dpaa-eth.dtsi"
/include/ "qoriq-bman-portals-sdk.dtsi"
/include/ "qoriq-qman1-portals-sdk.dtsi"
&soc {
fsldpaa: fsl,dpaa {
compatible = "simple-bus", "fsl,dpaa";
ethernet@2 {
status = "disabled";
};
};
};

74
arch/powerpc/boot/dts/fsl/p4080ds-sdk.dts 100644
View File

@ -0,0 +1,74 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright 2017-2018 NXP
*/
/include/ "p4080ds.dts"
/ {
aliases {
phy_rgmii = &phyrgmii;
phy5_slot3 = &phy5slot3;
phy6_slot3 = &phy6slot3;
phy7_slot3 = &phy7slot3;
phy8_slot3 = &phy8slot3;
emi1_slot3 = &p4080mdio2;
emi1_slot4 = &p4080mdio1;
emi1_slot5 = &p4080mdio3;
emi1_rgmii = &p4080mdio0;
emi2_slot4 = &p4080xmdio1;
emi2_slot5 = &p4080xmdio3;
};
};
/include/ "qoriq-fman-0-sdk.dtsi"
/include/ "qoriq-fman-1-sdk.dtsi"
/include/ "qoriq-bman-portals-sdk.dtsi"
/include/ "qoriq-qman1-portals-sdk.dtsi"
&soc {
fsldpaa: fsl,dpaa {
compatible = "simple-bus", "fsl,dpaa";
ethernet@0 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet0>;
};
ethernet@1 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet1>;
};
ethernet@2 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet2>;
};
ethernet@3 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet3>;
};
ethernet@4 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet4>;
};
ethernet@5 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet5>;
};
ethernet@6 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet6>;
};
ethernet@7 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet7>;
};
ethernet@8 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet8>;
};
ethernet@9 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet9>;
};
};
};

41
arch/powerpc/boot/dts/fsl/p5020ds-sdk.dts 100644
View File

@ -0,0 +1,41 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright 2017-2018 NXP
*/
/include/ "p5020ds.dts"
/include/ "qoriq-fman-0-sdk.dtsi"
/include/ "qoriq-bman-portals-sdk.dtsi"
/include/ "qoriq-qman1-portals-sdk.dtsi"
&soc {
fsldpaa: fsl,dpaa {
compatible = "simple-bus", "fsl,dpaa";
ethernet@0 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet0>;
};
ethernet@1 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet1>;
};
ethernet@2 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet2>;
status = "disabled";
};
ethernet@3 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet3>;
};
ethernet@4 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet4>;
};
ethernet@5 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet5>;
};
};
};

68
arch/powerpc/boot/dts/fsl/p5040ds-sdk.dts 100644
View File

@ -0,0 +1,68 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright 2017-2018 NXP
*/
/include/ "p5040ds.dts"
/include/ "qoriq-fman-0-sdk.dtsi"
/include/ "qoriq-fman-1-sdk.dtsi"
/include/ "qoriq-bman-portals-sdk.dtsi"
/include/ "qoriq-qman1-portals-sdk.dtsi"
&soc {
fsldpaa: fsl,dpaa {
compatible = "simple-bus", "fsl,dpaa";
ethernet@0 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet0>;
status = "disabled";
};
ethernet@1 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet1>;
};
ethernet@2 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet2>;
};
ethernet@3 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet3>;
};
ethernet@4 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet4>;
};
ethernet@5 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet5>;
};
ethernet@6 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet6>;
status = "disabled";
};
ethernet@7 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet7>;
};
ethernet@8 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet8>;
};
ethernet@9 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet9>;
};
ethernet@10 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet10>;
};
ethernet@11 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet11>;
};
};
};

48
arch/powerpc/boot/dts/fsl/pq3-power.dtsi 100644
View File

@ -0,0 +1,48 @@
/*
* PQ3 Power Management device tree stub
*
* Copyright 2012-2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
power@e0070 {
compatible = "fsl,mpc8548-pmc";
reg = <0xe0070 0x20>;
etsec1_clk: soc-clk@24 {
fsl,pmcdr-mask = <0x00000080>;
};
etsec2_clk: soc-clk@25 {
fsl,pmcdr-mask = <0x00000040>;
};
etsec3_clk: soc-clk@26 {
fsl,pmcdr-mask = <0x00000020>;
};
};

80
arch/powerpc/boot/dts/fsl/qoriq-bman-portals-sdk.dtsi 100644
View File

@ -0,0 +1,80 @@
/*
* QorIQ BMan Portal device tree stub for 10 portals
*
* Copyright 2011 - 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&bportals {
bman-portal@0 {
cell-index = <0>;
};
bman-portal@4000 {
cell-index = <1>;
};
bman-portal@8000 {
cell-index = <2>;
};
bman-portal@c000 {
cell-index = <3>;
};
bman-portal@10000 {
cell-index = <4>;
};
bman-portal@14000 {
cell-index = <5>;
};
bman-portal@18000 {
cell-index = <6>;
};
bman-portal@1c000 {
cell-index = <7>;
};
bman-portal@20000 {
cell-index = <8>;
};
bman-portal@24000 {
cell-index = <9>;
};
bman-bpids@0 {
compatible = "fsl,bpid-range";
fsl,bpid-range = <32 32>;
};
};

62
arch/powerpc/boot/dts/fsl/qoriq-dpaa-eth.dtsi 100644
View File

@ -0,0 +1,62 @@
/*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2017 NXP
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&soc {
fsldpaa: fsl,dpaa {
compatible = "simple-bus", "fsl,dpaa";
ethernet@0 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet0>;
};
ethernet@1 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet1>;
};
ethernet@2 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet2>;
};
ethernet@3 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet3>;
};
ethernet@4 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet4>;
};
ethernet@5 {
compatible = "fsl,dpa-ethernet";
fsl,fman-mac = <&enet5>;
};
};
};

4
arch/powerpc/boot/dts/fsl/qoriq-fman-0-10g-0.dtsi
View File

@ -35,13 +35,13 @@
fman@400000 {
fman0_rx_0x10: port@90000 {
cell-index = <0x10>;
compatible = "fsl,fman-v2-port-rx";
compatible = "fsl,fman-v2-port-rx","fsl,fman-port-10g-rx";
reg = <0x90000 0x1000>;
};
fman0_tx_0x30: port@b0000 {
cell-index = <0x30>;
compatible = "fsl,fman-v2-port-tx";
compatible = "fsl,fman-v2-port-tx","fsl,fman-port-10g-tx";
reg = <0xb0000 0x1000>;
};

4
arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-0.dtsi
View File

@ -35,13 +35,13 @@
fman@400000 {
fman0_rx_0x08: port@88000 {
cell-index = <0x8>;
compatible = "fsl,fman-v2-port-rx";
compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
reg = <0x88000 0x1000>;
};
fman0_tx_0x28: port@a8000 {
cell-index = <0x28>;
compatible = "fsl,fman-v2-port-tx";
compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
reg = <0xa8000 0x1000>;
};

4
arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-1.dtsi
View File

@ -35,13 +35,13 @@
fman@400000 {
fman0_rx_0x09: port@89000 {
cell-index = <0x9>;
compatible = "fsl,fman-v2-port-rx";
compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
reg = <0x89000 0x1000>;
};
fman0_tx_0x29: port@a9000 {
cell-index = <0x29>;
compatible = "fsl,fman-v2-port-tx";
compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
reg = <0xa9000 0x1000>;
};

4
arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-2.dtsi
View File

@ -35,13 +35,13 @@
fman@400000 {
fman0_rx_0x0a: port@8a000 {
cell-index = <0xa>;
compatible = "fsl,fman-v2-port-rx";
compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
reg = <0x8a000 0x1000>;
};
fman0_tx_0x2a: port@aa000 {
cell-index = <0x2a>;
compatible = "fsl,fman-v2-port-tx";
compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
reg = <0xaa000 0x1000>;
};

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