MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT
[ Upstream commit5.4-rM2-2.2.x-imx-squashed564c836fd9
] Commit930beb5ac0
("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non coherent DMA because of a wrong allocation alignment. Fixes:930beb5ac0
("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Sasha Levin <sashal@kernel.org>
parent
b86434c072
commit
751930560e
|
@ -862,6 +862,7 @@ config SNI_RM
|
||||||
select I8253
|
select I8253
|
||||||
select I8259
|
select I8259
|
||||||
select ISA
|
select ISA
|
||||||
|
select MIPS_L1_CACHE_SHIFT_6
|
||||||
select SWAP_IO_SPACE if CPU_BIG_ENDIAN
|
select SWAP_IO_SPACE if CPU_BIG_ENDIAN
|
||||||
select SYS_HAS_CPU_R4X00
|
select SYS_HAS_CPU_R4X00
|
||||||
select SYS_HAS_CPU_R5000
|
select SYS_HAS_CPU_R5000
|
||||||
|
|
Loading…
Reference in New Issue