redonkable
/
alistair23-linux
1
0
Fork 0
Code Releases Activity

MLK-24667-3 perf vendor: add bandwidth usage metric for i.MX8QM DDR Perf 

Add bandwidth usage metric for i.MX8QM DDR Perf.

Test Report:
------------------------------------------------------
root@imx8qmmek:~# ./perf list metric

List of pre-defined events (to be used in -e):

Metrics:

  imx8qm-ddr0-all-r
       [imx8qm: bytes of all masters read from ddr0]
  imx8qm-ddr0-all-w
       [imx8qm: bytes of all masters write to ddr0]
  imx8qm-ddr0-bandwidth-usage
       [imx8qm: percentage of bandwidth usage for ddr0]
  imx8qm-ddr1-all-r
       [imx8qm: bytes of all masters read from ddr1]
  imx8qm-ddr1-all-w
       [imx8qm: bytes of all masters write to ddr1]
  imx8qm-ddr1-bandwidth-usage
       [imx8qm: percentage of bandwidth usage for ddr1]
------------------------------------------------------
root@imx8qmmek:~# ./perf stat -a -I 1000 -M imx8qm-ddr0-bandwidth-usage dd if=/dev/zero of=/dev/null bs=1M count=1000000
     1.000137560            8403160      imx8_ddr0/read-cycles/    #     11.9 %  imx8qm-ddr0-bandwidth-usage
     1.000137560           86499449      imx8_ddr0/write-cycles/
     1.000137560         1000137560 ns   duration_time
     2.000542875            8818984      imx8_ddr0/read-cycles/    #     10.5 %  imx8qm-ddr0-bandwidth-usage
     2.000542875           74883499      imx8_ddr0/write-cycles/
     2.000542875         1000405315 ns   duration_time
     3.000839188            8604400      imx8_ddr0/read-cycles/    #      9.6 %  imx8qm-ddr0-bandwidth-usage
     3.000839188           68284175      imx8_ddr0/write-cycles/
     3.000839188         1000296313 ns   duration_time
--------------------------------------------------------
root@imx8qmmek:~# ./perf stat -a -I 1000 -M imx8qm-ddr1-bandwidth-usage dd if=/dev/zero of=/dev/null bs=1M count=1000000
     1.000129435           15152856      imx8_ddr1/read-cycles/    #     14.5 %  imx8qm-ddr1-bandwidth-usage
     1.000129435          100669236      imx8_ddr1/write-cycles/
     1.000129435         1000129435 ns   duration_time
     2.000521875           15463356      imx8_ddr1/read-cycles/    #     13.4 %  imx8qm-ddr1-bandwidth-usage
     2.000521875           91710077      imx8_ddr1/write-cycles/
     2.000521875         1000392440 ns   duration_time
     3.000794688           15773560      imx8_ddr1/read-cycles/    #     12.7 %  imx8qm-ddr1-bandwidth-usage
     3.000794688           85948507      imx8_ddr1/write-cycles/
     3.000794688         1000272813 ns   duration_time

Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Joakim Zhang 2020-09-01 21:44:55 +08:00
parent 93b3f99c40
commit f7f6266daf
1 changed files with 18 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8qm-ddr-uncore.json
View File

@ -1,4 +1,13 @@
[
{
"PublicDescription": "lpddr4 mek board bandwidth usage",
"BriefDescription": "imx8qm: percentage of bandwidth usage for ddr0",
"MetricName": "imx8qm-ddr0-bandwidth-usage",
"MetricExpr": "(( imx8_ddr0\\/read\\-cycles\\/ + imx8_ddr0\\/write\\-cycles\\/) * 4 * 4 / duration_time) / (800 * 1000000 * 4 * 4)",
"MetricGroup": "i.MX8QM_DDR_MON",
"ScaleUnit": "1e2%",
"SocName": "i.MX8QM"
},
{
"PublicDescription": "Calculate bytes all masters read from DDR based on read-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.",
"BriefDescription": "imx8qm: bytes of all masters read from ddr0",
@ -15,6 +24,15 @@
"MetricGroup": "i.MX8QM_DDR_MON",
"SocName": "i.MX8QM"
},
{
"PublicDescription": "lpddr4 mek board bandwidth usage",
"BriefDescription": "imx8qm: percentage of bandwidth usage for ddr1",
"MetricName": "imx8qm-ddr1-bandwidth-usage",
"MetricExpr": "(( imx8_ddr1\\/read\\-cycles\\/ + imx8_ddr1\\/write\\-cycles\\/) * 4 * 4 / duration_time) / (800 * 1000000 * 4 * 4)",
"MetricGroup": "i.MX8QM_DDR_MON",
"ScaleUnit": "1e2%",
"SocName": "i.MX8QM"
},
{
"PublicDescription": "Calculate bytes all masters read from DDR based on read-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.",
"BriefDescription": "imx8qm: bytes of all masters read from ddr1",