We don't need holding mutex when accessing registers in display engine
units, because KMS is the only relevant client driver and it has ww mutex
mechansim to ensure there is no race condition on the CRTC resources.
Also, we are naturally safe when the driver initializes the units at the
probe and system power management stages.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Implement Blt engine as DRM renderer.
Add dpu blit engine device. And as dpu bliteng has
no device tree node, so to set dpu's of_node as the
platform data for imx-drm component compare_of.
Signed-off-by: Meng Mingming <mingming.meng@nxp.com>
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
Acked-by: Liu Ying <victor.liu@nxp.com>
This patch sets display clock's parent to bypass clock when display
encoder type is TMDS, otherwise, to pll clock when other types of
encoder.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The dpu is found in i.MX8qm/qxp SoCs.
It has a display controller and a blit engine to support graphics.
This patch adds dpu common driver support.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The new imx folder may contain ipu-v3 and dpu common drivers.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
[ Aisheng: fix source path ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Liu Ying