When CONFIG_PM_SLEEP is disabled, the suspend and resume hooks
are implemented as dummy functions, but GCC will report below
build warnings:
drivers/gpu/imx/lcdif/lcdif-common.c:731:12: warning: ‘imx_lcdif_suspend’ defined but not used [-Wunused-function]
static int imx_lcdif_suspend(struct device *dev)
^
drivers/gpu/imx/lcdif/lcdif-common.c:735:12: warning: ‘imx_lcdif_resume’ defined but not used [-Wunused-function]
static int imx_lcdif_resume(struct device *dev)
^
So remove these dummy functions to avoid these build warnings.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
According to the design spec for IMX8MN platform, the GPR reset
module for DISPMIX has some changes. So the reset code should be
adjusted accordingly. This is a temporary solution and will be
improved later.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
The 16bpp BGR order pixel formats 'DRM_FORMAT_ABGR1555' and
'DRM_FORMAT_XBGR1555' also require to be re-ordered to RGB
order for display, just like the format 'DRM_FORMAT_BGR565'
does.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit f5cc4f4699570fe697d21cb47c54aa91b82c8458)
According to LCDIF specification, the input pixel data
width and the output pixel data width can be different,
and this conversion is done by LCDIF automatically. So
config the output data width according to the requested
bus format from the encoder, instead to be same with the
input pixel data width.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit bfd27f6d71d86a7f2fc8314f082565db3682b925)
According to the LCDIF specification, the Legacy Mode does not
support cropping function in the horizontal direction, so add
Pigeon Mode which can support this kind of function. And when
enable this mode, the legacy horizontal timings configuration
should use stride value but not the active width, and related
pigeon configuration should use the active width but not the
stride value.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit e6da9542693dd585972897f62748a101f5726a74)
Change the 'rpm_suspended' field to be an atomic type from
boolean type to make it have the counting ability which can
help to detect and avoid runtime suspend and resume calls
mismatch caused problems.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit dece6fbe51f9c0ea3cd42c52e1c174bd26ae70f1)
Implement the suspend()/resume() callbacks to support system
power management functions for LCDIF.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 7e00487012753cb370eab4ff5c05f76f7361297f)
After the DISPMIX power domain enabled, all the related registers
will drop their values once runtime pm suspend called. So in the
pm runtime resume process, the LCDIF de-reset and some init jobs
need to be done, and these jobs are no longer necessary to be done
during probe stage anymore.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit f83aaaecaeb54d8b1231be2cb7175ce58682dae7)
Add an function to get the LCDIF controller supported bus
formats according to the pixel format bpp. And change the
bus format sanity check in the plane's atomic check to see
if the bus format required by the peripheral attached to
LCDIF can be supported by LCDIF.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
After adding LCDIF DRM/KMS driver, there will be a Kconfig recursive
dependency loop:
drivers/media/v4l2-core/Kconfig:7:error: recursive dependency detected!
drivers/media/v4l2-core/Kconfig:7: symbol VIDEO_V4L2 depends on I2C
drivers/i2c/Kconfig:8: symbol I2C is selected by FB_DDC
drivers/video/fbdev/Kconfig:63: symbol FB_DDC depends on FB
drivers/video/fbdev/Kconfig:12: symbol FB is selected by DRM_KMS_FB_HELPER
drivers/gpu/drm/Kconfig:75: symbol DRM_KMS_FB_HELPER depends on DRM_KMS_HELPER
drivers/gpu/drm/Kconfig:69: symbol DRM_KMS_HELPER is selected by DRM_IMX
drivers/gpu/drm/imx/Kconfig:2: symbol DRM_IMX depends on IMX_LCDIF_CORE
drivers/gpu/imx/lcdif/Kconfig:1: symbol IMX_LCDIF_CORE depends on RESET_CONTROLLER
drivers/reset/Kconfig:5: symbol RESET_CONTROLLER is selected by QCOM_SCM
drivers/firmware/Kconfig:218: symbol QCOM_SCM is selected by VIDEO_QCOM_VENUS
drivers/media/platform/Kconfig:482: symbol VIDEO_QCOM_VENUS depends on V4L_MEM2MEM_DRIVERS
drivers/media/platform/Kconfig:165: symbol V4L_MEM2MEM_DRIVERS depends on VIDEO_V4L2
Making IMX_LCDIF_CORE select RESET_CONTROLLER instead of depending on it
breaks this loop.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
The LCDIF core driver is responsible to provide controller
registers configuration and create the platform devices for
the child port nodes. And the platform devices later will
attach to the corresponding DRM/KMS drivers via name match.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
[ Aisheng: Kconfig & Makefile update for a clean base ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
The new imx folder may contain ipu-v3 and dpu common drivers.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
[ Aisheng: fix source path ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
The new imx folder may contain ipu-v3 and dpu common drivers.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
[ Aisheng: fix source path ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
The new imx folder may contain ipu-v3 and dpu common drivers.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
[ Aisheng: fix source path ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Fast-forward imx8_dprc driver from imx_4.14.y.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
[ Liu Ying: scfw call updates and other small tweaks for upgrade]
The new imx folder may contain ipu-v3 and dpu common drivers.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
[ Aisheng: fix source path ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
To make sure SCU misc settings are in valid status at system resume
stage, let's initialize them in dpu_resume().
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The KACHUNK_CNT SCU misc setting is for DPU blit engine's prefetch engine.
It represents how many cycles are needed to trigger prefetch engine after
DPU shadow being loaded. Set it to be 32, which is recommended and tested.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The SCU misc settings of DC subsystem contain pixel link settings
and other settings, like DC sync mode and KACHUNK_CNT. So, it would
be better to rename dpu_pxlink_init() to dpu_sc_misc_init(), which
includes initialization code for all SCU misc settings of DC subsystem.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The function dpu_sc_misc_init() actually gets the SCU handle only.
So, renaming it to dpu_sc_misc_get_handle() better reflects what it does.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The LVDS encoder driver for i.MX8qxp SoC needs to enable/disable pixel link
in order to meet some sequence requirements, otherwise, display artifacts
will be seen on LVDS display. This patch avoids to enable/disable pixel
link in the FrameGen driver for this special encoder.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
i.MX8qxp LDB dual channel mode uses two LDB channels from two LDB
instances, while i.MX8qm LDB uses two LDB channels from one LDB
instance. So, this patch adds flag has_dual_ldb in struct dpu_data
so that it can be used to tell the difference.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch caches encoder_type in struct dpu_framegen when we
call framegen_cfg_videomode(). This cached type can be used
later when determining whether to enable pixel link in the
FrameGen driver or not.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
As DPU fetchunits support ITU601(limited range)/ITU601_FR(full range)
and ITU709(limited range) YUV to RGB color space conversions, we may
add color encoding and color range properties support for planes.
Considering software backward compatibility, the default color encoding
is set to ITU601 with full color range.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds mulitple pixel blend modes for DPU plane.
The modes are "None", "Pre-multiplied" and "Coverage".
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Without the new blend modes("None", "Pre-multiplied" and "Coverage")
introduced in the below commit, the old userspace assumes alpha in
pixel is per-premultiplied by default. So, let's support the default
blend mode properly.
commit a5ec8332d4 ("drm: Add per-plane pixel blend mode property")
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds extdst_pixengcfg_syncmode_master() helper support
so that the callers may control if a extdst is master or slave
when it works in sync mode. The bit16 of extdst's PIXENGCFG_STATIC
register controls this and it's a part of sync mode fixup logic.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Bit7 of framegen's SECSTATCONFIG register is used to control
the sync mode fixup logic implemented in framegen. This patch
adds framegen_syncmode_fixup() helper so that the callers
may enable/disable the fixup logic for a framegen.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Store9 unit can be shared bewteen display engine(for sync mode fixup)
and blit engine. It's proper to get the store resource in the DPU
common driver and then provide it to client platform device via
platform data.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Bit16 of store9's PIXENGCFG_STATIC register is used to control
the sync mode fixup logic implemented in store9. So, let's
add store9 support in the DPU core driver and export a function
for users to enable/disable the fixup logic.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch sets master stream id to be 1 for i.MX8QM DPU.
The master stream id is used when FrameGen works in sync mode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds pixel combiner support in the DPU core driver.
Users may get and enable/disable/control a pixel combiner instant
via tcon functions and may tell if it is needed in a specific usecase
via the dpu_get_syncmode_min_prate() and dpu_get_singlemode_max_width()
helpers.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds side-by-side support for tcon so that
two tcons can participate in the dual display streams
to work with pixel combiner to drive a high pixel rate
display.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds side-by-side support for framegen so that
two framegens can work in sync mode to participate in the
dual display streams to drive a high pixel rate display
via a pixel combiner.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds helper dpu_pxlink_set_dc_sync_mode() support
so that callers may enable or disable DC sync mode.
In DC sync mode, high pixel rate video mode can be supported
by combining two display streams together.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds tcon_is_master/slave() helpers support so that
callers may know if a tcon is a master or slave tcon.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds extdst_is_master() helper support so that
callers may know if a extdst is a master extdst or not.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds framegen_is_master/slave() helpers support so that
callers may know if a framegen is a master or slave framegen.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds helper dpu_get_master_stream_id() support
so that callers may know the master stream when FrameGen
works in sync mode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch introduces master_stream_id flag in struct dpu_data
so that master stream can be chosen when FrameGen works in sync mode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds a new di_grp_id entry in display client pdev's data
so that the relevant display platform driver may know the display
group ID of the display device.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The CRTC background should be full screen instead of partial
screen, because the DRM core is likely to add configurable
background color support in the future. We may cover the full
screen with ConstFrame0/1, upon which builds planes. With this,
it is easier to compute each plane's layer offset vs CRTC start
point and all ConstFrame units can be controlled by CRTC.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds two helpers to get and clear FrameGen secondary channel
status respectively. Via the two helpers, users may know if there is
empty FIFO read request on this channel or not after getting the status.
And, if yes, users may choose to clear the status. According to the IP
spec, the empty FIFO read request indicates that data stream from a Fetch
unit(e.g., AXI bandwidth not sufficient) fell down. Assuming the display
driver sets things up properly, the falling down is very likely caused by
the insufficient AXI bandwidth, that is, display underrun.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
To workaround the errata TKT320950, DPR/PRG need to evade the first dumb frame
which is generated by DPU. The way we achieve that is to bypass TCON(but set
the TCON sync signals and KA_CHUCK strobe signal up) before enabling the DPU
display controller, and then 1) enable the display controller, 2) wait for the
frame index starting to move and 3) finally switch TCON to operation mode.
Steps 1) to 3) should be done within a frame, so we disable local irq and
preemption to make sure we don't relinquish CPU during the procedure.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
We don't need holding mutex when accessing registers in display engine
units, because KMS is the only relevant client driver and it has ww mutex
mechansim to ensure there is no race condition on the CRTC resources.
Also, we are naturally safe when the driver initializes the units at the
probe and system power management stages.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Implement Blt engine as DRM renderer.
Add dpu blit engine device. And as dpu bliteng has
no device tree node, so to set dpu's of_node as the
platform data for imx-drm component compare_of.
Signed-off-by: Meng Mingming <mingming.meng@nxp.com>
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
Acked-by: Liu Ying <victor.liu@nxp.com>
This patch sets display clock's parent to bypass clock when display
encoder type is TMDS, otherwise, to pll clock when other types of
encoder.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The dpu is found in i.MX8qm/qxp SoCs.
It has a display controller and a blit engine to support graphics.
This patch adds dpu common driver support.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The new imx folder may contain ipu-v3 and dpu common drivers.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
[ Aisheng: fix source path ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Fancy Fang