-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEZH8oZUiU471FcZm+ONu9yGCSaT4FAl9rJlYACgkQONu9yGCS
aT6WbRAAga6QVKrO6R4NeKk0fPqKQQoQeTK+phBOFA7jAoX/rIRKyob2Si9BwhBA
F77vZ6HIZ7+e/o35JJQYQbffbHYs0ANuS1oHGqe0vgbh+72Viaan6g7lFOhpx8qf
y0YS7q+hw4WLZB0gGlBM7nkPXRiis32IrEVabQW+t8hmT2lWyutY8E2yFAU60tvI
Tvjm2c2pvHEcHz9MrjEd/jIVxMFnIl42FBTx9bGsbDUCDzBwEvPArS4bNioP7EFJ
O+rrGCNvwtiv0DuKzX1UIZzQ88IROmU3ZjsIlgOwla7xJWv4QDgmPfyAyRI48QhH
PAZQmSntz+y+MP6B3z3ZBrxc2Fx0kCDtugn2P9+2RVUEpheANJ293vUgYTKN9Roy
dHdWHFWNTO9IYpIN0cZjc25db4ULdjerWQrKcCr6ZO8+Ep/0mSzx3lkWjfuUP8Hr
L2RD6rAm259OpPq8xhAcJpJvoQLwGxaBHyr4QYUmRgmNVURoqe9Q0MTZuiyGsXhm
rtcNky9WvmyyI1lJgXi4A+vmsIThCHEstEMycgTejfJ4itIVA9e1ctJVVomWULCn
9oNStBJpmHw0myDCohbKNjeO1UX/erdF9NaoGto5bnfIhcSae1YQEjRB8zKmzbg1
DpgC1f7IZ7q53vfrDGsAjInOcuEwAn/Y5JMLJOL4mdA9j3XlX2o=
=Ot99
-----END PGP SIGNATURE-----
Merge tag 'v5.4.67' into 5.4-2.2.x-imx
This is the 5.4.67 stable release
This updates the kernel present in the NXP release imx_5.4.47_2.2.0 to the
latest patchset available from stable korg.
Base stable kernel version present in the NXP BSP release is v5.4.47.
Following conflicts were recorded and resolved:
- arch/arm/mach-imx/pm-imx6.c
NXP version has a different PM vectoring scheme, where the IRAM bottom
half (8k) is used to store IRAM code and pm_info. Keep this version to
be compatible with NXP PM implementation.
- arch/arm64/boot/dts/freescale/imx8mm-evk.dts
- arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
NXP patches kept to provide proper LDO setup:
imx8mm-evk.dts: 975d8ab07267ded741c4c5d7500e524c85ab40d3
imx8mn-ddr4-evk.dts: e8e35fd0e759965809f3dca5979a908a09286198
- drivers/crypto/caam/caamalg.c
Keep NXP version, as it already covers the functionality for the
upstream patch [d6bbd4eea2]
- drivers/gpu/drm/imx/dw_hdmi-imx.c
- drivers/gpu/drm/imx/imx-ldb.c
- drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c
Port changes from upstream commit [1a27987101], which extends
component lifetime by moving drm structures allocation/free from
bind() to probe().
- drivers/gpu/drm/imx/imx-ldb.c
Merge patch [1752ab50e8] from upstream to disable both LVDS channels
when Enoder is disabled
- drivers/mmc/host/sdhci-esdhc-imx.c
Fix merge fuzz produced by [6534c897fd].
- drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
Commit d1a00c9bb1 from upstream solves the issue with improper error
reporting when qdisc type support is absent. Upstream version is merged
into NXP implementation.
- drivers/net/ethernet/freescale/enetc/enetc.c
Commit [ce06fcb6a6] from upstream merged,
base NXP version kept
- drivers/net/ethernet/freescale/enetc/enetc_pf.c
Commit [e8b86b4d87] from upstream solves
the kernel panic in case if probing fails. NXP has a clean-up logic
implemented different, where the MDIO remove would be invoked in any
failure case. Keep the NXP logic in place.
- drivers/thermal/imx_thermal.c
Upstream patch [9025a5589c] adds missing
of_node_put call, NXP version has been adapted to accommodate this patch
into the code.
- drivers/usb/cdns3/ep0.c
Manual merge of commit [be8df02707] from
upstream to protect cdns3_check_new_setup
- drivers/xen/swiotlb-xen.c
Port upstream commit cca58a1669 to NXP tree, manual hunk was
resolved during merge.
- sound/soc/fsl/fsl_esai.c
Commit [53057bd4ac] upstream addresses the problem of endless isr in
case if exception interrupt is enabled and tasklet is scheduled. Since
NXP implementation has tasklet removed with commit [2bbe95fe6c],
upstream fix does not match the main implementation, hence we keep the
NXP version here.
- sound/soc/fsl/fsl_sai.c
Apply patch [b8ae2bf5cc] from upstream, which uses FIFO watermark
mask macro.
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
This patch increase the DPU single pipe maximum from 1920 to 2560 for
both the DPU common and HDMI/DP.
Signed-off-by: Oliver F. Brown <oliver.brown@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
This patch checks the return value of imx_sc_misc_set_control() called
in dprc_prg_sel_configure() and generates warning dmesg in case the
return value is nonzero. The check makes Coverity happy.
This fixes Coverity issue: CID 10836597.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Sandor Yu <sandor.yu@nxp.com>
This patch checks the return value of imx_sc_misc_set_control() called
in dprc_dpu_gpr_configure() and generates warning dmesg in case the
return value is nonzero. The check makes Coverity happy.
This fixes Coverity issue: CID 10836598.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Sandor Yu <sandor.yu@nxp.com>
Instead of getting scu ipc handle from time to time in helpers
of the driver, we can get it in ->probe() once and cache it in
struct dprc. Also, we should check the return value of
imx_scu_get_handle() to get the handle in case it returns error
code. This makes Coverity happy.
This fixes two Coverity issues: CID 9993376 & CID 9993377.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
This patch adds helper disengcfg_sig_select() support so that
users may select different taps(FrameGen, GammaCor, Matrix or
Dither) to do signature computation. Also, select FrameGen as
the default tap in _dpu_dec_init() and call it in dpu_dec_init().
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
This patch adds signature unit support in the dpu common driver.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
null return value check for of_id to reslove coverity ID 10058073.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit c444dcf0aee821cf42892d03b698008bd1d6f0f5)
In imx_drm_suspend() and imx_drm_resume(), the display
pipeline will be disabled and enabled respectively, so
the correct suspend sequence should be master first to
disable the pipeline, and then the components can be
suspended, and resume sequence is obviously opposite.
So, to satisfy this sequence, use the late system sleep
PM ops to replace normal sleep PM ops for this purpose.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
This is an issue reported by Coverity with CID 10020289. Since
the return ptr by of_match_device may be NULL, its dereference
should check the ptr value to avoid NULL ptr dereference issue.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 1007a41f6b208104cd96d60c133fed255136aaba)
This is an issue reported by Coverity with CID 5433770. Since
the return ptr by of_match_device may be NULL, its dereference
should check the ptr value to avoid NULL ptr dereference issue.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit ecbbbc7eb6f88badb8c8a60399b5460a3a2978c6)
It would be good to check of_match_device() return value in dpu_probe()
in case it returns a NULL pointer. This may avoid NULL pointer dereference
from happening.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Sandor Yu <sandor.yu@nxp.com>
After the atomic plane update, the shadow load should be
enabled to make sure its update can take effect on next
frame in any cases. And this enable is better to be done
in CRTC's atomic_flush() which is called after plane's
atomic_update() is called.
Besides, the shadow load enable in controller enable is
unnecessary, so remove it.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
The dpu common driver creates a irq chip for dpu irqs.
The parent of the irq chip on the i.MX8qm/qxp SoC is the irqsteer.
Since the irqsteer driver may support runtime PM, the dpu common
driver needs to call irq_chip_pm_get/put() where necessary to make
sure power of the irq chip is enabled/disabled properly. This
patch enables the power at the driver probe stage and disables it
at driver remove stage to achieve basic power management support
for the irq chip.
Suggested-by: Andy Duan <fugang.duan@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
After attach multiple power domains, these power domains are
power on since the state is DL_FLAG_PM_RUNTIME & DL_FLAG_RPM_ACTIVE.
The action is expected by the driver to let all power domains
always on.
Fixes: 583c9de66ebf(gpu: imx: Add dpu common driver support)
Reviewed-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
DPU found in i.MX8qxp SoC may drive parallel display via
pixel link with display stream1. The pixel link MST address
of this particular display path is 1 instead of 0. So, this
patch adds DPI encoder support so as to specify the MST
address and also to enable SYNC_CTRL and pixel link MST_VLD.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds MEDIA_BUS_FMT_RGB565_1X30_PADLO format support for
the DPU TCON unit.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
To support system suspend and resume, the system sleep
PM ops of suspend and resume are required to be added
for LCDIFv3 display.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
LCDIF DMA disable should be done before display is
turned off. And enough delay should be added after
DMA disable to make sure it is really done.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Tested-by: Liu Ying <victor.liu@nxp.com>
Some display flicker issue may be observed when doing mode
switch or display disable and enable switch. The frame clear
bit can clear the FIFO data on every vsync blank period to
avoid any affect for next frame display and can solve this
kind of flicker issues.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Tested-by: Liu Ying <victor.liu@nxp.com>
In the coming patch, we would wait for FrameGen counter moving in
->atomic_disable() to get synchronization before disabling DPRC
repeat_en. It appears that waiting for 50ms for video mode
1920x1080@24Hz is not enough in this case and increasing timeout
to 100ms looks ok.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 910d3b8759bb8635b2b9d563cc934748e5aeaa81)
This patch adds helper dprc_disable_repeat_en() so that callers
may disable DPRC repeat_en.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 37b68e353a2dc8e3370fb27a4aebf42f5da63047)
No one is using pin-off operations, so let's remove them.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 7243d962bb29a35ba4ee1328bdb5d011cf1471cd)
The current lcdifv3 common driver uses of_device_id data to determine
the data enable signal polarity of LCDIFv3. As required by LDB, the
polarity has to be "de_invert", so this patch introduces a compatible
string for LDB's LCDIFv3 and sets the "de_invert" flag to true in the
relevant of_device_id data.
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
There could be multiple LCDIFv3 instances in a SoC, so client
specific pdev id is needed. With this supported, LCDIFv3
instance1(for MIPI DSI) and instance2(for LDB) in i.MX8MP SoC
can add client pdev at the same time without id confliction
and thus can be both probed successfully.
As the i.MX8MP EVK bootloader can do splash screen with MIPI DSI,
we need properly reset LCDIFv3 instance1 in the LCDIFv3 driver,
otherwise, the LCDIFv3 instance2 cannot work(the reason behind
needs investigation). This also requires the two instances can
be probed at same time so that instance1 can be reset.
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Change LCDIFv3 burst size from 128B to 256B
to improve lpddr4 efficiency by adding about 200MB
Signed-off-by: Jian Li <jian.li@nxp.com>
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
The LCDIFv3 panic threshold enable register should be
'LCDIFV3_INT_ENABLE_D1' instead of 'LCDIFV3_PANIC0_THRES'.
So correct it.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
According to the LCDIFv3 specification, the input pixel
FIFO size is 8K(512 * 128bit) and the panic threshold
low and high should be chosen from 0 to 511, so correct
the thresholds calculation.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
The LCDIFv3 core driver is responsible to provide
controller registers configuration and create the
platform devices for the child port nodes. And the
platform devices later will attach to the related
DRM/KMS drivers via name match. And the LCDIFv3 is
completely different from the LCDIF controller
which is used on imx8mm and imx8mn platforms.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
When built the driver as module, this typo error can
be found by compiler with below build error reported:
In file included from drivers/gpu/imx/lcdif/lcdif-common.c:20:
drivers/gpu/imx/lcdif/lcdif-common.c:78:25: error: ‘lcdif_dt_ids’ undeclared here (not in a function); did you mean ‘imx_lcdif_dt_ids’?
78 | MODULE_DEVICE_TABLE(of, lcdif_dt_ids);
| ^~~~~~~~~~~~
./include/linux/module.h:227:15: note: in definition of macro ‘MODULE_DEVICE_TABLE’
227 | extern typeof(name) __mod_##type##__##name##_device_table \
| ^~~~
./include/linux/module.h:227:21: error: ‘__mod_of__lcdif_dt_ids_device_table’ aliased to undefined symbol ‘lcdif_dt_ids’
227 | extern typeof(name) __mod_##type##__##name##_device_table \
| ^~~~~~
drivers/gpu/imx/lcdif/lcdif-common.c:78:1: note: in expansion of macro ‘MODULE_DEVICE_TABLE’
78 | MODULE_DEVICE_TABLE(of, lcdif_dt_ids);
| ^~~~~~~~~~~~~~~~~~~
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Another coming patch will wait for framegen secondary channel syncup
for non-sync mode cases. It appears that waiting for 50ms for video
modes like 1920x1080p@24 and 1920x1080p@30 is not enough. So, this
patch increases the timeout value to 100ms.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Since of_irq_count() is not exported as a symbol, we cannot
find it's definition when imx-dpu-core is built as a module.
To address this issue, this patch calls platform_irq_count()
to get irq count instead.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
* origin/display/prefetch:
MLK-21378-2 gpu: imx: Add imx8_dprc support
MLK-21378-1 gpu: imx: Add imx8_prg support
gpu: Move ipu-v3 to imx folder
drm/imx: Revert a patch which merges imx-drm-core and ipuv3-crtc in one module
* origin/display/pc:
gpu: imx: Add imx8 pixel combiner support
gpu: Move ipu-v3 to imx folder
drm/imx: Revert a patch which merges imx-drm-core and ipuv3-crtc in one module
Any CRTC driver should use the crtc_clock instead of clock value from
drm_display_mode structure, since the crtc_clock might differ from the
actual pixel clock needed by that mode.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
The bit DIV0 of register STORE9_STATIC is used as a control bit
to fix the unsynchronization issue bewteen two display streams
in FrameGen side-by-side mode, which is introduced from an ECO
operation for the display controller. The bit has to be one
when the side-by-side mode is enabled. And, it has to be zero
when the mode is disabled, otherwise, a single display stream
cannot startup correctly. Since the DPU common driver initializes
the register for us at the driver probe stage and system resume
stage, we may remove the same initialization logic of our own.
Without this patch, as the DPU blit engine DRM driver is resumed
relatively late, the bit would be overwritten to be zero at the
driver's ->resume() callback, which causes the display controller
cannot be correctly resumed from FrameGen side-by-side mode and
content ExtDst shadow load done event from the slave stream won't
come.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
video playback cause system hang with Wayland g2d compositor,
this also can be reproduced with Android G2D HWComposer.
the problem is second prg not handled between GPU and video.
need re-enable dprc & prg pipes when modifier changed.
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
(cherry picked from commit 8ca7df522719ac94d126d34618cc9d25a2798660)
auto-trigger cause dpr hang in inital blitter implementation,
the problem is dpr repeat mode has conflict with command sequencer.
as proposed by design, blitter need do manual trigger for each process:
dpr register -> dpr run -> seeris register -> seeris trigger -> sync
frstly this patch removed dprc first frame handler from dpu blitter,
then removed dpr repeat, and enable dpr run for each blit processing.
also add sync flag to avoid the duplicated calling to dpu_be_wait.
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
(cherry picked from commit 04eb0533d5008ab20aae1e0acb9e4d8b910d82e5)
chrome browser hang is reproduced with mouse connected,
the first frame handler trigger the problem in below scenario:
tile (dprc-enable) --> linear (dprc->disable) --> tile (handle first frame wrongly).
need_handle_start is set following dprc_enable, need reset it with dprc_disable.
fix event trigger as previous implementation does not flush command sequence,
that will cause the obvious flicker when run glmark2 in full-screen.
also reduce bitter delay to 30us to improve blitter performance.
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
(cherry picked from commit 9b5700a98e9b12b9d0119a67e45251a8d2405628)
resume will increase unlock counter, max allowed value is 15.
suspend need decrease unlock counter to avoid overflow panic.
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
(cherry picked from commit 0582cd50ed70f932158fe20d6caf2f4ad68eabf0)
(cherry picked from commit a9b740f91b05398564bf776e4f1959e44c876938)
Add struct drm_imx_dpu_frame_info.
Configure dprc to enable prefetch for dpu blit.
Configure prefetch with source frame info for dpu blit.
Signed-off-by: Meng Mingming <mingming.meng@nxp.com>
The new imx folder may contain ipu-v3 and dpu common drivers.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
[ Aisheng: fix source path ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
After the dispmix reset driver development, the reset flow
is better to be replaced by using this driver to hide the
reset details for all the dispmix submodules, and whose
driver code for reset can become platform independent.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Andrey Zhizhikin