This makes it easier to reference the CPU nodes afterwards.
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
The skeleton.dtsi file is now deprecated as noted in commit 9c0da3cc61
("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). The SoCFPGA
device trees already contain the nodes that are defined in skeleton.dtsi
(#address-cells, #size-cells, chosen, aliases, memory).
Including skeleton.dtsi is useless and will produce the following
warning when compiled with W=1:
Node /memory has a reg or ranges property, but no unit name
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Node eccmgr has a unit name, but do not have a reg property as only the
child nodes do have this property. Likewise the usbphy node do not have
a reg property. This will trigger the following warnings when compiled
with W=1:
Node /soc/eccmgr@ffd08140 has a unit name, but no reg property
Node /soc/usbphy@0 has a unit name, but no reg property
Remove the superfluous unit names.
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Most clock nodes in Arria5, Cyclone5 and Arria10 have a reg property but
does not have a unit name. This will trigger several warnings like this
one (when compiled with W=1):
Node /soc/clkmgr@ffd04000/clocks/periph_pll has a reg or ranges
property, but no unit name
Add the corresponding unit name to each node.
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Add h2f and lwh2f bridges.
Add base FPGA Region to support DT overlays for FPGA programming.
Add l3regs.
Signed-off-by: Alan Tull <atull@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: removed fpga-bridges, ranges, and reset-names
Adjust regs property for the FPGA manager data register to
properly reflect that it is a single 32 bit register.
Signed-off-by: Dalon Westergreen <dwesterg@altera.com>
Signed-off-by: Alan Tull <atull@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Enable the bit(22) shared-override bit for the SoCFPGA family. While at it,
enable the prefetch-data and prefetch-instr settings for the Arria10.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
These are all the updates to device tree files for 32-bit platforms,
plus a couple of related 64-bit updates:
New SoC support:
- Allwinner A83T
- Axis Artpec-6 SoC
- Mediatek MT7623 SoC
- TI Keystone K2G SoC
- ST Microelectronics stm32f469
New board or machine support:
- ARM Juno R2
- Buffalo Linkstation LS-QVL and LS-GL
- Cubietruck plus
- D-Link DIR-885L
- DT support for ARM RealView PB1176 and PB11MPCore
- Google Nexus 7
- Homlet v2
- Itead Ibox
- Lamobo R1
- LG Optimus Black
- Logicpd dm3730
- Raspberry Pi Model A
Other changes include
- Lots of updates for Qualcomm APQ8064, MSM8974 and others
- Improved support for Nokia N900 and other OMAP machines
- Common clk support for lpc32xx
- HDLCD display on ARM
- Improved stm32f429 support
- Improved Renesas device support, r8a779x and others
- Lots of Rockchip updates
- Samsung cleanups
- ADC support for Atmel SAMA5D2
- BCM2835 (Raspberry Pi) improvements
- Broadcom Northstar Plus enhancements
- OMAP GPMC rework
- Several improvements for Atmel SAMA5D2 / Xplained
- Global change to remove inofficial "arm,amba-bus" compatible string
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIVAwUAVu67PmCrR//JCVInAQIZlA//UV7DK8tHNvLCuHBX8MnW5xxljUWFCoFp
Zsi9LJj+KDIE+rpY65n75+il+rT1ZcgaITzH+Qvaq75f51ZwW7HY5jHiPYsINa80
oMtbdWlnpNIH48jD5yMKaDTE8md7lZ8tgA//6aw1doDx2LYX4D1QRG6XI1OC6E62
OjlzXkTTe50Aowi6aMQz4PZQM89m09FT0aw/Qsokh0fcW8oXhXcJSlFgLF/tZUYs
VU4oWshUX2/VW3ShXlAJdrItpdDIogwZtDS7xKXmk6AHfapLb7s4HuEOInqbeOa7
QWTjtoVj6ZHyeVptyn6kj5+xOdL4bXAT4Kg2TctF1iv0I6XG8CKflNqOJt2wLR1M
DP0VQXK0TmKCeI+vbRhniLRP7EPYp4N9KFAe6M6aVP3nKYX81EqWdtPjuwp7GxAC
sIGad2ocynKW4Eb4xOD2/5EwzkhwHv7SPQTCyCyQo8ILGN5MOSBZJOC1kXATTtbq
u7LbOLyFMeWPJFYZyPxe79MwiX0dfJekrZYQ1tYL3MEQqQNmbY6+r+6QLMhT+iSj
SE1oBaAReOuZUquiBEt398OvdfQ/n+F5BasKKCojXuhueNO3+rY7mT5X/vmOs2eh
CUpfl766CixaZmF6p8es1Qeu64ASODbPiOw3Dv5Cgwcbfy/C3b3ccty0zazlOaNJ
Sm6VXU3RavA=
=RLUc
-----END PGP SIGNATURE-----
Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Arnd Bergmann:
"These are all the updates to device tree files for 32-bit platforms,
plus a couple of related 64-bit updates:
New SoC support:
- Allwinner A83T
- Axis Artpec-6 SoC
- Mediatek MT7623 SoC
- TI Keystone K2G SoC
- ST Microelectronics stm32f469
New board or machine support:
- ARM Juno R2
- Buffalo Linkstation LS-QVL and LS-GL
- Cubietruck plus
- D-Link DIR-885L
- DT support for ARM RealView PB1176 and PB11MPCore
- Google Nexus 7
- Homlet v2
- Itead Ibox
- Lamobo R1
- LG Optimus Black
- Logicpd dm3730
- Raspberry Pi Model A
Other changes include
- Lots of updates for Qualcomm APQ8064, MSM8974 and others
- Improved support for Nokia N900 and other OMAP machines
- Common clk support for lpc32xx
- HDLCD display on ARM
- Improved stm32f429 support
- Improved Renesas device support, r8a779x and others
- Lots of Rockchip updates
- Samsung cleanups
- ADC support for Atmel SAMA5D2
- BCM2835 (Raspberry Pi) improvements
- Broadcom Northstar Plus enhancements
- OMAP GPMC rework
- Several improvements for Atmel SAMA5D2 / Xplained
- Global change to remove inofficial "arm,amba-bus" compatible
string"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (350 commits)
ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus"
ARM: dts: artpec: dual-license on artpec6.dtsi
ARM: dts: ux500: add synaptics RMI4 for Ux500 TVK DT
arm64: dts: juno/vexpress: fix node name unit-address presence warnings
arm64: dts: foundation-v8: add SBSA Generic Watchdog device node
ARM: dts: at91: sama5d2 Xplained: add leds node
ARM: dts: at91: sama5d2 Xplained: add user push button
ARM: dts: at91: sama5d2 Xplained: set pin muxing for usb gadget and usb host
ARM: dts: stm32f429: Enable Ethernet on Eval board
ARM: dts: omap3-sniper: TWL4030 keypad support
Revert "ARM: dts: DRA7: Add dt nodes for PWMSS"
ARM: dts: dm814x: dra62x: Disable wait pin monitoring for NAND
ARM: dts: dm814x: dra62x: Fix NAND device nodes
ARM: dts: stm32f429: Add Ethernet support
ARM: dts: stm32f429: Add system config bank node
ARM: dts: at91: sama5d2: add nand0 and nfc0 nodes
ARM: dts: at91: sama5d2: add dma properties to UART nodes
ARM: dts: at91: sama5d2 Xplained: Correct the macb irq pinctrl node
ARM: dts: exynos: Don't overheat the Odroid XU3-Lite on high load
ARM: dts: exynos: Add cooling levels for Exynos5422/5800 CPUs
...
The compatible string "simple-bus" is well defined in ePAPR, while
I see no documentation for the "arm,amba-bus" arnywhere in ePAPR or
Documentation/devicetree/.
DT is also used by other projects than Linux kernel. It is not a
good idea to rely on such an unofficial binding.
This commit
- replaces "arm,amba-bus" with "simple-bus"
- drops "arm,amba-bus" where it is used along with "simple-bus"
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
The socfpga.dtsi explicitly enabled MMC support, but not all boards are
equiped with an MMC card. There are setups which only have QSPI NOR.
Therefore, disable the MMC support on socfpga.dtsi level and enable it
on per-board basis.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alan Tull <atull@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Thor Thayer <tthayer@altera.com>
Cc: Vince Bridgers <vbridgers2013@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
The sorting policy for this file is alphabetically.
Reorder all nodes, that are out of place.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Add FPGA manager to device tree for SoCFPGA.
Signed-off-by: Alan Tull <atull@opensource.altera.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
- Add DTS property "altr,modrst-offset" for reset driver to
use
- Add updated reset defines for the reset driver
- Add reset property for EMACs on Arria10
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVyBZjAAoJEBmUBAuBoyj0IWEP/jlmY2g+/lloIRI7Yu49wncy
xOnFX5+1N6NoKaPvSiNO9w2i4QMMw9nCs/+UccQqbjiOS2ggFuU12ODxSw91PadI
FbDuMgsjXzeCcUK4p9sv+S3YK0FnajLuuB4EI9UhCn1nOnGi8Qs6QKKLnwwCvF+X
1JB5cWcEz48SRl9p1K7ZmxvBJIjrhghl16sIBfNPWNzin+yjDBCvf2qtLJyzMz+z
bG+Q3aztrr0vtt7EgEUNaeEZHmseuKtFVLFzL+d4L/HtpnczcNNmbhZDjZZuZjmc
1jLMHZO7/W28njkmU4rYlQPeA4skKn1/a0BQ6S/UEC/RBNsFgkRGBgfsloslofuO
kSaTW02g1ekxRPnZZNU+iqFZ3zHTbq609aCF/x48vbl5Ti6xB+RH5g7XGJSxFeRC
4aEIMaLxyrCTkqN2bh6I4ABLAJnzD4+IcofnLioLiDJOlo0BqEI0mh9KMBHDBoKM
uvltqwaVuWdMxzJue7SITAobsThkp3IS7ZU05JqKM/y1Qpu7DofplYTSQVN/oaWP
3XS8M+ZMgAz9o8E67hv/54NX3PM8zw1fbBW1brCKeXdFqGhcww75aLlcfwBTLVaU
hYDBRMMj2YkRCGjc2mFqlPozy4ovuqQ2ILKAh6/cqWiww1dV0hIw7mP50On7sLU8
Ip/H2H5Q5OCk1but68iq
=dKt6
-----END PGP SIGNATURE-----
Merge tag 'socfpga_dts_for_v4.3_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt
SoCFPGA DTS updates for v4.3, take 2
- Add DTS property "altr,modrst-offset" for reset driver to
use
- Add updated reset defines for the reset driver
- Add reset property for EMACs on Arria10
* tag 'socfpga_dts_for_v4.3_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: socfpga: dts: Add resets for EMACs on Arria10
ARM: socfpga: dts: add "altr,modrst-offset" property
dt-bindings: Add reset manager offsets for Arria10
Signed-off-by: Olof Johansson <olof@lixom.net>
The "altr,modrst-offset" property represents the offset into the reset manager
that is the first register to be used by the driver to bring peripherals out
of reset.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
The gates for the clocks coming out of the sdram pll
were missing. The change adds the missing nodes to
the device tree.
Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
The l3_sp_clk's parent should be the l3_mp_clk. This will account for
the extra divider that is present for the l3_mp_clk.
The dbg_clk's parent should be the dbg_at_clk. This will account for
the extra divider that is present for the dbg_at_clk.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Just in case the firmware did not enable data and instruction prefetch in
the L2 cache controller, we enable it in the kernel.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Add the enable-method property for the cpu node on socfpga.dtsi and
socfpga_arria10.dtsi. This is for CPU_METHOD_OF_DECLARE to use to enable
the secondary core.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
- Add a DTS node for the A9 SCU
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJVU1L4AAoJEBmUBAuBoyj05zEP/02UJVcqCHT2P/z/1XJnIwed
hZgO0Oej4ZEc+futAIx6IeMEkgNoIDZX1rdijiQe3Uv2QK8niC7R8yOjwcZrM8jZ
ws/jyKWpCBsV0J+lzZevxa3DpxMHPmcx0W9gAqYpikrwgbXt0Dyy62CQkp+XKZ5d
mluxSEbkSlORddzD8eQbM1yuVlFGg9RAzdwaeZk4j6x+vq2Zk+jEwq5EKLBIiO/U
kGwu/mEryiWl+lzqV7Nlagt4uLASsT5ZxEjr4zUx9ddDTJo4mqStqONdDPMTdf9h
0qzHrWa9mMhI7RLoOWBuvTEcvEVPSRNhVfo6cY8ZnQcZ/V5tj4sG3jAPUFXkFSMd
iZW3mud5P45ugbKiumR5R7ve3t6yxhvNqWH9FZqfnlPPNXtCaUqBGB772A0Xr2Hz
mRPu2Vl9cjmGdrWQHqF5sViPdm52E8Het3/HO0ccsx4aoH+jhgGKeqmiK779EKTA
lA0NPBrL5PRzjNacNwnR7RxtLpcISf5CbsV0ojiIDtB8x11TCg1Zct+ogeE03luT
YpTNuOgTEg7Gy4oa6LPPXahUS+6RffHmASjlt15xaWx/x5MaCXTyk3H4JtSumDiL
blFzdQmNUcO2YpggSgyS0UzRFyqYJIRPq7lHKMJz5NMfaHVzu4VzoDKmJVo4zG2T
BftEOP7ROh5wq1HkWJs3
=23ne
-----END PGP SIGNATURE-----
Merge tag 'socfpga_dts_for_v4.2_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt
Merge "SoCFPGA update for v4.2 part 2" from Dinh Nguyen:
- Add a DTS node for the A9 SCU
* tag 'socfpga_dts_for_v4.2_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: socfpga: dts: add the a9-scu node
Add tx-fifo-depth and rx-fifo-depth devicetree properties for socfpga
stmmac. These devicetree properties will be used to configure certain
features of the stmmac on the socfpga.
Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
The CIU(Card Interface Unit) get its clock from the sdmmc_clk_divided clock
which is used to clock the card. The sdmmc_clk_divided clock is the sdmmc_clk
passed through a fixed divider of 4. This patch adds the sdmmc_clk_divided
node and makes the sdmmc_clk it's parent.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: renamed ciu_clk to sdmmc_clk_divided
The socfpga.dtsi currently has the wrong interrupt number set for SPI master 1
Trying to use the master without this change results in the kernel boot
process waiting forever for an interrupt that will never occur while
attempting to probe any slave devices configured in the device tree as being
under SPI master 1.
The change works for the Cyclone V, and according to the Arria 5 handbook
should be good there too.
Signed-off-by: Mark James <maj@jamers.net>
Acked-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
socfpga.dtsi is missing the DMA channels for the uart nodes.
This will produce the following errors:
of_dma_request_slave_channel: dma-names property of node '/soc/serial0@ffc02000' missing or empty
ttyS0 - failed to request DMA
Provide the correct DMA channels to fix this.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
- Add DTS support for a new chip in the SOCFPGA family, the Arria 10.
- Enable watchdog node.
- Add SPI nodes.
- Add the OCRAM node.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJUbslHAAoJEBmUBAuBoyj0R0EP/2nF0rHzM7s9TivfLLnknwu5
UCPFkuB9DFsfBn6XauAjuioY2/K1yugU5Xh4IyKgXfOdUYDRxT18FzltJl8Tk25h
yx7tm5DlukQ68sdKgcSNMXgH1VNR0zV0k0P1PBjdB2W78DGpQTi5KUDb29a6wk7a
g7pYnhrzlKgLVfAazhxsD/N2o+ImxFvsVpdQBxi4/oR5zgYEoLbv6i4CKzPBrPv9
T/v4MP9E9p8tviSpuj99plMZN8w4uBQ7Clc1xCrh8y+KvKRjViFnUZPXFZHnPENs
XnqPuDyHvMxYEKQgrSDO5GQ4USUFM+TTSKGSobkCYYmaw53F+g6FxYTCDkubyCW/
v9OAH5t3lQf3P8SyHdZ2hhGH4EAoTzxC7uYJes/JdjxZgBHpfZv/bj3MGMI6r+w8
5rUF8ueipQjVOVJtr2YkkGM9U0CFw1dBGFBGk3eMrXPV418fcrIJZkRoDwdnvpQj
I8sG1rEoZHAbPOu2ejyxVAlvHF5uy7HAXpt3ktekJV70DtcNTUpREbMso7fksEzL
xufDmwe/BjUzJBFsVhZZLULUlHt1rZLYHXOn/NdfBEWluT4+uhc+1DcsCsc99Bhe
AIUMX+ngDpWZazxRGhzlOxdzi9dhuN1pFtJlXuj2wBhVNdivac4OjgBgFYWu9lpZ
cC/byWHasY2Kyyi1+tDd
=sh1R
-----END PGP SIGNATURE-----
Merge tag 'socfpga_dts_updates_for_v3.19' of git://git.rocketboards.org/linux-socfpga-next into next/dt
Pull "SoCFPGA DTS updates for v3.19" from Dinh Nguyen:
- Add DTS support for a new chip in the SOCFPGA family, the Arria 10.
- Enable watchdog node.
- Add SPI nodes.
- Add the OCRAM node.
* tag 'socfpga_dts_updates_for_v3.19' of git://git.rocketboards.org/linux-socfpga-next:
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC
arm: dts: socfpga: enable watchdog for socfpga platform
arm: dts: socfpga: Add SPI nodes to SOCFPGA DT.
arm: dts: socfpga: Add OCRAM node
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Since the Synopsys GPIO IP can support multiple ports of varying widths, it
would make more sense to have the GPIO node DTS entry as this:
gpio0: gpio@ff708000{
porta{
};
};
Also, this is documented in the snps-dwapb-gpio.txt.
Suggested-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
project.
There was a discussion thread on whether this driver should be an mfd driver
or just make use of syscon, which is already a mfd. Ultimately, the
decision to use a simple syscon interface was reached.[1]
[1] https://lkml.org/lkml/2014/7/30/514
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
[dinguyen] cleaned-up commit header and remove version history.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Unlike the board branch, this keeps having large sets of changes for
every release, but that's quite expected and is so far working well.
Most of this is plumbing for various device bindings and new platforms,
but there's also a bit of cleanup and code removal for things that
are moved from platform code to DT contents (some OMAP clock code in
particular).
There's also a pinctrl driver for tegra here (appropriately acked),
that's introduced this way to make it more bisectable.
I'm happy to say that there were no conflicts at all with this branch
this release, which means that changes are flowing through our tree as
expected instead of merged through driver maintainers (or at least not
done with conflicts).
There are several new boards added, and a couple of SoCs. In no particular
order:
* Rockchip RK3288 SoC support, including DTS for a dev board that they
have seeded with some community developers.
* Better support for Hardkernel Exynos4-based ODROID boards.
* CCF conversions (and dtsi contents) for several Renesas platforms.
* Gumstix Pepper (TI AM335x) board support
* TI eval board support for AM437x
* Allwinner A23 SoC, very similar to existing ones which mostly has
resulted in DT changes for support. Also includes support for an Ippo
tablet with the chipset.
* Allwinner A31 Hummingbird board support, not to be confused with the
SolidRun i.MX-based Hummingboard.
* Tegra30 Apalis board support
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJT5DqvAAoJEIwa5zzehBx3tm0QAJk8zFyZuMhUPz6SoZTtO9ti
zojZ2218oqLRDfLSYdJx/3QE7gb2ef0e2S6FrthecdAY8sqZzDddL7M/cCf1WSgy
+D4dD1UEq+W/hOeEwIWyo3GR/71exgo/LMTIw8HOJh5c9fanQ2wNChNetCgh8b4u
sVOEMmP1UTO2W7mH9cCRhWXFifBNi0yNl1QBYnLPzM2CbSEa4qQRarTn/94NSEiY
U9XgzysklvYEW/30wcEkz8ZonKbJrtP+zEjODU4wN/muhHECeTehDrkJq0WEK/3C
3ptko2xQGURNaLM6HVvQS9qkXxyhCeZxqkELpjkjjM+YPFN8wdHu7gDctGZlDr39
LQ2pZF6K8vaFvxp3UM2wzdDeoNi3rxguzpFoBmfRP5NWguDrOvjT3w8W4hO9q04J
8SqMGca0av9myHmeSjtRRg5rmcC3kBbOgSN6siVJ8W80rHT7tnFjl6eCawDreQzn
szFzGaOOUnf/kJ/00vzm1dCuluowFPdSYgW3aamZhfkqu2qYJ8Ztuooz5eZGKtex
zlUfKtpL26gnamoUT42K7E8J968AjHjUc/zimwYzIgHCzTTApYGJQcbD/Y28b8QH
gTvhRxP+0kFb+NNq4IHStVMvJrFOPvzOHXcL8x07HqTxrl7W4XoW+KJxCJOk433W
5NJ9s4tEmiTRMtFL1kv6
=xxlY
-----END PGP SIGNATURE-----
Merge tag 'dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device-tree changes from Olof Johansson:
"Unlike the board branch, this keeps having large sets of changes for
every release, but that's quite expected and is so far working well.
Most of this is plumbing for various device bindings and new
platforms, but there's also a bit of cleanup and code removal for
things that are moved from platform code to DT contents (some OMAP
clock code in particular).
There's also a pinctrl driver for tegra here (appropriately acked),
that's introduced this way to make it more bisectable.
I'm happy to say that there were no conflicts at all with this branch
this release, which means that changes are flowing through our tree as
expected instead of merged through driver maintainers (or at least not
done with conflicts).
There are several new boards added, and a couple of SoCs. In no
particular order:
- Rockchip RK3288 SoC support, including DTS for a dev board that
they have seeded with some community developers.
- Better support for Hardkernel Exynos4-based ODROID boards.
- CCF conversions (and dtsi contents) for several Renesas platforms.
- Gumstix Pepper (TI AM335x) board support
- TI eval board support for AM437x
- Allwinner A23 SoC, very similar to existing ones which mostly has
resulted in DT changes for support. Also includes support for an
Ippo tablet with the chipset.
- Allwinner A31 Hummingbird board support, not to be confused with
the SolidRun i.MX-based Hummingboard.
- Tegra30 Apalis board support"
* tag 'dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (334 commits)
ARM: dts: Enable USB host0 (EHCI) on rk3288-evb
ARM: dts: add rk3288 ehci usb devices
ARM: dts: Turn on USB host vbus on rk3288-evb
ARM: tegra: apalis t30: fix device tree compatible node
ARM: tegra: paz00: Fix some indentation inconsistencies
ARM: zynq: DT: Clarify Xilinx Zynq platform
ARM: dts: rockchip: add watchdog node
ARM: dts: rockchip: remove pinctrl setting from radxarock uart2
ARM: dts: Add missing pinctrl for uart0/1 for exynos3250
ARM: dts: Remove duplicate 'interrput-parent' property for exynos3250
ARM: dts: Add TMU dt node to monitor the temperature for exynos3250
ARM: dts: Specify MAX77686 pmic interrupt for exynos5250-smdk5250
ARM: dts: cypress,cyapa trackpad is exynos5250-Snow only
ARM: dts: max77686 is exynos5250-snow only
ARM: zynq: DT: Remove DMA from board DTs
ARM: zynq: DT: Add CAN node
ARM: EXYNOS: Add exynos5260 PMU compatible string to DT match table
ARM: dts: Add PMU DT node for exynos5260 SoC
ARM: EXYNOS: Add support for Exynos5410 PMU
ARM: dts: Add PMU to exynos5410
...
This patch adds socfpga Ethernet filter attributes for multicast
and unicast filters per Synopsys Ethernet IP configuration chosen
by Altera for the Cyclone 5 and Arria SOC FPGAs.
Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
add #reset-cells to socfpga.dtsi. This was missing from the
latest updates and caused the socfpga reset controller to fail
to load like so:
ffd05000.rstmgr: /soc/rstmgr@ffd05000 missing #reset-cells property
probe of ffd05000.rstmgr failed with error -22
Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
The SoCFPGA has two watchdog timers. Add them to the dtsi.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
[dinh: modified patch to have correct irq flag]
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
The cycloneV has three gpio controllers, each one with 29 gpios. This patch
adds the three controller with the gpio driver which is now sitting the
gpio tree.
Cc: devicetree@vger.kernel.org
Acked-by: Alan Tull <atull@altera.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
The mpu_clk, main_clk, and dbg_base_clk outputs from the main PLL go through a
pre-divider. Update socfpga.dtsi to represent those dividers for these
clocks.
Re-use the "div-reg" property that was used for the socfpga-gate-clock as this
is the same thing. Also update the documentation.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Add the necessary #reset-cells property to the rst-mgr node and
provide a header-file with all possible resets specified.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
The timers and uart can get their clock frequencies using the common clock
driver.
Reviewed-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Convert all socfpga DT files to the dtc preprocessor include syntax.
This allows to include header files in the devicetrees like other
SoC-types already do.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Add both can controllers to the dtsi.
Reviewed-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Florian Vaussard