Rename some variables and structure fields to make the code more
comprehensible. Also change the prototype of internal functions to be
more in line with the OPP core functions.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Instead of copying parts of the CVB table into a separate structure,
keep track of the selected CVB table and directly reference data from
it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The kerneldoc for struct tegra_dfll_soc_data is stale. Update it to
match the current structure definition.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The post divider value in the frequency table is wrong as it would lead
to the PLL producing an output rate of 960 MHz instead of the desired
480 MHz. This wasn't a problem as nothing used the table to actually
initialize the PLL rate, but the bootloader configuration was used
unaltered.
If the bootloader does not set up the PLL it will fail to come when used
under Linux. To fix this don't rely on the bootloader, but set the
correct rate in the clock driver.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
If the bootloader does not touch PLL_C it will stay in its reset state,
failing to lock when enabled. This leads to consumers of this clock to
fail probing. Fix this by always programming the PLL with a sane rate,
which allows it to lock, at startup.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Use a new Tegra210 version of the pll_register_pllre function to
allow setting the proper settings for the m and n div fields.
Additionally define PLL_RE_OUT1 on Tegra210.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
[treding@nvidia.com: define PLLRE_OUT1 register offset]
Signed-off-by: Thierry Reding <treding@nvidia.com>
The sor_safe clock is a fixed factor (1:17) clock derived from pll_p. It
has a gate bit in the peripheral clock registers. While the SOR is being
powered up, sor_safe can be used as the source until the SOR brick can
generate its own clock.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The dpaux (on Tegra124 and Tegra210) and dpaux1 (on Tegra210) are fixed
factor clocks (1:17) and derived from pll_p_out0 (pll_p). They also have
a gate bit in the peripheral clock registers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
This clock is of the same type as dpaux and is added to feed into the
second DPAUX block used in conjunction with SOR1.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Some of the peripheral clocks on Tegra are derived from one of the top-
level PLLs with a fixed factor. Support these clocks by implementing the
->enable() and ->disable() callbacks using the peripheral clock register
banks and the ->recalc_rate() by dividing the parent rate by the fixed
factor.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Starting with Tegra124, the mipi-cal clock uses the 72 MHz clock as its
source. On Tegra114 this clock's parent was clk_m, so it is the one-off
chip.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Trailing blank lines are undesirable (several tools, such as git,
complain about them), so remove it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The peripheral clock registers are defined in static tables. These
tables never need to be modified at runtime, so they can reside in
read-only memory.
Signed-off-by: Thierry Reding <treding@nvidia.com>
On Tegra210, hardware control of the SATA and XUSB pad PLLs must be
done during the UPHY enable sequence rather than the PLLE enable
sequence. Export functions to do this so that hardware control can
be enabled from the XUSB padctl driver.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This patch fix spelling typos in printk from various part
of the codes.
Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
As a pure Clock Domain does not have the concept of powering the domain
itself, the CPG/MSTP driver does not provide power_off() and power_on()
callbacks.
However, the genpd core may still perform a dummy power down, causing
/sys/kernel/debug/pm_genpd/pm_genpd_summary to report the domain's
status being "off-0".
Use the always-on governor to make sure the domain is never powered
down, and always shows up as "on" in pm_genpd_summary.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
All local setup of the generic_pm_domain structure should have been
completed before calling pm_genpd_init().
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
As a pure Clock Domain does not have the concept of powering the domain
itself, the CPG/MSTP driver does not provide power_off() and power_on()
callbacks.
However, the genpd core may still perform a dummy power down, causing
/sys/kernel/debug/pm_genpd/pm_genpd_summary to report the domain's
status being "off-0".
Use the always-on governor to make sure the domain is never powered
down, and always shows up as "on" in pm_genpd_summary.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
All local setup of the generic_pm_domain structure should have been
completed before calling pm_genpd_init().
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
The i.MX 7 designs Ethernet PLL provides a 1000MHz reference clock.
Store the reference clock in the clk_pllv3 structure according to
the PLL type.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Introduce a DT-based driver for the R-Car System Controller, as found on
Renesas R-Car H1, R-Car Gen2, and R-Car Gen3 SoCs.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXHryuAAoJENfPZGlqN0++Zq4QAJkrqIK774IUSa58+U4bMG2h
ceRhG+uqr5AGoQJ/pEpFZjgaLe7hmrgKQmF2Uh1uWns633o2t6N2rR6gM36/BTqh
HyyCMKT4vUoU6lyZ7qnB8LOxRj4oRa5J2C82rROWRx9m7TNmyHpA05KZUW2sUMmi
6/g+YF0wT8XbwSjUskxFSwO8TeKNcOSpFi0wWVR1WUh2RhVNbGXhyUSxxGTD3Ojt
X6f1YmrfJmwzI0cY8AZScOr7WCU0HFk8IZRkEbg8t39TVOrEL5o97Ki9QK6WaGf8
uKA7gA1eDhO8DSXX1ycawx8uh4AxRGgYSZFc0Lq7E08k+VTn7D7qDsk4DDz+JnpH
aLy95N4lDuQf9iiKFWEECc2OK3hxAnJb8c4yU2pS7tg1K4JNMT0iUkp2Ha+/RLrd
+FcWYcerXLziBItseM0caDPyv7PXpNLpLnqfgYPAOcP4h5+tT8burH9Ic5zHdFgZ
JAD30KBYH8xB7wRisf4S/MP6sHFD8XQl6WdQK1Vwl1oPitRRdgDIxaFhyDszli3O
/mX5+iMavM/s36MZwAgck2nTNTal1CHqupzkvWzttee3sZXzmK8QuiYLqI8iqz2i
HPxXM90IjzfQNtBZH6ZVdL3xCh8HKkzQdD6wb7I2nP7clMHJlNmQwanXcSw6vcvB
/Jx3o0v31gXfdUx3lgCy
=Lg0X
-----END PGP SIGNATURE-----
Merge tag 'renesas-rcar-sysc2-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers
Merge "Second Round of Renesas ARM Based SoC R-Car SYSC Updates for v4.7" from Simon Horman:
Introduce a DT-based driver for the R-Car System Controller, as found on
Renesas R-Car H1, R-Car Gen2, and R-Car Gen3 SoCs.
* tag 'renesas-rcar-sysc2-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (30 commits)
soc: renesas: rcar-sysc: Add support for R-Car H3 power areas
soc: renesas: rcar-sysc: Add support for R-Car E2 power areas
soc: renesas: rcar-sysc: Add support for R-Car M2-N power areas
soc: renesas: rcar-sysc: Add support for R-Car M2-W power areas
soc: renesas: rcar-sysc: Add support for R-Car H2 power areas
soc: renesas: rcar-sysc: Add support for R-Car H1 power areas
soc: renesas: rcar-sysc: Enable Clock Domain for I/O devices
soc: renesas: rcar-sysc: Make rcar_sysc_power_is_off() static
soc: renesas: rcar-sysc: Add DT support for SYSC PM domains
soc: renesas: rcar-sysc: Improve rcar_sysc_power() debug info
soc: renesas: Move pm-rcar to drivers/soc/renesas/rcar-sysc
clk: renesas: cpg-mssr: Export cpg_mssr_{at,de}tach_dev()
clk: renesas: mstp: Provide dummy attach/detach_dev callbacks
clk: renesas: Provide Kconfig symbols for CPG/MSSR and CPG/MSTP support
soc: renesas: Add r8a7795 SYSC PM Domain Binding Definitions
soc: renesas: Add r8a7794 SYSC PM Domain Binding Definitions
soc: renesas: Add r8a7793 SYSC PM Domain Binding Definitions
soc: renesas: Add r8a7791 SYSC PM Domain Binding Definitions
soc: renesas: Add r8a7790 SYSC PM Domain Binding Definitions
soc: renesas: Add r8a7779 SYSC PM Domain Binding Definitions
...
The cifout clock is incorrect due to the manual error, we need to
fix it.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We don't need to many clocks enable after startup, to reduce some
power consumption.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch add some necessary frequencies for the RK3399 clock.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The gate bits of the i2c4 and i2c8 are incorrect due to the manual
error, we need to fix them.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Currently, the sunxi clock driver gets the name for the base factor clock
of divs clocks from the name field in factors_data. This prevents reusing
of the factor clock for clocks with same properties, but different name.
This commit makes the divs setup function try to get a name from
clock-output-names in the devicetree. It also removes the name field where
possible and merges the sun4i PLL5 and PLL6 clocks.
[Andre: Make temporary name allocation dynamic.]
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
fix spelling mistake, unsucessful -> unsuccessful
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
- Two sets of name and unit address check fixes for dts files.
- DMA, McASP, and timer and regulator related dts changes for dra7
- Add more devices for Nokia N9/N950
- Initial support for am335x ICEv2
- Initial support for am572x-IDK
- Pinctrl changes for am335x-baltos-ir5221
- Initial support for Amazon Kindle Fire (first generation)
- A series of changes to add GPIO controller support for the
GPMC driver. The driver changes will be merged separately.
- Support for am43xx clkout1
- Pinctrl and RTC changes for am335x-chili
- Add support for dra72-evm rev C (SR2.0)
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXGp/XAAoJEBvUPslcq6VzbhwQAKHgA3os+FR8sj2PRMkr4zwn
o4WVhh3A6rEHPB7gR9QpMrc+12eD4eQEb+HpbEd5P4j40DN0BXC82l0BCza5XRsS
qBqaPKE983nY3HtisibPufM/0DtMDJmLvUGgAe03mAorrN23pZkvE0MSKVx0EwSl
q/c/r19rfFTIz1EDTX8loW4gxPI/lr1iU7G1wX4tKpeA75EBdNG7xgyKmbSzfF1e
MnZP4qhKzCRWPN+w41g7hpjdj0sPx3gxCeLn7ofM2WUnxXyMUTtVgMSdUoFhImxF
0Ivsh1uiPz2/HKZSclRYy0yHmeEsEHMGiyYGJXw6+PazlTNDSP+71nC++HMm4Gzr
lYUrIgmCNRtyw9nXWcNtcDTPIgM7HreLK39W4e4O+h4D9pb2w3l6C1qdUZRrjydk
oODJP7b6OXS3JnOfhO5lsS0rd31CpORWS5lP1NoXfgS3KVV4VNxqDe1bNM3IoqiX
ypzY4aiRKRQxUB6OMfRXh3uUSICZnIpMmZehobMOyWAWVU/xZOkVWMbm5aZUevnN
2ywWi5RXryPsa2HiRdtunXA5pM2hHklhabufEC3qz2rO1kPJxIseI2SxkScsDQOi
Z8g5zL+2JhKZQgo0/9qYT/mTFbNtsjfq2XwNcxOGx+4QPj9GziGcROW84wHOVxlM
Q/H2+GtOuytXEMVQvjqE
=zZDR
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.7/dt-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Merge "First set of device tree changes for omaps for v4.7 merge window" from Tony Lindgren:
- Two sets of name and unit address check fixes for dts files.
- DMA, McASP, and timer and regulator related dts changes for dra7
- Add more devices for Nokia N9/N950
- Initial support for am335x ICEv2
- Initial support for am572x-IDK
- Pinctrl changes for am335x-baltos-ir5221
- Initial support for Amazon Kindle Fire (first generation)
- A series of changes to add GPIO controller support for the
GPMC driver. The driver changes will be merged separately.
- Support for am43xx clkout1
- Pinctrl and RTC changes for am335x-chili
- Add support for dra72-evm rev C (SR2.0)
* tag 'omap-for-v4.7/dt-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (61 commits)
ARM: dts: Add support for dra72-evm rev C (SR2.0)
ARM: dts: am335x-chilisom: Enable poweroff PMIC sequence using RTC signal
ARM: dts: am335x-chili*: Move Ethernet MAC description from SOM to board
ARM: dts: am335x-chili*: Move uart0 description from SOM to board
ARM: dts: am43xx: add support for clkout1 clock
ARM: dts: omap3-beagle: Provide NAND ready pin
ARM: dts: am335x: Provide NAND ready pin
ARM: dts: am437x: Provide NAND ready pin
ARM: dts: dra7x-evm: Provide NAND ready pin
ARM: dts: dm816x: Enable gpio controller for GPMC
ARM: dts: dm814x: Enable gpio controller for GPMC
ARM: dts: omap3: Enable gpio controller for GPMC
ARM: dts: am4372: Enable gpio controller for GPMC
ARM: dts: am335x: Enable gpio controller for GPMC
ARM: dts: dra7: Enable gpio controller for GPMC
ARM: dts: omap5: Enable gpio and interrupt controller for GPMC
ARM: dts: omap4: Enable gpio and interrupt controller for GPMC
ARM: dts: omap24xx: Enable gpio and interrupt controller for GPMC
ARM: dts: omap4-kc1: Power off support
ARM: dts: omap4-kc1: LEDs support
...
Merge necessary new clocks from Sylwester (used by new board) and add support
for Exynos3250-based Artik5 board.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXDgugAAoJEME3ZuaGi4PX8JIP/0UmBC5FLJLgzFRgzVcGvwjS
nzLRcIqwQ7i/ztT3r3kUndjrHLQAqWRynrNdq0w+W+DYGVEYEToBfVbqdVezJ9i+
XgfeXvUU/k+4aZHpsrcl6ZST7MD6UQn9qSLB1R3Y4zHVw68gldNPMtDNpyrQJutu
440+vd5fKZxmcEx8exAIon4AEnPXsDkom2YQTd4NfeKmVHxsfJsv3Irj3DcRrcYV
StCp7n1UhZmEP3pAhOhyGx6XmU/Qrl4iYZtSwpmDC5PwAt8dHQ8b4Z/N+uP8Ghas
jCaNTA+z9mKdTyNNdLAefWeIddhCTp1eAdzoV5znBAIDjpGBqZjWKbq77v1m2NqU
jSmY+m/UpexNnC5b5eYJbjU+l85VhXECog3qjCUjuJtj+nib95icYM536WhTzhRf
ZEZ/NZyU5ReO10bTYr+YTb4O/iz+SMzfghGvs2HXpVk4X89utG7HUqcYg6zCQIWz
4sL8JGAhq1bmzzgnS+8km2ZpRD6gmssB+2tG16nJk0tJFplHzU9Wr46Q/ttMeg9I
d2GK/sE9EFooQH+fqoQmi1aNKb3fEJlUIvqpxfTeFbhnRpOCCfaIq+U9bmg9JxdG
HuZuEO0ClNFyQN8TBUNmzZL5XzYGPUksbVWyVc4VuZ0PNEXLeMsyzCUmgrLEPQEU
EzgObFNrzaouu8QN3rii
=mQfO
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt-exynos3250-artik5-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt
Merge "Topic branch for Device Tree changes for Exynos 3250 for v4.7" from Krzysztof Kozlowski:
Merge necessary new clocks from Sylwester (used by new board) and add support
for Exynos3250-based Artik5 board.
* tag 'samsung-dt-exynos3250-artik5-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: Add MSHC2 DT node for SD card for exynos3250-artik5-eval board
ARM: dts: exynos: Add exynos3250-artik5 dtsi file for ARTIK5 module
ARM: dts: exynos: Add MSHC2 DT node for Exynos3250 SoC
ARM: dts: exynos: Add UART2 DT node for Exynos3250 SoC
ARM: dts: exynos: Add initial gpio setting of MMC2 device for exynos3250-monk
ARM: dts: exynos: Add initial pin configuration for exynos3250-rinato
clk: samsung: exynos3250: Add MMC2 clock
clk: samsung: exynos3250: Add UART2 clock
dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250
The TCON is a controller generating the timings to output videos signals,
acting like both a CRTC and an encoder.
It has two channels depending on the output, each channel being driven by
its own clock (and own clock controller).
Add a driver for the channel 1 clock.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
PLL7, clocked from a 3MHz oscillator, that drives the display related
clocks (GPU, display engine, TCON, etc.)
Add a driver for it.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Use the function resource_size instaed of explicit computation.
Problem found using Coccinelle.
Signed-off-by: Vaishali Thakkar <vaishali.thakkar@oracle.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add the clock type which is used by the sun6i/8i families for video display.
Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
add CLK_SET_RATE_PARENT to modify the rate on clk upstream
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The composite clock didn't have any unregistration function, which forced
us to use clk_unregister directly on it.
While it was already not great from an API point of view, it also meant
that we were leaking the clk_composite structure allocated in
clk_register_composite.
Add a clk_unregister_composite function to fix this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add Oxford Semiconductor OXNAS SoC Family Standard Clocks support.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[sboyd@codeaurora.org: Drop NULL/continue check in registration
loop]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
- Export the CPG/MSSR and CPG/MSTP attach/detach_dev callbacks, so
they can be called by the R-Car SYSC PM Domain driver.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXF2zRAAoJEEgEtLw/Ve77lQkP/0ePeLyPLr2kqmMWe3+5MaVe
suKU0i3GAV1fQJpl6Z3CibiDdjXrT9/7S+VVDaBme3VHwlE22QvBD0f2yn4RyL11
f5wJIyCf1TXMdfsL0MSnX+6efcfwfdDDgUe/aoMj2ybOwOfFwIbKEPDhVjkMeqQo
OcbIG8qBN0Hh237Lkb70SC0Oc27djSPpdoxd5+3B5ytpHo1q0ER1qQfdwy0MmG2J
vtcXnZxHoigxk6uanH8BwpdYbFhhRA+KRmyxfS4MYmOVdaVvUZPCddbLBDfcE6d9
xYpno+7TKVYni9rwd48Vq0EASVkRSyBJplCfLYOWCieIvrdHbFVpxGFTeW+uxzBS
b+mRKnuM7fGm8j5At+i7bVbKVAXVvWaRr9K4j4E/XukT2B1/dNfRoc0HEBJzNsnO
+S/X2JoHDyeiGva8cESlnQgO2rE9YiktxMVPX+Ey0k0ab7UigM6SzUle7wt1PVOg
PfNLfJUkGxv77GpPKjhb/BbhImBmMIBLeHKOwMKM8WFCeLUjk6h8CsPFmsFPgAE7
rTk87G1bMWBjjpk0d0nTggIStErF91yTZW+4kSMK9LRg+1//b+NO3xe9kQABLcmX
5qaZoQDRqHiq+6loqsOW0xzvMjAYOxUmvE0oeqLamX20Qg5SzZmwcMtC+JceWSFG
GE5VOJ8cBWcaBLFUmCmq
=jmQf
-----END PGP SIGNATURE-----
Merge tag 'clk-renesas-for-v4.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
clk: renesas: R-Car SYSC PM Domain Preparation
- Export the CPG/MSSR and CPG/MSTP attach/detach_dev callbacks, so
they can be called by the R-Car SYSC PM Domain driver.
* tag 'clk-renesas-for-v4.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: cpg-mssr: Export cpg_mssr_{at,de}tach_dev()
clk: renesas: mstp: Provide dummy attach/detach_dev callbacks
clk: renesas: Provide Kconfig symbols for CPG/MSSR and CPG/MSTP support
rk3399 header and also in the clock code itself.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABCAAGBQJXFzXaAAoJEPOmecmc0R2BfoIH/jzxzuOFb7oMIEjWA1Dlv6ev
I9l63Pi5+/BGXMXkuvBCpyVKRk9T7jyAkQbvMuoo6ELOmEtn2AX4BC7Pq+xok7Xz
WZZQY/+nkYaAjJ6GscLpqWtNlhwCY0Ms/1WOp9DwTwcDztiTJaa9iQf5CELEJMhg
RfANV2DIi9mNh+Nx4JIQi2e01tN2EXUsSNH8NVKTqfZKR/hvb9KO3qQWQzGdgqPr
jNaAuVIq1iOIV0fBD7X8WJwQ2JqmrP7UsvIAXYk46E53jSk5RvnrGIvFp23pu0Jc
0a677jCpx09en6LLPXQOwgtx687hChP5HT466BXo241daJkX4isDKAx430p7hGY=
=99uY
-----END PGP SIGNATURE-----
Merge tag 'v4.7-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull some checkpatch silencers from Heiko Stuebner:
Fix quite some checkpatch warnings in the newly added
rk3399 header and also in the clock code itself.
* tag 'v4.7-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: fix checkpatch warning in core code
clk: rockchip: drop unnecessary header comment
clk: rockchip: reign in some overly long lines in the rk3399 controller
clk: rockchip: fix checkpatch errors in rk3399 dt-binding header
We seem to have accumulated a bunch of checkpatch warnings, with mainly
overlong lines and two unnecessary allocation error messages.
Most were introduced with the recent multi-controller-support but some
were quite a bit older.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The R-Car SYSC PM Domain driver has to power manage devices in power
areas using clocks. To reuse code and to share knowledge of clocks
suitable for power management, this is ideally done through the existing
cpg_mssr_attach_dev() and cpg_mssr_detach_dev() callbacks.
Hence these callbacks can no longer rely on their "domain" parameter
pointing to the CPG/MSSR Clock Domain. To handle this, keep a pointer to
the clock domain in a static variable. cpg_mssr_attach_dev() has to
support probe deferral, as the R-Car SYSC PM Domain may be initialized,
and devices may be added to it, before the CPG/MSSR Clock Domain is
initialized.
Dummy callbacks are provided for the case where CPG/MSTP support is not
included, so the rcar-sysc driver won't have to care about this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Currently the decision whether to build the renesas-cpg-mssr and
clk-mstp drivers is handled by Makefile logic. However, the rcar-sysc
driver will need to know whether CPG/MSSR and/or CPG/MSTP support are
available or not.
To avoid having to duplicate this logic, move it to Kconfig. Provide
non-visible CLK_RENESAS_CPG_MSSR and CLK_RENESAS_CPG_MSTP Kconfig
symbols, which can be used by both Makefiles and C code.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
In poweroff, we set the reset bit and the power down bit, but only
managed to unset the reset bit for poweron. This meant that if HDMI
did -EPROBE_DEFER after it had grabbed its clocks, we'd power down the
PLLH (that had been on at boot time) and never recover.
Signed-off-by: Eric Anholt <eric@anholt.net>
Fixes: 41691b8862 ("clk: bcm2835: Add support for programming the audio domain clocks")
Cc: stable@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add __init attribute on a function that is only called from other __init
functions and that is not inlined, at least with gcc version 4.8.4 on an
x86 machine with allyesconfig. Currently, the function is put in the
.text.unlikely segment. Declaring it as __init will cause it to be put in
the .init.text and to disappear after initialization.
The result of objdump -x on the function before the change is as follows:
0000000000000000 l F .text.unlikely 0000000000000071 sysclk_from_fixed.constprop.5
And after the change it is as follows:
0000000000000480 l F .init.text 000000000000006c sysclk_from_fixed.constprop.5
Done with the help of Coccinelle. The semantic patch checks for local
static non-init functions that are called from an __init function and are
not called from any other function.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
of_find_node_by_name() will call of_node_put() on the node so we need to
get it first to avoid warnings.
The cfg_node needs to be put after we have finished processing the
properties.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add registration APIs in the clk fixed-rate code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add registration APIs in the clk gpio code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add registration APIs in the clk composite code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add registration APIs in the clk fractional divider code to
return struct clk_hw pointers instead of struct clk pointers.
This way we hide the struct clk pointer from providers unless
they need to use consumer facing APIs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add registration APIs in the clk fixed-factor code to return
struct clk_hw pointers instead of struct clk pointers. This way
we hide the struct clk pointer from providers unless they need to
use consumer facing APIs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add registration APIs in the clk mux code to return struct clk_hw
pointers instead of struct clk pointers. This way we hide the
struct clk pointer from providers unless they need to use
consumer facing APIs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add registration APIs in the clk gate code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add registration APIs in the clk divider code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Now that we have a clk registration API that doesn't return
struct clks, we need to have some way to hand out struct clks via
the clk_get() APIs that doesn't involve associating struct clk
pointers with a struct clk_lookup. Luckily, clkdev already
operates on struct clk_hw pointers, except for the registration
facing APIs where it converts struct clk pointers into struct
clk_hw pointers almost immediately.
Let's add clk_hw based registration APIs so that we can skip the
conversion step and provide a way for clk provider drivers to
operate exclusively on clk_hw structs. This way we clearly
split the API between consumers and providers.
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Now that we have a clk registration API that doesn't return
struct clks, we need to have some way to hand out struct clks via
the clk_get() APIs that doesn't involve associating struct clk
pointers with an OF node. Currently we ask the OF provider to
give us a struct clk pointer for some clkspec, turn that struct
clk into a struct clk_hw and then allocate a new struct clk to
return to the caller.
Let's add a clk_hw based OF provider hook that returns a struct
clk_hw directly, so that we skip the intermediate step of
converting from struct clk to struct clk_hw. Eventually when
we've converted all OF clk providers to struct clk_hw based APIs
we can remove the struct clk based ones.
It should also be noted that we change the onecell provider to
have a flex array instead of a pointer for the array of clk_hw
pointers. This allows providers to allocate one structure of the
correct length in one step instead of two.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
We've largely split the clk consumer and provider APIs along
struct clk and struct clk_hw, but clk_register() still returns a
struct clk pointer for each struct clk_hw that's registered.
Eventually we'd like to only allocate struct clks when there's a
user, because struct clk is per-user now, so clk_register() needs
to change.
Let's add new APIs to register struct clk_hws, but this time
we'll hide the struct clk from the caller by returning an int
error code. Also add an unregistration API that takes the clk_hw
structure that was passed to the registration API. This way
provider drivers never have to deal with a struct clk pointer
unless they're using the clk consumer APIs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Now that we've converted the only caller over to another clkdev
API, remove this one.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The internal clk header did contain a comment indicating that some of the
defined registers were shared over multiple clock controller variants.
In recent times, it was simply extended all the time and stopped providing
any meaningful information, so drop it and it's overlong line.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We allow overlong lines in the array portitions describing the clock
trees to ease readability by having each element always at the same
position. But the rest of the code should honor the 80 char limit.
Fix the newly added rk3399 clock code to respect that.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
A new element got inserted into enum mx35_clks with commit 3713e3f5e9
("clk: imx35: define two clocks for rtc"). This insertion shifted most
nummerical clock assignments to a new nummerical value which in turn
rendered most hardcoded nummeric values in imx35.dtsi incorrect.
Restore the existing order by moving the newly introduced clock to the
end of the enum. Update the dts documentation accordingly.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Fixes: 3713e3f5e9 ("clk: imx35: define two clocks for rtc")
Cc: <stable@vger.kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The OMAP Platform code provides possibility to select GP Timer as
default clocksource instead of counter_32K by using bootcmd parameter
'clocksource', but the system will crash during early boot when this
option is used on dra7 or omap5 platforms, because it will hit BUG()
statement:
omap2_gptimer_clocksource_init
->BUG_ON(res);
This happens because clk_dev alias "sys_clkin_ck" is not registered.
Hence, fix it by adding missing "sys_clkin_ck" clk_dev aliases
definitions for omap5 and dra7.
Acked-by: Tero Kristo <t-kristo@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
AM33xx/AM43xx devices use the same DPLL IP blocks, which only support
maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type
DPLLs [2]. Reflect this limitation in the DPLL init code by adding the
max-rate parameter based on the DPLL types.
[1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
[2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
DPLLs typically have a maximum rate they can support, and this varies
from DPLL to DPLL. Add support of the maximum rate value to the DPLL
data struct, and also add check for this in the DPLL round_rate function.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add support for USB and SDIO clocks.
Report unsupported setups and panic.
Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The clk_register() function returns a valid pointer to struct clk or
ERR_PTR() error code, this makes a check for returned NULL value
useless and may lead to oops on error path.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Fixes: bcc5fd49a0 ("clk: at91: add a driver for the h32mx clock")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This flag is a no-op now. Remove usage of the flag.
Cc: Hou Zhiqiang <B48286@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This flag is a no-op now. Remove usage of the flag.
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This flag is a no-op now. Remove usage of the flag.
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This flag is a no-op now. Remove usage of the flag.
Cc: Guo Zeng <Guo.Zeng@csr.com>
Cc: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add a driver for the main clock controller of the Artpec-6 Soc.
Signed-off-by: Lars Persson <larper@axis.com>
[sboyd@codeaurora.org: Reformatted driver structure and of match]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Commit 7aba4f5201 ("clk: ti: dflt: fix enable_reg validity check")
fixed a validation check by using an IS_ERR() macro within the
existing unlikely expression, but IS_ERR() macro already has an
unlikely inside it, so get rid of the redundant unlikely macro
from the validation check.
Reported-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Main change is probably the added support for the new rk3399 soc
and necessary infrastructure changes surrounding it.
The biggest chunk is probably that clock code is now able to
handle multiple clock providers in one system, as the rk3399
has two of those. A general one and another smaller one in a
separate power domain. The rk3399 also uses another new pll type.
Thankfully it just fits nicely into our current structure.
It also needs some parts like the cpuclk mux parameters to be
a bit more flexible and an new fractional divider subtype without
gate.
Apart from this big change we have some more fixes and removal
of forgotten variables.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABCAAGBQJXDHdWAAoJEPOmecmc0R2BrSAIAIf3g2D84lSEYPDfjLCPHKWQ
vdmBG/J53+OqFfk0IgYFPcgFfXsgXX0iv34WgtxDOQ1uF+uPDC1KQFlyNrg3E8Mu
7yUzHewphWumgtun/niThjhKTH+fRAZV4koo35KndXpsOXAy87uW+PZc+0f33ocD
FzF8mu3eQGsXNkZ3NM/BlLN38gfQVFLiiBNxg/yPmIGqI4VcWJPVUWr51nOURL78
5NozCjr1giUXPazat0IzsvGdO9szben7al2MixufnpkojjQkB+C8r2lxVXPSC7xH
EWHPj8WVS0eLYLPW6T3t27zvLNRuORzv5y7cHS8TMc4en1qFS5NJ56ruRv7SzNQ=
=kC1q
-----END PGP SIGNATURE-----
Merge tag 'v4.7-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk updates from Heiko Stuebner:
This is first big chunk of Rockchip clock-related changes for 4.7.
Main change is probably the added support for the new rk3399 soc
and necessary infrastructure changes surrounding it.
The biggest chunk is probably that clock code is now able to
handle multiple clock providers in one system, as the rk3399
has two of those. A general one and another smaller one in a
separate power domain. The rk3399 also uses another new pll type.
Thankfully it just fits nicely into our current structure.
It also needs some parts like the cpuclk mux parameters to be
a bit more flexible and an new fractional divider subtype without
gate.
Apart from this big change we have some more fixes and removal
of forgotten variables.
* tag 'v4.7-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: add clock controller for the RK3399
dt-bindings: add bindings for rk3399 clock controller
clk: rockchip: add dt-binding header for rk3399
clk: rockchip: release io resource when failing to init clk
clk: rockchip: remove redundant checking of device_node
clk: rockchip: fix warning reported by kernel-doc
clk: rockchip: remove mux_core_reg from rockchip_cpuclk_reg_data
clk: rockchip: add new pll-type for rk3399 and similar socs
clk: rockchip: Add support for multiple clock providers
clk: rockchip: allow varying mux parameters for cpuclk pll-sources
clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type
Pull renesas clk driver updates from Geert Uytterhoeven:
- Support for the PWM module clock and watchdog related clocks on R-Car H3,
- Cleanups and clarifications.
* 'clk-renesas-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: mstp: Clarify cpg_mstp_{at,de}tach_dev() domain parameter
clk: renesas: cpg-mssr: Drop check for CONFIG_PM_GENERIC_DOMAINS_OF
clk: renesas: mstp: Drop check for CONFIG_PM_GENERIC_DOMAINS_OF
clk: renesas: r8a7795: add RWDT clock
clk: renesas: r8a7795: add R clk
clk: renesas: r8a7795: add OSC and RINT clocks
clk: renesas: cpg-mssr: add generic support for read-only DIV6 clocks
clk: renesas: r8a7795: make SD clk definition specific for GEN3
clk: renesas: r8a7795: add PWM clock
- Register SAI clk as shared clocks to support SAI audio on i.MX6SX
- Add the missing ckil clock for i.MX7
- Update clk-gate2 and vf610 clock driver to prepare for suspend
support on VF610
- Fix DCU clock configurations and add TCON ipg clock to support DRM
display on VF610
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJXDfCqAAoJEFBXWFqHsHzOg1EH/RbQ0iuyprdbHM8ItWuesWlN
rUoqLEb7HiGlKaz47HD7F47scQxuaMw+Qhj1YJapLojqRZOS2f8ZYc4WiDn0RLxU
zCBaqeyOuT8JvqbcDnSItCZAFH5XRJ5TA+8s/oCuZOfLL1pVT/pyWaulXhNDTVp3
DWhXfDEOJhy8Lyc6jb19NCwP8pceE5WW9xEHAc28WIBl8cVZjb9m4QGmWZsZK39z
4X3ckE7b+O0AaAgS9UuSEUr2WSu4oGCQ2CvHQrwdEZBMQTuC7cmhXtHFHmKl9S9f
7ROu3sMBgWx+Pbj5vcIwn5It6iEuaCnLRqiVUjY/rYHVO+VsAfA/0mLuoNsIeDQ=
=Ix59
-----END PGP SIGNATURE-----
Merge tag 'imx-clk-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next
The i.MX clock update for 4.7:
- Register SAI clk as shared clocks to support SAI audio on i.MX6SX
- Add the missing ckil clock for i.MX7
- Update clk-gate2 and vf610 clock driver to prepare for suspend
support on VF610
- Fix DCU clock configurations and add TCON ipg clock to support DRM
display on VF610
* tag 'imx-clk-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
clk: imx: vf610: fix whitespace in vf610-clock.h
clk: imx: vf610: add TCON ipg clock
clk: imx: vf610: fix DCU clock tree
clk: imx: add ckil clock for i.MX7
clk: imx: vf610: add suspend/resume support
clk: imx: vf610: add WKPU unit
clk: imx: vf610: leave DDR clock on
clk: imx: clk-gate2: allow custom gate configuration
clk: imx6sx: Register SAI clocks as shared clocks
- Fix the typo in CAN clock definition which is introduced by commit
ee36027427 ("clk: imx: Add clock support for imx6qp")
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJXDfVNAAoJEFBXWFqHsHzOoKwIALheb8malCyK2qqbYnALttq+
fj/dCWG6Qg4Z/DtoudEzNxFcskZcKjI+Apy6DA4JKS5Z+j9fF9kDYpqiOsagUC1+
FR/DmUVgRUGD8nl//xsh2akLxthgj/vGb1dvmUIYrtw0RxNrjM74c2bpmsMGFBOY
4YB2atE0sUpvy10nUBSnKzAIBp+0PKq7+bCgAxedIF7ACdGoDwk6gamF8ypH3nhe
nJHAcgkM0I2MWBTRP/esooCBegZ1fSo+UwJ6savMN8L+EMswV6cOTplxmagSd/gb
9GLun+IGCpYqx9veryARFvdT8TqIMq8BciP/ZfxyLkG4qZSuDUkF55ypv/LOsRU=
=0uIk
-----END PGP SIGNATURE-----
Merge tag 'imx-clk-fixes-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-fixes
The i.MX clk fixes for 4.6:
- Fix the typo in CAN clock definition which is introduced by commit
ee36027427 ("clk: imx: Add clock support for imx6qp")
* tag 'imx-clk-fixes-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
clk: imx6q: fix typo in CAN clock definition
(UART, MMC2 clocks) for exynos3250 SoC and exporting of IDs
for exynos543x SoC AMBA AXI bus clocks needed for bus frequency
scaling.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCAAGBQJXER7wAAoJEE1bIKeAnHqLkJIP/3QZKFAg94HtNPzmqvS8ZcyN
DADbg2V3VAWSwWz3jwXz+NQOK5IDKmCnvxHQJdnm/0HpbXRW1C413KC+f84xq0zL
Us4j7BvXemEyw2Gnv5VAiaEZ6iD/tj6HkCvq5Y12fWPFc1Bqpgf6ghxcADngc22j
wj8V1RjJ5iXjGmlqYTEPDA7OXVA4sC2HLuWiUvehW56KAlzL6UfThXweiChBiDOh
fockxKiYWVuxiFqd3GkhJGXjzK9RHzUGJSqCNjruIjyG0dekADZnm12nYjFjxym2
kL5sPI8Fo2UgzvAV8ax6Ln62uIqtzFhkZAeqkKZSJjEBryYHzAq8QVXS9iP+Ky+E
8VxZ6IGL1scoVU7g094LjyX9mP2p2PnZWvzCGdvK1qNjYzVO0ZjfXkoU71+JKoat
JxjUQ2rZTNQGb3KeqfV5SJtE8ffP+9BE+y8K4EaczdYRMqf08pKuhY9c2IHuCEs3
mpPALIVOHMSh1s58gF26tMyY3vo/04Few63S9YH/mB7LEXeH6Xs7oHHsnMvsPu3N
CVZwuQ8V/u1W4H7dCU2b9HzgqpxUfM97DbX5NtJH/1zdmpuzWVJxv8K5kT7cHRfi
IKEjhqRuNAytXojXEL1HElgsPw0THtz+qdBOAxaNwPHZCE3kBLgL4U9hKMBWewx4
oPH4MjN6xv4sbezGaas7
=Sl7j
-----END PGP SIGNATURE-----
Merge tag 'clk-v4.7-samsung' of git://linuxtv.org/snawrocki/samsung into clk-next
Pull samsung clk updates from Sylwester Nawrocki:
This includes addition of some missing clock tree definitions
(UART, MMC2 clocks) for exynos3250 SoC and exporting of IDs
for exynos543x SoC AMBA AXI bus clocks needed for bus frequency
scaling.
* tag 'clk-v4.7-samsung' of git://linuxtv.org/snawrocki/samsung:
clk: samsung: exynos542x: Add the clock id for ACLK
dt-bindings: clock: Add the clock id for ACLK clock of Exynos542x SoC
clk: samsung: exynos3250: Add MMC2 clock
clk: samsung: exynos3250: Add UART2 clock
dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250
When changing the clock-rate, currently a new parent is set first and a
divider adapted thereafter. This may result in the clock-rate overflowing
its target rate for a short time if the new parent has a higher rate than
the old parent.
While this often doesn't produce negative effects, it can affect components
in a voltage-scaling environment, like the GPU on the rk3399 socs, where
the voltage than simply is to low for the temporarily to high clock rate.
For general clock hirarchies this may need more extensive adaptions to
the common clock-framework, but at least for composite clocks having
both parent and rate settings it is easy to create a short-term solution to
make sure the clock-rate does not overflow the target.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds the clock id for ACLK clock which is source clock
of AMBA AXI bus. This clock should be handled in the bus frequency
scaling driver.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Markus Reichl <m.reichl@fivetechno.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
commit ee36027427 ("clk: imx: Add clock support for imx6qp")
introduced a regression due to a subtle typo in the 'can_root' clock
definition. The effect is that trying to configure the bitrate of the
can interfaces fails with -EDOM or produces a division by zero error
due to the clock_freq of the can serial clock being reported as '0'.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Fixes: ee36027427 ("clk: imx: Add clock support for imx6qp")
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the ipg (bus) clock for the TCON modules (Timing Controller). This
module is required by the new DCU DRM driver, since the display signals
pass through TCON.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Similar to an earlier fix for the SAI clocks, the DCU clock hierarchy
mixes the bus clock with the display controllers pixel clock. Tests
have shown that the gates in CCM_CCGR3/9 registers do not control
the DCU pixel clock, but only the register access clock (bus clock).
Fix this by defining the parent clock of VF610_CLK_DCUx to be the bus
clock (ipg_bus).
Since the clock has not been used far, there are no further changes
needed.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
rename the mcasp8_ahclk_mux to mcasp8_ahclkx_mux.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[tony@atomide.com: updated for the unit offsets]
Signed-off-by: Tony Lindgren <tony@atomide.com>
