79 lines
2.4 KiB
C
79 lines
2.4 KiB
C
/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2018 NXP
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _DFS_S32V234_H
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#define _DFS_S32V234_H
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/* DFS Control Register (DFS_CTRL) */
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#define DFS_CTRL(base) ((base) + 0x00000018)
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#define DFS_CTRL_DLL_LOLIE (1 << 0)
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#define DFS_CTRL_DLL_RESET (1 << 1)
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/* DFS Port Status (DFS_PORTSR) */
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#define DFS_PORTSR(base) ((base) + 0x0000000C)
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#define DFS_PORTSR_MASK (0x0000000F)
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#define DFS_PORTSR_OFFSET (28)
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/* DFS Port Reset Register (DFS_PORTRESET) */
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#define DFS_PORTRESET(base) ((base) + 0x00000014)
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#define DFS_PORTRESET_PORTRESET_SET(val) \
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(DFS_PORTRESET_PORTRESET_MASK | \
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(((val) & DFS_PORTRESET_PORTRESET_MAXVAL) \
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<< DFS_PORTRESET_PORTRESET_OFFSET))
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#define DFS_PORTRESET_PORTRESET_MAXVAL (0xF)
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#define DFS_PORTRESET_PORTRESET_MASK (0x0000000F)
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#define DFS_PORTRESET_PORTRESET_OFFSET (28)
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/* DFS Divide Register Portn (DFS_DVPORTn) */
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#define DFS_DVPORTn(base, n) ((base) + (0x0000001C + \
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((n) * sizeof(u32))))
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#define DFS_DVPORTn_MFI_SET(val) (DFS_DVPORTn_MFI_MASK & \
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(((val) & DFS_DVPORTn_MFI_MAXVAL) \
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<< DFS_DVPORTn_MFI_OFFSET))
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#define DFS_DVPORTn_MFN_SET(val) (DFS_DVPORTn_MFN_MASK & \
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(((val) & DFS_DVPORTn_MFN_MAXVAL) \
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<< DFS_DVPORTn_MFN_OFFSET))
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#define DFS_DVPORTn_MFI_MASK (0x0000FF00)
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#define DFS_DVPORTn_MFN_MASK (0x000000FF)
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#define DFS_DVPORTn_MFI_MAXVAL (0xFF)
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#define DFS_DVPORTn_MFN_MAXVAL (0xFF)
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#define DFS_DVPORTn_MFI_OFFSET (8)
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#define DFS_DVPORTn_MFN_OFFSET (0)
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#define DFS_MAXNUMBER (4)
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/*
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* Naming convention for PLL:
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* ARMPLL - PLL0
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* PERIPHPLL - PLL1
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* ENETPLL - PLL2
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* DDRPLL - PLL3
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* VIDEOPLL - PLL4
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*/
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/* The max values for PLL DFS is in Hz */
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/* ARMPLL */
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#define ARMPLL_DFS0_MAX_RATE (266000000)
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#define ARMPLL_DFS1_MAX_RATE (600000000)
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#define ARMPLL_DFS2_MAX_RATE (600000000)
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/* ENETPLL */
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#define ENETPLL_DFS0_MAX_RATE (350000000)
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#define ENETPLL_DFS1_MAX_RATE (350000000)
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#define ENETPLL_DFS2_MAX_RATE (416000000)
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#define ENETPLL_DFS3_MAX_RATE (104000000)
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/* DDRPLL */
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#define DDRPLL_DFS0_MAX_RATE (500000000)
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#define DDRPLL_DFS1_MAX_RATE (500000000)
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#define DDRPLL_DFS2_MAX_RATE (350000000)
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#define ARMPLL_DFS_NR (3)
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#define ENETPLL_DFS_NR (4)
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#define DDRPLL_DFS_NR (3)
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#endif
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