alistair23-linux/drivers/clk/renesas
Yoshihiro Shimoda 1ab4f43927 clk: renesas: rcar-usb2-clock-sel: Add reset_control
This hardware needs to deassert resets of both host and peripheral.
So, this patch adds reset control.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1583304137-28482-5-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-03-09 09:29:58 +01:00
..
clk-div6.c clk: renesas: div6: Combine clock-private and parent array allocation 2019-06-20 11:36:29 +02:00
clk-div6.h We have two changes to the core framework this time around. The first being a 2017-11-17 20:04:24 -08:00
clk-emev2.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-mstp.c clk: renesas: mstp: Delete unnecessary kfree() in cpg_mstp_clocks_init() 2019-10-01 09:50:28 +02:00
clk-r8a73a4.c clk: Remove io.h from clk-provider.h 2019-05-15 13:21:37 -07:00
clk-r8a7740.c clk: Remove io.h from clk-provider.h 2019-05-15 13:21:37 -07:00
clk-r8a7778.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-r8a7779.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-rz.c remove ioremap_nocache and devm_ioremap_nocache 2020-01-06 09:45:59 +01:00
clk-sh73a0.c clk: Remove io.h from clk-provider.h 2019-05-15 13:21:37 -07:00
Kconfig clk: renesas: rcar-usb2-clock-sel: Add reset_control 2020-03-09 09:29:58 +01:00
Makefile clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support 2019-11-01 13:36:39 +01:00
r7s9210-cpg-mssr.c clk: renesas: r7s9210: Add SPIBSC clock 2019-12-20 15:03:27 +01:00
r8a774a1-cpg-mssr.c clk: renesas: r8a774a1: Add TMU clock 2019-06-18 11:02:51 +02:00
r8a774b1-cpg-mssr.c clk: renesas: r8a774b1: Add TMU clock 2019-10-07 14:29:53 +02:00
r8a774c0-cpg-mssr.c clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC 2019-04-02 10:08:35 +02:00
r8a7743-cpg-mssr.c Merge branch 'clk-renesas' into clk-next 2018-10-18 15:38:51 -07:00
r8a7745-cpg-mssr.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
r8a7790-cpg-mssr.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
r8a7791-cpg-mssr.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
r8a7792-cpg-mssr.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
r8a7794-cpg-mssr.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
r8a7795-cpg-mssr.c clk: renesas: r8a7795: Add RPC clocks 2020-02-10 14:04:39 +01:00
r8a7796-cpg-mssr.c clk: renesas: r8a7796: Add RPC clocks 2020-02-10 14:04:50 +01:00
r8a77470-cpg-mssr.c scripts/spelling.txt: add spelling fix for prohibited 2019-07-12 11:05:41 -07:00
r8a77965-cpg-mssr.c clk: renesas: r8a77965: Add RPC clocks 2020-02-10 14:04:59 +01:00
r8a77970-cpg-mssr.c clk: renesas: r8a77970: Add CPEX clock 2018-12-04 10:29:48 +01:00
r8a77980-cpg-mssr.c clk: renesas: r8a77980: Fix RPC-IF module clock's parent 2019-04-02 10:31:05 +02:00
r8a77990-cpg-mssr.c clk: renesas: rcar-gen3: Add CCREE clocks 2020-02-10 14:01:03 +01:00
r8a77995-cpg-mssr.c clk: renesas: rcar-gen3: Add CCREE clocks 2020-02-10 14:01:03 +01:00
r9a06g032-clocks.c clk: renesas: r9a06g032: Set GENPD_FLAG_ALWAYS_ON for clock domain 2019-08-23 11:09:52 +02:00
rcar-gen2-cpg.c clk: renesas: rcar-gen2: Switch Z clock to .determine_rate() 2019-10-21 09:53:43 +02:00
rcar-gen2-cpg.h clk: renesas: rcar-gen2: Change multipliers and dividers to u8 2019-12-10 10:24:10 +01:00
rcar-gen3-cpg.c clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks 2019-12-20 15:02:15 +01:00
rcar-gen3-cpg.h Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and 'clk-spdx' into clk-next 2019-05-07 11:45:29 -07:00
rcar-usb2-clock-sel.c clk: renesas: rcar-usb2-clock-sel: Add reset_control 2020-03-09 09:29:58 +01:00
renesas-cpg-mssr.c clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support 2019-11-01 13:36:39 +01:00
renesas-cpg-mssr.h clk: renesas: cpg-mssr: Add r8a774b1 support 2019-10-01 10:24:38 +02:00