The layerblend units don't contain the CONTROLWORD, CURPIXELCNT,
LASTPIXELCNT and PERFCOUNTER registers, so let's remove them
and their wrappers(no one is calling them), which were introduced
accidentally.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Pixel combiner uses two display streams to drive a single display.
Either of the two display streams can be master stream and the
other slave stream. This patch supports auxiliary stream as master
stream when pixel combiner is used. The master stream ID can be
specified via the newly introduced entry 'master_stream_id' in the
device type of the DPU(s) in a particular SoC.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Store9 unit can be shared bewteen display engine(for sync mode fixup)
and blit engine. It's proper to get the store resource in the DPU
common driver and then pass it to relevant client drivers. From the
CRTC driver point of view, it's straightforward to get the store
resource via platform data instead of getting it directly, which avoids
the wrong situation where getting it twice(one time for one of the two
CRTCs of one DPU, respectively).
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Currently, when enabling/disabling vblank interrupt, we also
enable/disable the CTXLD kick interrupt. Most of the time this is fine,
because when vblank gets disabled user-space does not submit any buffers
and CTXLD kick interrupt is not needed.
There is one case when we actually need to be able to have the CTXLD
kick interrupt enabled: when disabling CRTC. Vblank interrupt, in this
case, is disabled before the crtc_atomic_disable routine is called.
However, we still need CTXLD to push the changes to SUBSAM and DTG.
This patch will create a routine just for enabling/disabling CTXLD kick
interrupt and move the code from vblank routine to the new one.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
This patch removes PM_QoS request from DCSS driver. This will allow the
A-53 cores to go idle even when DCSS is used.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
This patch adds extdst_pixengcfg_syncmode_master() helper support
so that the callers may control if a extdst is master or slave
when it works in sync mode. The bit16 of extdst's PIXENGCFG_STATIC
register controls this and it's a part of sync mode fixup logic.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds framegen_secondary_is_syncup() and
framegen_wait_for_secondary_syncup() helpers support so that
the callers may know a framegen's syncup status for the
secondary input.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Bit7 of framegen's SECSTATCONFIG register is used to control
the sync mode fixup logic implemented in framegen. This patch
adds framegen_syncmode_fixup() helper so that the callers
may enable/disable the fixup logic for a framegen.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Bit16 of store9's PIXENGCFG_STATIC register is used to control
the sync mode fixup logic implemented in store9. So, let's
add store9 support in the DPU core driver and export a function
for users to enable/disable the fixup logic.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds constframe_framedimenstions_copy_prim() helper support
so that callers may may copy frame dimensions from a primary constframe
to the relevant secondary constframe.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds pixel combiner support in the DPU core driver.
Users may get and enable/disable/control a pixel combiner instant
via tcon functions and may tell if pixel combiner is available for
a particular DPU variant via the dpu_has_pc() helper and if it is
needed in a specific usecase via the dpu_get_syncmode_min_prate()
and dpu_get_singlemode_max_width() helpers.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds side-by-side support for tcon so that
two tcons can participate in the dual display streams
to work with pixel combiner to drive a high pixel rate
display.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds side-by-side support for framegen so that
two framegens can work in sync mode to participate in the
dual display streams to drive a high pixel rate display
via a pixel combiner.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds tcon_is_master/slave() helpers support so that
callers may know if a tcon is a master or slave tcon.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds extdst_is_master() helper support so that
callers may know if a extdst is a master extdst or not.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds framegen_is_master/slave() helpers support so that
callers may know if a framegen is a master or slave framegen.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds helper framegen_syncmode() support so that callers may
control the sync mode of a framegen.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds a new di_grp_id entry in display client pdev's data
so that the relevant display platform driver may know the display
group ID of the display device.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
There are prefetch engine fixups embedded in the updated i.MX8QM silicons.
So, prefetch engines in all i.MX8 variants should be the same. Let's
remove has_prefetech_fixup from devtypes which is no more needed.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 875c31a70f3527c59cc597a10a88c39f3a0095df)
This patch will allow userspace to rotate planes by setting the
'rotation' property. Generally, 0 and 180 rotations are allowed for
pretty much all 8-bit xRGB and 2-plane YUV420 formats. 90/270 rotations
can be performed only for non-compressed tiled GPU xRGB formats. Tiled
YUV420 formats do not allow rotations at all because these formats need
DTRC for de-tiling and DTRC has no rotation support.
For more info, consult the DPR Features chapter in the reference manual.
Test example:
modetest -M imx-drm -w 27:rotation:4 -w 32:rotation:33 -w 27:alpha:30 -s
42@31:3840x2160-60@XR24 -P 32@31:3840x2160@NV21
The above will perform:
* 180 degree rotation of primary plane (XR24);
* vertical flip of first overlay plane (rotate-0 | reflect-y);
* set primary plane alpha to 30;
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
According to LCDIF specification, the input pixel data
width and the output pixel data width can be different,
and this conversion is done by LCDIF automatically. So
config the output data width according to the requested
bus format from the encoder, instead to be same with the
input pixel data width.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit bfd27f6d71d86a7f2fc8314f082565db3682b925)
According to the LCDIF specification, the Legacy Mode does not
support cropping function in the horizontal direction, so add
Pigeon Mode which can support this kind of function. And when
enable this mode, the legacy horizontal timings configuration
should use stride value but not the active width, and related
pigeon configuration should use the active width but not the
stride value.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit e6da9542693dd585972897f62748a101f5726a74)
DCSS needs PM QoS in order to keep interrupt latency low. Otherwise,
page flipping will not work smooth enough because CTXLD will not be
triggered in time.
Currently, PM QoS is requested all the time but that does not allow the
CPUs to go idle. Hence, this leads to increased power consumption.
This patch will change how PM QoS is requested by doing it only when
VBLANK is enabled/disabled. The VBLANK interrupt is enabled just before
a commit takes place and disabled after one second after last commit.
This will allow DCSS to function properly and, also, allow CPUs to go
idle whenever there's no buffer submitted.
Exception to this is when DTRC is used (when DCSS is passed tiled
buffers). In this case, PM QoS will always be active, even if no buffer
is submitted, because DTRC banks need to be switched in CTXLD ISR, so
that DCSS does not underrun. DTRC does not have the REPEAT feature, as
the rest of DCSS does.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
This patch adds a DCSS tracing mechanism that introduces as low latency
as possible, so that it does not affect timings. Instead of text, 64 bit
tags will be logged, together with the system time in nanoseconds. Based
on these, post-processing can be done on any PC to compute deltas,
delays, missed buffers, etc.
Example usage:
echo 1 > /sys/module/imx_dcss_core/parameters/tracing
gplay-1.0 movie.mpg
echo 0 > /sys/module/imx_dcss_core/parameters/tracing
To dump the trace:
cat /sys/kernel/debug/imx-dcss/dump_trace_log > trace.txt
With the help of a scripting language (awk), the trace can then be
post-processed and analyzed on the PC.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The video tearing appeared only when the application used 2 buffers.
That's because, sometimes, the context loader could be armed after the
DB event came in the frame trace. That made a buffer submitted in frame
N end up on screen in frame N+2 because the context loader waits for the
next DB event. Since vblank events are sent at the end of the frame, by
the time the buffer lands on screen, the application will reuse it while
it's being displayed, hence the tearing effect.
This patch moves the CTXLD trigger moment all the way to the end of the
frame trace, just before DB event arrives. This will leave the
application plenty of time to submit new buffers.
In the event that the trigger moment is missed (application submits a
buffer right at the end of a frame trace), then we're not signalling the
next VBLANK event to application. This way, application will know that
the buffer is still needed and will not submit a new one.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
i.MX8dx/dxp/qxp use two LDBs(one primary, one auxiliary) to support
dual channel mode. This patch adds the dual channel mode support
for i.MX8dx/dxp/qxp. Note that the drivers contain specific sequence
needed by this mode - LDB VSYNC polarity and channel selection settings
should be configured into the register a bit earlier in ->atomic_mode_set
instead of in ->enable, and DC subsystem pixel link enablement is moved
from the DPU driver to the LDB driver to make sure it happens later
than LDB clocks enablement in ->enable.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Add an function to get the LCDIF controller supported bus
formats according to the pixel format bpp. And change the
bus format sanity check in the plane's atomic check to see
if the bus format required by the peripheral attached to
LCDIF can be supported by LCDIF.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
The LCDIF core driver is responsible to provide controller
registers configuration and create the platform devices for
the child port nodes. And the platform devices later will
attach to the corresponding DRM/KMS drivers via name match.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
The framegen driver should get PLL clock, bypass clock and display
selection/mux clock via device tree if available. It may use bypass
clock when a TMDS encoder is connected with the framegen, otherwise,
PLL clock is used. This way, the assigned-clocks and assigned-clock-parents
device tree properties can be removed from the dpu device tree node.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
We use PRG x/y offset to do in-micro-tile cropping for new DPR/PRG IPs.
When tile resolving is enabled by using the new IPs, the design team
indicates that DPU fetch unit base address and DPU/PRG stride need to be
calculated in the below steps:
1) prg_Baddr = dpr_Baddr
2) tmp_dpu_Baddr = prg_Baddr + prg_x_offset * bytes_per_pixel
3) tmp_burst_size = 1 << (ffs(tmp_dpu_Baddr) - 1)
tmp_burst_size = round_up(tmp_burst_size, 8)
burst_size = min(tmp_burst_size, 128)
4) tmp_dpu_stride = dpu_width * bytes_per_pixel
5) dpu_stride =
round_up(tmp_dpu_stride + round_up(tmp_dpu_Baddr % 8, 8), burst_size)
6) dpu_Baddr = tmp_dpu_Baddr + prg_y_offset * dpu_stride
7) prg_stride = dpu_stride
The legacy DPR/PRG IPs and linear formats driver logic should not be
essentially touched.
This patch implements the above calculation method in the drivers
so that all valid in-micro-tile x/y cropping arguments can be supported.
Without this, at least, some cropping cases with odd x value would fail.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
It turns out that local alpha value of the secondary input is set to
0xFF by the hardware if the secondary input is from scaler(hscaler or
vscaler). This makes the layer on this secondary input accidentally
cover the layer with higher z-order(if it exists), even though the
layer with lower z-order doesn't supply local alpha. This patch zeros
the secondary local alpha value to prevent the issue from happening.
Users are unlikely to expect local alpha to be correctly scaled, so
it looks fine to simply zero the alpha. If we find the unlikely case,
the KMS driver may later explicitly do atomic check to invalidate the case.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch abstracts fetch unit concept for all the fetch units
we have - fetchdecode, fetcheco, fetchlayer and fetchwarp.
They have some similar features and operations which are suitable
to be abstracted. A lot of boilerplate code is removed.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds prg_put_auxiliary() helper support so that users may
set a particular PRG not serve as an auxiliary one.
Signed-off-by: Yuchou Gan <yuchou.gan@nxp.com>
Define a new struct 'dma_metadata' to hold the config parameters
for DEC400D. This struct data should be passed in from the fb's
first gem_obj's 'dma_buf' field.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Fetchdecode may work together with vscaler to do bob deinterlacing.
This patch adds the deinterlacing support for DPU DRM plane by using them.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds dpu_has_prefetch_fixup() helper support.
Users may use it to tell if a DPU has fixups for prefetch
engines in silicon or not.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds the first subsidiary layer0(out of layer0 to layer7)
support for the fetchwarp2 fetch unit to be the backend of DRM plane.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Fetchwarp is a type of dpu fetch unit with the additional
warping function. Each fetchwarp contains 8 subsidiary layers.
Fetchwarp2 can work with fetcheco2 to fetch planar YUV pixel
formats. Also, it may fetch RGB pixel formats. This patch
adds basic fetchwarp2 fetch unit support in the dpu common driver
so that it may fetch frames in RGB pixel formats. YUV pixel formats
and warping function could be supported later.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds the first subsidiary layer0(out of layer0 to layer7)
support for the fetchlayer0/1 fetch units to be the backend of DRM plane.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds some prefetch engine helpers support
in the dpu common driver so that callers may deal with
the prefetch engines of the fetch units the callers
are interested in.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Fetchlayer is a type of dpu fetch unit. Each fetchlayer
contains 8 subsidiary layers. Fetchlayer cannot work with
fetcheco to fetch planar YUV pixel formats. However, it may
fetch RGB pixel formats. This patch adds basic fetchlayer0/1
fetch units support in the dpu common driver.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds prg_set_blit() helper support so that users may
set a particular PRG to be a part of a blit channel.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
We don't have correct support for fb x/y source offset for tile formats.
The buffer address calculation is wrong when the offset is non-zero.
Also, finer offset needs a fix in silicon(TKT344978). So, let's do not
support the offset currently. We may add it back after we figure out
how the updated silicon supports the offset.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The DPR works in manual mode for the first frame and we need to
switch it to auto mode so that auto shadow load mechanism works.
The designers require us to switch the DPR manual mode to auto mode
directly for display controllers instead of using the DPR control
done irq handler, because the irq will not come in some cases(which
leads to shadow load failure). Finer switch operations on DPR
register bits are needed for SW_SHADOW_LOAD_SEL, SHADOW_LOAD_EN,
RUN_EN and REPEAT_EN. Also, for overlay planes, we need to wait for
a frame additionally in the "on-the-fly" cases to make sure the
switch is successful. In all, this patch should be able to address
frame dropping and screen tearing issue(due to the shadow load
failure) when users play video on overlay planes.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The resources for a plane group are shared by the two display streams
of one DPU. Thus, the two Framegen(fg) instances of one DPU should be
in the plane group resource. The resource users may find the fg instance
onto which the resources are built via the stream id. This patch corrects
the number of fg instances in a plane group resource from one to two.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Yong Gan