The dpu driver may properly handle display clock parent selection now.
Thus, let's remove the assigned-clock and assigned-clock-parent
device tree properties from the dpu device tree node.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The dpu driver may properly handle display clock parent selection now.
Thus, let's remove the assigned-clocks and assigned-clock-parents
device tree properties from the dpu device tree nodes.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
After the WAIT mode is enabled on imx8mm, the previous latency setting
seems can NOT meet the system the latency requirement. audio playback is
impacted by cpuidle. So increasing the latency setting as large as possible
to eliminate the impact of system performance. The latency value is not very
accurate, need to be updated after we have enough performance test result.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Optimize the pciea disable pin to drive NTB0104 device:
(NTB0104 requires at least 2 mA per data sheet)
- push-pull output
- pull disabled
- high drive strength
And the patch also change the lvds gpio to lsio gpio.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
pcie aux clock is mandatory required by pcie power management.
add the aux clock into imx8mm pcie dts node explicitly.
pcie ctrl clock would be turned on, when pcie root clock
is enabled.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
i.MX8MQ uses same GPT as i.MX7D, add i.MX7D compatible
string for GPT driver, and disable it by default.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Change the hdmi dig_pll clock rate to 675MHz,
hdmi core clock is source from dig_pll.
And HDMI CEC required core clock should integer MHz(675/5=135MHz).
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Add the pcie support for imx8mm and verify
it on imx8mm evk board when internal pll is
used as ref clock.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
The vendor tree does imx7 PGC management through regulator notifiers
while upstream implemented the same features using power domains. These
two drivers have entirely different interfaces with higher-level IP
blocks.
Resolve this conflict by moving the old code to drivers/soc and
supporting both power-domain and regulator interfaces. This effectively
merges the two drivers and is similar to how imx6sx implements both
power domains and a regulator notifier for pcie specifically.
Supporting both interfaces allows consumes to switch one-by-one, for
example by having PCI work with a power-domains reference while usb hsic
still uses the regulator enable/disable interface.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
The power domain code shares the same node and will not probe if irqchip
probes first and marks the node with OF_POPULATED.
Clearing the OF_POPULATED flag is also done in imx_gpc_init for imx6 and
imx_gpcv2_irqchip_init implemented by upstream.
In imx_4.9.y this was solved in a different way by adding a second pgc
node, see commit fab513930e78 ("MLK-14280: gpc: gpc driver not probed").
Solving the problem by clearing OF_POPULATED allows using the upstream
PGC driver without hacks.
Having two irqchip implementations with same name seems to work fine
with the mach-imx variant taking precedence.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Add micfil DAI node in dtsi and pdm sound card in dts.
We also moved ak5558 nodes into separate dts since
ak5558 uses sai5 which share some pins with micfil.
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
(cherry picked from commit 8451c6886b0175b7e1391293aa9fb461395f8485)
Enable AK4497 with mode 0. For ak4497 the same SAI interface as
for AK4458 is used, so a separate ak4497 dts is needed.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Added no_clk_reset property for 8M dts files, since DSI doesn't need
it's clocks stopped during suspend.
Also, added power on delay for 8QM and 8QXP for a better suspend/resume
stability.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
In order to enlarge the CMA easily, change the rpmsg
reserved memory region from 0xb800_0000 to 0x9000_0000.
And refine the layout of the reserved memory.
- RPMSG buffers are allocated from CMA dynamically, and have to
be accessed by M4 side. But M4 can only access the 1.5Gbytes
DDR memory from 0x8000_0000. So, the finial reserved memory
layout is just like the one below.
Thus, the largest size of the DDR memory left for CMA, is about
1212Mbytes in theory, since 32Mbytes alignment is required by
CMA allocation.
reserved-memory layout
0x8800_0000 ~ 0x8FFF_FFFF M4 + RTOS(128M)
0x9000_0000 ~ 0x903F_FFFF RPMSG Vring(4M)
0x9440_0000 ~ 0xDFFF_FFFF(MAX) CMA(1212M)(MAX)
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Regarding to the latest layout of the reserved memory
on imx8qxp, correct the rpmsg address on arm2 board too.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
When wifi driver switch to QCA CLD from ATH10K, there have one known issue:
- QCA CLD driver only support ONE instance.
So it has to disable pcie0 port.
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Since uart1 and uart3 has cts/rts lines connection, add cts/rts
support for uart1 and uart3
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
On i.mx7ULP, poweroff kernel by sending rpmsg message to M4, and
M4 poweroff CA7. Then M4 can power on CA7 again by type 'V' command
in its console or press POWERON key once M4 support POWERON.
Note: CA7 should enter VLLS mode firstly before poweroff by M4.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Enable usbotg1 and disable usbotg2, both are USB 2.0 and dual role
capable, but the typec port for usbotg2 is primary for power, and
the dead battery is not ready, so disable the typec2 and usbotg2.
Acked-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
This fixes a pinctrl error in the guest, fixing these warnings:
imx8qm-pinctrl passthrough:iomuxc: pin_config_set op failed for pin 60
imx-lpi2c 157247000.i2c: Error applying setting, reverse things back
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Remove CSI0/1 GPIO related clocks to make sure all GPIOs
clocks are always ON.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
The reserved memory for dsp is defined in dts file, however, the dsp
driver has also defined the address and size of this reserved memory,
which is repeated and inflexible.
So by cancelling the definition in dsp driver and use system API to
get the information of reserved memory from dts dynamically to fix
this problem.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
In order to enlarge the CMA easily, change the rpmsg
reserved memory region from 0xb800_0000 to 0x9000_0000.
And refine the layout of the reserved memory.
- RPMSG buffers are allocated from CMA dynamically, and have to
be accessed by M4 side. But M4 can only access the 1.5Gbytes
DDR memory from 0x8000_0000. So, the finial reserved memory
layout is just like the one below.
Thus, the largest size of the DDR memory left for CMA, is about
1212Mbytes in theory, since 32Mbytes alignment is required by
CMA allocation.
reserved-memory layout
0x8000_0000 ~ 0x83FF_FFFF A core + Linux Kernel(64M)
0x8400_0000 ~ 0x85FF_FFFF VPU encoder boot(32M)
0x8600_0000 ~ 0x87FF_FFFF VPU decoder boot(32M)
0x8800_0000 ~ 0x8FFF_FFFF M4 + RTOS(128M)
0x9000_0000 ~ 0x903F_FFFF RPMSG Vring(4M)
0x9040_0000 ~ 0x913F_FFFF VPU decoder rpc(16M)
0x9140_0000 ~ 0x923F_FFFF VPU encoder rpc(16M)
0x9240_0000 ~ 0x943F_FFFF DSP(32M)
0x9440_0000 ~ 0xDFFF_FFFF(MAX) CMA(1212M)(MAX)
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Add some necessary configs for qualcomm wifi QCA6174/QCA9377 qcacld-2.0
CLD driver and remove the ath10k configs.
(Run "make savedefconfig" to change the defconfig)
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
