i.MX8qxp uses two LDB(one primary, one auxiliary) to support dual
channel mode. This patch adds DT property descriptions for those
properties needed by this case.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
specify the spdif in imx8mm for the ipg clock is higher that
it can support 192kHz
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
Add new cell for sw_done/sw_done_selector, because PDM need enable
software done feature in sdma script.
The new fourth cell defined as below:
Bit31: sw_done
Bit15~bit0: selector
For example: 0x80000000 means sw_done enabled for done0 sector which
is for PDM on i.mx8mm.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Add the pcie support for imx8mm and verify
it on imx8mm evk board when internal pll is
used as ref clock.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
In order to avoid the name problem going forward with
integration with Qcom, Qcom has their own dsp and hifi
is competitor, so the hifi name should not be used in
our code.
So use the name of dsp instead of hifi to fix this
problem.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
NXP i.MX7ULP EVK boards all sensors connect with M4 core, A core
has to conmunicate with sensors by virtual io bus like rpmsg bus.
The driver implement the virtual sensor input driver to configure
sensors active/idle/delay actions and report the sensors' event to
user space.
Supply below sysfs for user to enable/disable detector and counter,
set poll delay:
/sys/class/misc/step_counter/enable
/sys/class/misc/step_detector/enable
/sys/class/misc/step_counter/poll_delay
Reviewed-by: Elven Wang <elven.wang@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
- To save power consumption, PHY related CLKs can be
gated off after the configurations are done.
- The impedance ratio should be configured refer to
differnet REXT values.
0x6c <--> REXT valuse is 85Ohms
Default values 0x80 <--> REXT value is 100Ohms.
- IMX8QM_HSIO_PHY_X1_APB_CLK is mandatory required when
access SATA PHY registers. Change the power domain to SATA.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Add gpio interrupt chip support that only support wakeup feature
by M4 core.
Reviewed-by: Robin Gong<yibin.gong@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
The DSI-HDMI converter, ADV7535, driver uses four i2c memory maps: MAIN,
DSI-CEC, EDID and PACKET.
While the MAIN address is hard-coded in the ROM chip, the other three
can be programmed into the MAIN memory map.
Currently, the three memory maps addresses, that can be programmed, are
hard-coded into the code.
In order to avoid conflicts with other i2c clients on the bus, update
the driver to use configurable addresses specified in DTS file.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
Note IMX7ULP has two clock domains: M4 and A7. This binding doc
is only for A7 clock domain.
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
On MX7ULP, GPIO controller needs two necessary clocks:
Port module clock and GPIO module clock.
Add them as optional clocks to use.
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
This glues SAI interface with AK4497 DAC codec on i.MX boards.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
AK4497 is a 32-bit 2ch DAC, supporting up to 6 types
of digital filters and accepts up to 768kHz PCM data
and 22.4MHz DSD data.
This is based on original code received from Asahi Kasei
with the following modifications:
* there is now a .component_driver inside snd_soc_codec_driver holding
the controls, dapm_widgets and dap_routes.
* Remove akdbgprt
* Use module_i2c_driver
* Add NXP copyright
* Use symbolic names for registers
* Fix coding style issues
* fix function parameters indentation
* remove multiple empty newlines
* convert C++ style comments to C style comments
* fix spaces and tabs at the end of the line.
* remove braces {} for single block statements
* Make pointers const
* Fix lines over 80 chars
* Don't initialize statics to 0
* Use usleep_range instead of msleep
* Fx vendor prefix
* Add DT bindings documentation for ak4497 codec
* Remove regmap default functions
* Use devm_kzalloc
* Fix MAX_REGISTERS value
* Add $self as module author
* Remove .owner field
* Make ak4497_init_reg return void
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Add machine driver for i.MX boards that have AK5558 ADC attached to SAI.
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
The AK555x series is a 32-bit, 768 kHz sampling, differential input A/D
converter for digital audio systems. The datasheet is available here:
https://www.akm.com/akm/en/file/datasheet/AK5558VN.pdf
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Add machine driver for i.MX boards that have AK4458 DAC attached to SAI.
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
The AK4458 is a 32-bit 8ch Premium DAC, its datasheet is available here:
https://www.akm.com/akm/en/file/datasheet/AK4458VN.pdf
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Add a new property "adi,dsi-channel" to allow the user specify the DSI
channel to be used when communicating with DSI peripheral.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Add max_snk_mw property for power sink to know the max power.
Because the max mw may be smaller than the max ma multiplied by
max mv:
max-mw <= max-mv*max-ma
After the power sink decides the PDO from source, it needs
to check the power to see if the provided power of this PDO
can match its requirement, which needs consider max_snk_mw to
know the max current it can have based on selected voltage.
Acked-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
Some chipidea hardware needs to disable low power mode for controller
due to IC issue or hardware issue, add one quirk for it.
Acked-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
The Display Prefetch Resolve(DPR) is a processor of fetching display data
before the display pipeline which needs data to drive pixels in the active
display region. The data is transformed, or resolved from a variety of
tiled buffer formats into linear format. The DPR transaction sequences are
issued with a high level of DRAM efficiency. This patch adds the base
driver support for i.MX8qm/qxp DPR.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The Pretch Resolve Gasket(PRG) is a digital core function as a gasket
interface between RTRAM controller and DPU. The main function of PRG
is to convert the AXI interface to RTRAM interface and remapping the
ARADDR to a RTRAM address. This patch adds the base driver support
for i.MX8qm/qxp PRG.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
For stability issues, we want to limit the maximum resolution supported
by the MXSFB (eLCDIF) driver.
This patch adds a new property which we can use to impose such
limitation.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com
To allow the PLL to become stable before enabling the clocks, we may
need a delay. This patch adds a new property to specify this delay from
DTS file.
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Add a new dt property to the nwl_dsi-imx driver: sync-pol.
This property represents the sync polarity of the input signal to it's
internal DPI-to-DSI block.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Add pdm mic support on imx8mq evk platform
Hardware modifications connect PDM mic:
PDM pin SAI-3 pad Test point
------------------------------------
BCLK SAI3_RXC TP1802
DATA SAI3_RXD TP1804
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Add definition of CAAM page 0 in the device tree.
This page is only accessible by the CPU in secure world.
this is defined by the secure-status.
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
There is already one quirk for usb3 xhci flag XHCI_MISSING_CAS, for
those platform with OF we can use usb3-resume-missing-cas to enable
this quirk to work around usb3 resume from system sleep.
Signed-off-by: Li Jun <jun.li@nxp.com>
Acked-by: Peter Chen <peter.chen@nxp.com>
TCPCI stands for typec port controller interface, its implementation
has full typec port control with power delivery support, it's a
standard i2c slave with GPIO input as irq interface, detail see spec
"Universal Serial Bus Type-C Port Controller Interface Specification
Revision 1.0, Version 1.1"
Signed-off-by: Li Jun <jun.li@nxp.com>
Acked-by: Peter Chen <peter.chen@nxp.com>
port-type is required for any typec port; default-role is only required
for drp; power source capable needs src-pdos; power sink capable needs
snk-pdos, max-snk-mv, max-snk-ma, op-snk-mw.
Signed-off-by: Li Jun <jun.li@nxp.com>
Acked-by: Peter Chen <peter.chen@nxp.com>
The JDI TX26D202VM0BWA LCD panel is a 10.1" panel
with a 1920x1200 (WUXGA) resolution.
The panel has dual LVDS channels.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
- Add the clk_req property for imx8 pcie, make sure that
the clk_req would be active.
- Correct the spell mistake of pcie pinctrl on imx8qxp.
- Fix the potential conflication with the usage of SC MU,
remove the useless "fsl,imx8-mu" of rpmsg.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Currently, the Northwest Logic MIPI-DSI controller host specific code
resides under drm/bridge, but is not a real drm_bridge. It creates a
drm_bridge and adds itself to the drm_encoder that handles this file,
but this is wrong, since it does not implement the drm_bridge_funcs.
The correct way to implement a drm_bridge is to add the drm_bridge and
let other components (another bridge or a drm_encoder) to attach to this
bridge.
Since we are doing this, a new compatible strings can be used for this
driver: "nwl,mipi-dsi".
Since this was used by nwl_dsi-imx.c, update that driver to use this
bridge correctly.
This is needed in order to add support for MIPI-DSI on 8MQ. The IMX_NWL
driver will either add a DSI encoder to DRM, or a DSI bridge.
The encoder will be used by imx-drm-core driver, while the bridge
will be used by MXSFB driver (which creates a simple display pipe).
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
- Correct the comments of iMX8QM PCIEB
- Enlarge the CFG space of iMX8QXP PCIEB.
- PCIE port maybe hard-wired in the hardware design.
Use the hard-wired property to specify it on iMX8MQ.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
On i.mx8 mscale B0 chip, AHB/SDMA clock ratio 2:1 can't be supportted,
since SDMA clock ration has to be increased to 250Mhz, AHB can't reach
to 500Mhz, so use 1:1 instead.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
This powerkey driver is a virtual driver based on scfw which control
SNVS ON/OFF in SCU side. The key interrupt triggered by MU notfication
BuildInfo:
- SCFW e7d95e1e, IMX-MKIMAGE 05d3d4a7, ATF 93dd1cc
- U-Boot 2017.03-00684-g28c5243
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Added "adi,adv7535" to the adv7511 drm bridge and adi,adv7511.txt doc,
since the driver can also support the ADV7535 chipset (upgrade of ADV7533).
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Add support for the NorthWest Logic MIPI-DSI controller found
in the following i.MX8 platforms: i.MX8qm, i.MX8qxp and i.MX8mq.
This is the MIPI-DSI encoder containing the platform specific changes
and it uses the NWL MIPI-DSI bridge.
Currently only qm and qxp are tested with this driver. The mq support
will be added later.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
