add ".use_ack" ..etc for pf1550 irq, since we have to clear irq status in
pf1550, else no any more interrupt trigged.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Correct virtual irqs macro from zero for every sub-driver of pf1550,
otherwise,below warning will be triggered:
------------[ cut here ]------------
WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:280 irq_domain_associate+0x148/0x1d4()
error: hwirq 0xb is too large for (null)
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.1.15-01689-gb67ecb6-dirty #195
Hardware name: Freescale i.MX6 Ultralite (Device Tree)
[<80015e04>] (unwind_backtrace) from [<80012754>] (show_stack+0x10/0x14)
[<80012754>] (show_stack) from [<807909c0>] (dump_stack+0x84/0xc4)
[<807909c0>] (dump_stack) from [<80034914>] (warn_slowpath_common+0x84/0xb4)
[<80034914>] (warn_slowpath_common) from [<80034974>] (warn_slowpath_fmt+0x30/0x40)
[<80034974>] (warn_slowpath_fmt) from [<800717fc>] (irq_domain_associate+0x148/0x1d4)
[<800717fc>] (irq_domain_associate) from [<80071da4>] (irq_create_mapping+0x60/0xc4)
[<80071da4>] (irq_create_mapping) from [<804910a4>] (pf1550_onkey_probe+0xe8/0x230)
[<804910a4>] (pf1550_onkey_probe) from [<803823e8>] (platform_drv_probe+0x44/0xa4)
[<803823e8>] (platform_drv_probe) from [<80380ca0>] (driver_probe_device+0x174/0x2b4)
[<80380ca0>] (driver_probe_device) from [<80380eb0>] (__driver_attach+0x8c/0x90)
[<80380eb0>] (__driver_attach) from [<8037f1e8>] (bus_for_each_dev+0x6c/0xa0)
[<8037f1e8>] (bus_for_each_dev) from [<8038043c>] (bus_add_driver+0x148/0x1f0)
[<8038043c>] (bus_add_driver) from [<803814b4>] (driver_register+0x78/0xf8)
[<803814b4>] (driver_register) from [<80009730>] (do_one_initcall+0x8c/0x1d4)
[<80009730>] (do_one_initcall) from [<80a8bdac>] (kernel_init_freeable+0x144/0x1e4)
[<80a8bdac>] (kernel_init_freeable) from [<8078ca20>] (kernel_init+0x8/0xe8)
[<8078ca20>] (kernel_init) from [<8000f568>] (ret_from_fork+0x14/0x2c)
---[ end trace dc402f301115a3b2 ]---
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
The voltage of LDO1 and LDO3 are not linear, use voltage_table instead,so
add new ops for them. Meanwhile, correct 12500uV for one step of SW1/SW2
rather than 125000uV.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
i.MX6SLL has new hardware function of bus auto clock gating,
whenerve bus is idle, its clock will be auto gated to save
power, enable this function.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
i.MX6SLL has different DRAM IO offset, and it has no
CAS/RAS/ODT/RESET pin now, correct the DRAM IO offset.
To better support all different i.MX6 SoCs and different
DRAM types, introduce a new column to store the low power
settings for DRAM IO, then suspend asm code no need to check
SoC or DRAM type, just get the DRAM IO's low power
settings from OCRAM pm_info and set to each DRAM IO.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Add SD3 support, now can support SD3.0 card. Due to the WP pin
DNP, so SD3 slot do not support write protect feature.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
On i.MX6SLL, the 'L2_PGE' bit in GPC CNTR register is set
by default,this bit must be clear, otherwise, system will
failed to resume from DSM mode if L2 cache is enabled.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Since we share the same machine code for both imx6sll and imx6sl we
need to check the CPU in order to select the right device tree
binding for the PM CCM.
Signed-off-by: Octavian Purdila <octavian.purdila@nxp.com>
Add clock driver for i.MX6SLL.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Add i.MX6SLL-LPDDR3-ARM2 board support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Add i.MX6SLL pin and clock head files.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Fix system clock topology used by lpddr2 for audio mode
Keep pll2_pfd2 as clock root for periph_pre_clk to match
lpddr2_freq_imx6q.S switching mechanism.
(Rework from commit id 427b1b6d628827ca83887b92c8331a261a254151)
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Fix switch_to_100Mhz miss to store updated podf dividers
for system clocks running at 100Mhz (audio mode)
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
After MX6ULL DCP issue is fixed in commit 7a1cc1f, it introduces a new issue,
MX6SL will meet issue as no dcp clock is defined when initializing:
[ 3.061344] mxs-dcp 20fc000.dcp: can't identify DCP clk: -2
On mx6sl, dcp clock is always on, so the patch use dummy as dcp clock directly.
Signed-off-by: Quan Zhang <spring.zhang@nxp.com>
VADC module is in i.MX6SX display power domain.
It should enabled with display power domain,
otherwise vadc will fail to be work when
display in low power mode.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
(cherry picked from commit 8ab2cc06a6900889bd61e8de6f5436523e8227d2)
To enable a IRQ as a wakeup source, we should set its interrupt parent to
gpc not the intc. Fix the wrong CAAM JR interrupts setting by removing the
its interrupt parent to use default SOC's interrupt parent "gpc". Otherwise,
irq_set_irq_wake will return error.
Signed-off-by: ye li <ye.li@nxp.com>
In order to pass the pcie gen2 compliance tests,
the external oscillator is mandatory required by
imx6 legacy platforms.
add the external osc support by this patch.
- pll6 should be set bypass mode.
- src of the pll6_bypass should be lvds_clk1
- adjust the swing/deemphase value
- re-configure the phy if the external 100Mhz
differential osc is used. Because that phy used
the 125Mhz before.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
When the external oscillator is used as pcie ref clk.
the below configurations should done.
- set the lvds_clk1 as input
- set the source of the pll6_bypass to be lvds_clk1
- set the pll6 to be bypass mode.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
In order to pass the pcie gen2 compliance tests on imx6qp
sd revb board, add one standalone imx6qp sd ldo pcie dtb
- disalbe fec/sata, because that the fec/sata can't work
when pll6 is in bypass mode.
NOTE: Bypass mode of pll6 is mandatory required when
external oscillator is used as pcie ref clk.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Robin Gong