Prepare v2016.05
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXOdxnAAoJEIf59jXTHXZSvIQQAInTqpaxpGCoiXyGmMAkaGNy cliwUE4pFQE1MW5c2ZxMjgExuT7gBq0yRO3jBWm+U1RmjbN56jw3RBwX+HOIJ8X1 7uYr2amPVvnq0ZOZpP62JCmXGiQqoLfgIlSpcLxzYg7Y1tGwvXj3ds8Tab7Iklg3 uaq0/tRjE5aTNRl0lpXLscC4VtTQSuakfuHcfwgFLQsVfY8fnoJ9cnwyBPkLVsSL +NHmMbup5ZEIOS6LOl5uLYaar8/SZ73N2gxfbrye5Ar47w4VwGeQxAOPHQUGNPB7 HErL+dMQ0att36Az9saV0ExCC76JXl/2SvG1Da8t1rJqCAfhuPQI9/GjLOoYl9e/ GuOl8uz0SzimEKqJJKAhQXebmT8fDgZ/IKQ6hPo9npQRmmMXG/tNEqomBgpxJyFO x5zCk6dfKywQkcOn1mzw6iLqiozieBkD8Xqh8lTIWo9xAS9twf5VkLYsT4qmHTap 3g3meWgZr5hxci4Hna97PSwFp32Z/lnD67Lzr6aOPi651EiOHTrddrFtoXYMCCx7 jIZ4E00tCOE/KfWRGzo0VEATYu51Iumgj49WDrPAnLBbDQC+y4PEMwLU/dkbKY4f 9bB83qFTpTWsmd8NSoGde5XMHu9uHjm5z7HcYQxiG6Swhmsi4fwv/gUXTaDeaFSB KvcIqhxiIwFwZEL/GWFw =puMF -----END PGP SIGNATURE----- Merge tag 'v2016.05' into 2016.05+fslc Prepare v2016.05 * tag 'v2016.05': (65 commits) Prepare v2016.05 sunxi: Enable USB host in CHIP defconfig test, tools: update tbot documentation tests: py: fix NameError exception if bdi cmd is not supported arm/arm64: Move barrier instructions into separate header arm: socfpga: Update iomux and pll for c5 socdk RevE warp7: Fix boot by selecting CONFIG_OF_LIBFDT usb: gadget: dfu: discard dead code dfu: avoid memory leak usb: dwc2: Add delay to fix the USB detection problem on SoCFPGA usb: hub: Don't continue on get_port_status failure usb: Assure Get Descriptor request is in separate microframe usb: Wait after sending Set Configuration request socfpga: fix broken build if CONFIG_ETH_DESIGNWARE disabled mtd: cqspi: Simplify indirect read code mtd: cqspi: Simplify indirect write code arm: socfpga: socrates: Add 'time' command ARM: socfpga: Disable USB OC protection on SoCrates usb: Don't init pointer to zero, but NULL usb: ehci-mx6: allow board_ehci_hcd_init to fail ... Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>utp
commit
158a5196a5
1
.mailmap
1
.mailmap
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@ -10,6 +10,7 @@
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||||||
|
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||||||
Allen Martin <amartin@nvidia.com>
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Allen Martin <amartin@nvidia.com>
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Andreas Bießmann <andreas.devel@googlemail.com>
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Andreas Bießmann <andreas.devel@googlemail.com>
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||||||
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Andreas Bießmann <andreas@biessmann.org>
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Aneesh V <aneesh@ti.com>
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Aneesh V <aneesh@ti.com>
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Dirk Behme <dirk.behme@googlemail.com>
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Dirk Behme <dirk.behme@googlemail.com>
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Fabio Estevam <fabio.estevam@nxp.com>
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Fabio Estevam <fabio.estevam@nxp.com>
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@ -73,7 +73,7 @@ F: arch/arm/cpu/armv7/socfpga/
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F: board/altera/socfpga/
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F: board/altera/socfpga/
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ARM ATMEL AT91
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ARM ATMEL AT91
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M: Andreas Bießmann <andreas.devel@googlemail.com>
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M: Andreas Bießmann <andreas@biessmann.org>
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S: Maintained
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S: Maintained
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T: git git://git.denx.de/u-boot-atmel.git
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T: git git://git.denx.de/u-boot-atmel.git
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F: arch/arm/mach-at91/
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F: arch/arm/mach-at91/
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@ -206,7 +206,7 @@ F: arch/arm/cpu/armv8/zynqmp/
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F: arch/arm/include/asm/arch-zynqmp/
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F: arch/arm/include/asm/arch-zynqmp/
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AVR32
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AVR32
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M: Andreas Bießmann <andreas.devel@googlemail.com>
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M: Andreas Bießmann <andreas@biessmann.org>
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S: Maintained
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S: Maintained
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T: git git://git.denx.de/u-boot-avr32.git
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T: git git://git.denx.de/u-boot-avr32.git
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F: arch/avr32/
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F: arch/avr32/
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4
Makefile
4
Makefile
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@ -5,7 +5,7 @@
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VERSION = 2016
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VERSION = 2016
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PATCHLEVEL = 05
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PATCHLEVEL = 05
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SUBLEVEL =
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SUBLEVEL =
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EXTRAVERSION = -rc3
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EXTRAVERSION =
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NAME =
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NAME =
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# *DOCUMENTATION*
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# *DOCUMENTATION*
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@ -898,7 +898,7 @@ ifdef CONFIG_SPL_LOAD_FIT
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MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
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MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
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-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
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-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
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-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
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-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
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-b $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
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$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
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else
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else
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MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
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MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
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-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
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-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
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@ -237,4 +237,5 @@ void prcm_init()
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enable_basic_clocks();
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enable_basic_clocks();
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scale_vcores();
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scale_vcores();
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setup_dplls();
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setup_dplls();
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timer_init();
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}
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}
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@ -111,6 +111,8 @@ void save_omap_boot_params(void)
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(boot_device <= MMC_BOOT_DEVICES_END)) {
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(boot_device <= MMC_BOOT_DEVICES_END)) {
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switch (boot_device) {
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switch (boot_device) {
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case BOOT_DEVICE_MMC1:
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case BOOT_DEVICE_MMC1:
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boot_mode = MMCSD_MODE_FS;
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break;
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case BOOT_DEVICE_MMC2:
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case BOOT_DEVICE_MMC2:
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boot_mode = MMCSD_MODE_RAW;
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boot_mode = MMCSD_MODE_RAW;
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break;
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break;
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@ -180,7 +180,7 @@ ulong get_ddr_freq(ulong ctrl_num)
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/*
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/*
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* DDR controller 0 & 1 are on memory complex 0
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* DDR controller 0 & 1 are on memory complex 0
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* DDR controler 2 is on memory complext 1
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* DDR controller 2 is on memory complext 1
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*/
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*/
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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if (ctrl_num >= 2)
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if (ctrl_num >= 2)
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@ -214,7 +214,9 @@ WEAK(lowlevel_init)
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ldr x1, =GICC_BASE
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ldr x1, =GICC_BASE
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bl gic_init_secure_percpu
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bl gic_init_secure_percpu
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#endif
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#endif
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#endif
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#ifndef CONFIG_ARMV8_MULTIENTRY
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branch_if_master x0, x1, 2f
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branch_if_master x0, x1, 2f
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/*
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/*
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@ -83,5 +83,6 @@
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};
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};
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&usb1 {
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&usb1 {
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disable-over-current;
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status = "okay";
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status = "okay";
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};
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};
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@ -68,7 +68,7 @@ SPL: spl/u-boot-spl.bin $(IMX_CONFIG) FORCE
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$(call if_changed,mkimage)
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$(call if_changed,mkimage)
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MKIMAGEFLAGS_u-boot.uim = -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
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MKIMAGEFLAGS_u-boot.uim = -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
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-e $(CONFIG_SYS_TEXT_BASE) -C none
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-e $(CONFIG_SYS_TEXT_BASE) -C none -T firmware
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u-boot.uim: u-boot.bin FORCE
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u-boot.uim: u-boot.bin FORCE
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$(call if_changed,mkimage)
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$(call if_changed,mkimage)
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@ -42,6 +42,12 @@ void v7_outer_cache_enable(void)
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unsigned int val;
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unsigned int val;
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/*
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* Must disable the L2 before changing the latency parameters
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* and auxiliary control register.
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*/
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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/*
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/*
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* Set bit 22 in the auxiliary control register. If this bit
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* Set bit 22 in the auxiliary control register. If this bit
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* is cleared, PL310 treats Normal Shared Non-cacheable
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* is cleared, PL310 treats Normal Shared Non-cacheable
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@ -59,9 +65,6 @@ void v7_outer_cache_enable(void)
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}
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}
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#endif
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#endif
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/* Must disable the L2 before changing the latency parameters */
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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writel(0x132, &pl310->pl310_tag_latency_ctrl);
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writel(0x132, &pl310->pl310_tag_latency_ctrl);
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writel(0x132, &pl310->pl310_data_latency_ctrl);
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writel(0x132, &pl310->pl310_data_latency_ctrl);
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@ -26,7 +26,7 @@ int tegra_gpu_enable_node(void *blob, const char *gpupath);
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#else /* CONFIG_OF_LIBFDT */
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#else /* CONFIG_OF_LIBFDT */
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static inline int tegra_gpu_enable_node(void *blob, const char *gpupath)
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static inline int tegra_gpu_enable_node(void *blob, const char *compat)
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{
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{
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return 0;
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return 0;
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}
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}
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@ -59,26 +59,7 @@
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <linux/types.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/barriers.h>
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/*
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* CP15 Barrier instructions
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* Please note that we have separate barrier instructions in ARMv7
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* However, we use the CP15 based instructtions because we use
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* -march=armv5 in U-Boot
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*/
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#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0))
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#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
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#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
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#ifdef __ARM_ARCH_7A__
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#define ISB asm volatile ("isb" : : : "memory")
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#define DSB asm volatile ("dsb" : : : "memory")
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#define DMB asm volatile ("dmb" : : : "memory")
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#else
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#define ISB CP15ISB
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#define DSB CP15DSB
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#define DMB CP15DMB
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#endif
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/*
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/*
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* Workaround for ARM errata # 798870
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* Workaround for ARM errata # 798870
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@ -0,0 +1,44 @@
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/*
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* Copyright (C) 2016 ARM Ltd.
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*
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* ARM and ARM64 barrier instructions
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* split from armv7.h to allow sharing between ARM and ARM64
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*
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* Original copyright in armv7.h was:
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* (C) Copyright 2010 Texas Instruments, <www.ti.com> Aneesh V <aneesh@ti.com>
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*
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* Much of the original barrier code was contributed by:
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* Valentine Barshak <valentine.barshak@cogentembedded.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __BARRIERS_H__
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#define __BARRIERS_H__
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#ifndef __ASSEMBLY__
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#ifndef CONFIG_ARM64
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/*
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|
* CP15 Barrier instructions
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|
* Please note that we have separate barrier instructions in ARMv7
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* However, we use the CP15 based instructtions because we use
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* -march=armv5 in U-Boot
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|
*/
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#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0))
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#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
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#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
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#endif /* !CONFIG_ARM64 */
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#if defined(__ARM_ARCH_7A__) || defined(CONFIG_ARM64)
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#define ISB asm volatile ("isb sy" : : : "memory")
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#define DSB asm volatile ("dsb sy" : : : "memory")
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#define DMB asm volatile ("dmb sy" : : : "memory")
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|
#else
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|
#define ISB CP15ISB
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#define DSB CP15DSB
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#define DMB CP15DMB
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|
#endif
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|
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|
#endif /* __ASSEMBLY__ */
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|
#endif /* __BARRIERS_H__ */
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2015 Andreas Bießmann <andreas.devel@googlemail.com>
|
* Copyright (c) 2015 Andreas Bießmann <andreas@biessmann.org>
|
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*
|
*
|
||||||
* Copyright (c) 2011 The Chromium OS Authors.
|
* Copyright (c) 2011 The Chromium OS Authors.
|
||||||
* (C) Copyright 2002-2006
|
* (C) Copyright 2002-2006
|
||||||
|
|
|
@ -2,7 +2,7 @@
|
||||||
* [partely copied from arch/arm/cpu/arm926ejs/at91/arm9260_devices.c]
|
* [partely copied from arch/arm/cpu/arm926ejs/at91/arm9260_devices.c]
|
||||||
*
|
*
|
||||||
* (C) Copyright 2011
|
* (C) Copyright 2011
|
||||||
* Andreas Bießmann <andreas.devel@googlemail.com>
|
* Andreas Bießmann <andreas@biessmann.org>
|
||||||
*
|
*
|
||||||
* (C) Copyright 2007-2008
|
* (C) Copyright 2007-2008
|
||||||
* Stelian Pop <stelian@popies.net>
|
* Stelian Pop <stelian@popies.net>
|
||||||
|
|
|
@ -2,7 +2,7 @@
|
||||||
* [origin: arch/arm/cpu/arm926ejs/at91/cpu.c]
|
* [origin: arch/arm/cpu/arm926ejs/at91/cpu.c]
|
||||||
*
|
*
|
||||||
* (C) Copyright 2011
|
* (C) Copyright 2011
|
||||||
* Andreas Bießmann, andreas.devel@googlemail.com
|
* Andreas Bießmann, andreas@biessmann.org
|
||||||
* (C) Copyright 2010
|
* (C) Copyright 2010
|
||||||
* Reinhard Meyer, reinhard.meyer@emk-elektronik.de
|
* Reinhard Meyer, reinhard.meyer@emk-elektronik.de
|
||||||
* (C) Copyright 2009
|
* (C) Copyright 2009
|
||||||
|
|
|
@ -561,14 +561,14 @@ static void dram_all_config(const struct dram_info *dram,
|
||||||
&sdram_params->ch[chan];
|
&sdram_params->ch[chan];
|
||||||
|
|
||||||
sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
|
sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
|
||||||
sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
|
sys_reg |= chan << SYS_REG_CHINFO_SHIFT(chan);
|
||||||
sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
|
sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
|
||||||
sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
|
sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
|
||||||
sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
|
sys_reg |= info->bk == 3 ? 1 << SYS_REG_BK_SHIFT(chan) : 0;
|
||||||
sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
|
sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
|
||||||
sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
|
sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
|
||||||
sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
|
sys_reg |= info->bw << SYS_REG_BW_SHIFT(chan);
|
||||||
sys_reg |= (2 >>info->dbw) << SYS_REG_DBW_SHIFT(chan);
|
sys_reg |= info->dbw << SYS_REG_DBW_SHIFT(chan);
|
||||||
|
|
||||||
dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
|
dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
|
||||||
}
|
}
|
||||||
|
@ -720,13 +720,13 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu)
|
||||||
rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
|
rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
|
||||||
SYS_REG_RANK_MASK);
|
SYS_REG_RANK_MASK);
|
||||||
col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
|
col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
|
||||||
bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK) ;
|
bk = sys_reg & (1 << SYS_REG_BK_SHIFT(ch)) ? 3 : 0;
|
||||||
cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
|
cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
|
||||||
SYS_REG_CS0_ROW_MASK);
|
SYS_REG_CS0_ROW_MASK);
|
||||||
cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
|
cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
|
||||||
SYS_REG_CS1_ROW_MASK);
|
SYS_REG_CS1_ROW_MASK);
|
||||||
bw = (2 >> (sys_reg >> SYS_REG_BW_SHIFT(ch)) &
|
bw = (sys_reg >> SYS_REG_BW_SHIFT(ch)) &
|
||||||
SYS_REG_BW_MASK);
|
SYS_REG_BW_MASK;
|
||||||
row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
|
row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
|
||||||
SYS_REG_ROW_3_4_MASK;
|
SYS_REG_ROW_3_4_MASK;
|
||||||
|
|
||||||
|
|
|
@ -172,7 +172,7 @@ static int socfpga_eth_reset(void)
|
||||||
#else
|
#else
|
||||||
static int socfpga_eth_reset(void)
|
static int socfpga_eth_reset(void)
|
||||||
{
|
{
|
||||||
return 0
|
return 0;
|
||||||
};
|
};
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
|
@ -7,6 +7,7 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
|
#include <asm/barriers.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/arch/dram.h>
|
#include <asm/arch/dram.h>
|
||||||
|
|
||||||
|
@ -31,6 +32,7 @@ bool mctl_mem_matches(u32 offset)
|
||||||
/* Try to write different values to RAM at two addresses */
|
/* Try to write different values to RAM at two addresses */
|
||||||
writel(0, CONFIG_SYS_SDRAM_BASE);
|
writel(0, CONFIG_SYS_SDRAM_BASE);
|
||||||
writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
|
writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
|
||||||
|
DSB;
|
||||||
/* Check if the same value is actually observed when reading back */
|
/* Check if the same value is actually observed when reading back */
|
||||||
return readl(CONFIG_SYS_SDRAM_BASE) ==
|
return readl(CONFIG_SYS_SDRAM_BASE) ==
|
||||||
readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);
|
readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);
|
||||||
|
|
|
@ -404,16 +404,22 @@ ulong board_get_usable_ram_top(ulong total_size)
|
||||||
*/
|
*/
|
||||||
int ft_system_setup(void *blob, bd_t *bd)
|
int ft_system_setup(void *blob, bd_t *bd)
|
||||||
{
|
{
|
||||||
const char *gpu_path =
|
const char *gpu_compats[] = {
|
||||||
#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
|
#if defined(CONFIG_TEGRA124)
|
||||||
"/gpu@0,57000000";
|
"nvidia,gk20a",
|
||||||
#else
|
|
||||||
NULL;
|
|
||||||
#endif
|
#endif
|
||||||
|
#if defined(CONFIG_TEGRA210)
|
||||||
|
"nvidia,gm20b",
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
int i, ret;
|
||||||
|
|
||||||
/* Enable GPU node if GPU setup has been performed */
|
/* Enable GPU node if GPU setup has been performed */
|
||||||
if (gpu_path != NULL)
|
for (i = 0; i < ARRAY_SIZE(gpu_compats); i++) {
|
||||||
return tegra_gpu_enable_node(blob, gpu_path);
|
ret = tegra_gpu_enable_node(blob, gpu_compats[i]);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
|
@ -33,16 +33,17 @@ void tegra_gpu_config(void)
|
||||||
|
|
||||||
#if defined(CONFIG_OF_LIBFDT)
|
#if defined(CONFIG_OF_LIBFDT)
|
||||||
|
|
||||||
int tegra_gpu_enable_node(void *blob, const char *gpupath)
|
int tegra_gpu_enable_node(void *blob, const char *compat)
|
||||||
{
|
{
|
||||||
int offset;
|
int offset;
|
||||||
|
|
||||||
if (_configured) {
|
if (!_configured)
|
||||||
offset = fdt_path_offset(blob, gpupath);
|
return 0;
|
||||||
if (offset > 0) {
|
|
||||||
fdt_status_okay(blob, offset);
|
offset = fdt_node_offset_by_compatible(blob, -1, compat);
|
||||||
debug("enabled GPU node %s\n", gpupath);
|
while (offset != -FDT_ERR_NOTFOUND) {
|
||||||
}
|
fdt_status_okay(blob, offset);
|
||||||
|
offset = fdt_node_offset_by_compatible(blob, offset, compat);
|
||||||
}
|
}
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
|
|
@ -43,7 +43,7 @@ static struct boot_device_info boot_device_table[] = {
|
||||||
{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"},
|
{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"},
|
||||||
{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"},
|
{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"},
|
||||||
{BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"},
|
{BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"},
|
||||||
{BOOT_DEVICE_NONE, "Reserved"},
|
{BOOT_DEVICE_NOR, "NOR Boot (XECS1)"},
|
||||||
};
|
};
|
||||||
|
|
||||||
static int get_boot_mode_sel(void)
|
static int get_boot_mode_sel(void)
|
||||||
|
|
|
@ -114,7 +114,7 @@ static int do_mmcsetn(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||||
|
|
||||||
U_BOOT_CMD(
|
U_BOOT_CMD(
|
||||||
mmcsetn, 1, 1, do_mmcsetn,
|
mmcsetn, 1, 1, do_mmcsetn,
|
||||||
"Set the first MMC (not SD) dev number to \"mmc_first_dev\" enviroment",
|
"Set the first MMC (not SD) dev number to \"mmc_first_dev\" environment",
|
||||||
""
|
""
|
||||||
);
|
);
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -21,6 +21,10 @@ int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd)
|
||||||
writel(tmp, SC_RSTCTRL7);
|
writel(tmp, SC_RSTCTRL7);
|
||||||
|
|
||||||
/* provide clocks */
|
/* provide clocks */
|
||||||
|
tmp = readl(SC_CLKCTRL4);
|
||||||
|
tmp |= SC_CLKCTRL4_PERI;
|
||||||
|
writel(tmp, SC_CLKCTRL4);
|
||||||
|
|
||||||
tmp = readl(SC_CLKCTRL7);
|
tmp = readl(SC_CLKCTRL7);
|
||||||
tmp |= SC_CLKCTRL7_UMCSB | SC_CLKCTRL7_UMC32 | SC_CLKCTRL7_UMC31 |
|
tmp |= SC_CLKCTRL7_UMCSB | SC_CLKCTRL7_UMC32 | SC_CLKCTRL7_UMC31 |
|
||||||
SC_CLKCTRL7_UMC30;
|
SC_CLKCTRL7_UMC30;
|
||||||
|
|
|
@ -3,3 +3,4 @@
|
||||||
#
|
#
|
||||||
|
|
||||||
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-pinctrl-sld3.o
|
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-pinctrl-sld3.o
|
||||||
|
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-pinctrl-ld20.o
|
||||||
|
|
|
@ -0,0 +1,32 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "../init.h"
|
||||||
|
#include "../sg-regs.h"
|
||||||
|
|
||||||
|
int uniphier_ld20_early_pin_init(const struct uniphier_board_data *bd)
|
||||||
|
{
|
||||||
|
/* Comment format: PAD Name -> Function Name */
|
||||||
|
sg_set_pinsel(0, 0, 8, 4); /* XECS1 -> XECS1 */
|
||||||
|
sg_set_pinsel(1, 0, 8, 4); /* ERXW -> ERXW */
|
||||||
|
sg_set_pinsel(2, 0, 8, 4); /* XERWE1 -> XERWE1 */
|
||||||
|
sg_set_pinsel(6, 2, 8, 4); /* XNFRE -> XERWE0 */
|
||||||
|
sg_set_pinsel(7, 2, 8, 4); /* XNFWE -> ES0 */
|
||||||
|
sg_set_pinsel(8, 2, 8, 4); /* NFALE -> ES1 */
|
||||||
|
sg_set_pinsel(9, 2, 8, 4); /* NFCLE -> ES2 */
|
||||||
|
sg_set_pinsel(10, 2, 8, 4); /* NFD0 -> ED0 */
|
||||||
|
sg_set_pinsel(11, 2, 8, 4); /* NFD1 -> ED1 */
|
||||||
|
sg_set_pinsel(12, 2, 8, 4); /* NFD2 -> ED2 */
|
||||||
|
sg_set_pinsel(13, 2, 8, 4); /* NFD3 -> ED3 */
|
||||||
|
sg_set_pinsel(14, 2, 8, 4); /* NFD4 -> ED4 */
|
||||||
|
sg_set_pinsel(15, 2, 8, 4); /* NFD5 -> ED5 */
|
||||||
|
sg_set_pinsel(16, 2, 8, 4); /* NFD6 -> ED6 */
|
||||||
|
sg_set_pinsel(17, 2, 8, 4); /* NFD7 -> ED7 */
|
||||||
|
sg_set_iectrl_range(0, 2);
|
||||||
|
sg_set_iectrl_range(6, 17);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
|
@ -22,5 +22,7 @@ int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd)
|
||||||
sg_set_pinsel(102, 2, 4, 4); /* TXD2 */
|
sg_set_pinsel(102, 2, 4, 4); /* TXD2 */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
sg_set_pinsel(99, 1, 4, 4); /* GPIO26 -> EA24 */
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
|
@ -37,7 +37,6 @@ int uniphier_ld20_init(const struct uniphier_board_data *bd);
|
||||||
#if defined(CONFIG_MICRO_SUPPORT_CARD)
|
#if defined(CONFIG_MICRO_SUPPORT_CARD)
|
||||||
int uniphier_sbc_init_admulti(const struct uniphier_board_data *bd);
|
int uniphier_sbc_init_admulti(const struct uniphier_board_data *bd);
|
||||||
int uniphier_sbc_init_savepin(const struct uniphier_board_data *bd);
|
int uniphier_sbc_init_savepin(const struct uniphier_board_data *bd);
|
||||||
int uniphier_sld3_sbc_init(const struct uniphier_board_data *bd);
|
|
||||||
int uniphier_ld4_sbc_init(const struct uniphier_board_data *bd);
|
int uniphier_ld4_sbc_init(const struct uniphier_board_data *bd);
|
||||||
int uniphier_pxs2_sbc_init(const struct uniphier_board_data *bd);
|
int uniphier_pxs2_sbc_init(const struct uniphier_board_data *bd);
|
||||||
#else
|
#else
|
||||||
|
@ -53,11 +52,6 @@ static inline int uniphier_sbc_init_savepin(
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline int uniphier_sld3_sbc_init(const struct uniphier_board_data *bd)
|
|
||||||
{
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline int uniphier_ld4_sbc_init(const struct uniphier_board_data *bd)
|
static inline int uniphier_ld4_sbc_init(const struct uniphier_board_data *bd)
|
||||||
{
|
{
|
||||||
return 0;
|
return 0;
|
||||||
|
@ -90,6 +84,7 @@ int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd);
|
||||||
int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd);
|
int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd);
|
||||||
|
|
||||||
int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd);
|
int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd);
|
||||||
|
int uniphier_ld20_early_pin_init(const struct uniphier_board_data *bd);
|
||||||
|
|
||||||
int uniphier_ld4_umc_init(const struct uniphier_board_data *bd);
|
int uniphier_ld4_umc_init(const struct uniphier_board_data *bd);
|
||||||
int uniphier_pro4_umc_init(const struct uniphier_board_data *bd);
|
int uniphier_pro4_umc_init(const struct uniphier_board_data *bd);
|
||||||
|
|
|
@ -13,6 +13,8 @@
|
||||||
int uniphier_ld20_init(const struct uniphier_board_data *bd)
|
int uniphier_ld20_init(const struct uniphier_board_data *bd)
|
||||||
{
|
{
|
||||||
uniphier_sbc_init_savepin(bd);
|
uniphier_sbc_init_savepin(bd);
|
||||||
|
uniphier_pxs2_sbc_init(bd);
|
||||||
|
uniphier_ld20_early_pin_init(bd);
|
||||||
|
|
||||||
support_card_reset();
|
support_card_reset();
|
||||||
|
|
||||||
|
|
|
@ -15,7 +15,8 @@ int uniphier_sld3_init(const struct uniphier_board_data *bd)
|
||||||
uniphier_sld3_bcu_init(bd);
|
uniphier_sld3_bcu_init(bd);
|
||||||
|
|
||||||
uniphier_sbc_init_admulti(bd);
|
uniphier_sbc_init_admulti(bd);
|
||||||
uniphier_sld3_sbc_init(bd);
|
|
||||||
|
uniphier_sld3_early_pin_init(bd);
|
||||||
|
|
||||||
support_card_reset();
|
support_card_reset();
|
||||||
|
|
||||||
|
@ -34,8 +35,6 @@ int uniphier_sld3_init(const struct uniphier_board_data *bd)
|
||||||
|
|
||||||
led_puts("L2");
|
led_puts("L2");
|
||||||
|
|
||||||
uniphier_sld3_early_pin_init(bd);
|
|
||||||
|
|
||||||
led_puts("L3");
|
led_puts("L3");
|
||||||
|
|
||||||
#ifdef CONFIG_SPL_SERIAL_SUPPORT
|
#ifdef CONFIG_SPL_SERIAL_SUPPORT
|
||||||
|
|
|
@ -2,11 +2,11 @@
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
#
|
#
|
||||||
|
|
||||||
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += sbc-admulti.o sbc-sld3.o
|
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += sbc-admulti.o
|
||||||
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += sbc-savepin.o sbc-ld4.o
|
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += sbc-savepin.o sbc-ld4.o
|
||||||
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += sbc-savepin.o
|
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += sbc-savepin.o
|
||||||
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += sbc-savepin.o sbc-ld4.o
|
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += sbc-savepin.o sbc-ld4.o
|
||||||
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += sbc-savepin.o
|
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += sbc-savepin.o
|
||||||
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += sbc-savepin.o sbc-pxs2.o
|
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += sbc-savepin.o sbc-pxs2.o
|
||||||
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-savepin.o sbc-pxs2.o
|
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-savepin.o sbc-pxs2.o
|
||||||
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-savepin.o
|
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-savepin.o sbc-pxs2.o
|
||||||
|
|
|
@ -1,17 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <linux/io.h>
|
|
||||||
|
|
||||||
#include "../init.h"
|
|
||||||
#include "../sg-regs.h"
|
|
||||||
|
|
||||||
int uniphier_sld3_sbc_init(const struct uniphier_board_data *bd)
|
|
||||||
{
|
|
||||||
sg_set_pinsel(99, 1, 4, 4); /* GPIO26 -> EA24 */
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
|
@ -1,6 +1,6 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (C) 2004-2006 Atmel Corporation
|
* Copyright (C) 2004-2006 Atmel Corporation
|
||||||
* Copyright (C) 2015 Andreas Bießmann <andreas.devel@googlmail.com>
|
* Copyright (C) 2015 Andreas Bießmann <andreas@biessmann.org>
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -174,7 +174,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
|
||||||
/*
|
/*
|
||||||
* allow the PREP bootm subcommand, it is required for bootm to work
|
* allow the PREP bootm subcommand, it is required for bootm to work
|
||||||
*
|
*
|
||||||
* TODO: Andreas Bießmann <andreas.devel@googlemail.com> refactor the
|
* TODO: Andreas Bießmann <andreas@biessmann.org> refactor the
|
||||||
* do_bootm_linux() for avr32
|
* do_bootm_linux() for avr32
|
||||||
*/
|
*/
|
||||||
if (flag & BOOTM_STATE_OS_PREP)
|
if (flag & BOOTM_STATE_OS_PREP)
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (C) 2015 Andreas Bießmann <andreas.devel@googlemail.com>
|
* Copyright (C) 2015 Andreas Bießmann <andreas@biessmann.org>
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -145,7 +145,7 @@ config MIPS_BOOT_ENV_LEGACY
|
||||||
Enable this option if you want U-Boot to hand over the Yamon-style
|
Enable this option if you want U-Boot to hand over the Yamon-style
|
||||||
environment to the kernel. Information like memory size, initrd
|
environment to the kernel. Information like memory size, initrd
|
||||||
address and size will be prepared as zero-terminated key/value list.
|
address and size will be prepared as zero-terminated key/value list.
|
||||||
The address of the enviroment is stored in register $a2.
|
The address of the environment is stored in register $a2.
|
||||||
|
|
||||||
config MIPS_BOOT_FDT
|
config MIPS_BOOT_FDT
|
||||||
bool "Hand over a flattened device tree to Linux kernel"
|
bool "Hand over a flattened device tree to Linux kernel"
|
||||||
|
|
|
@ -1151,7 +1151,7 @@ phys_size_t initdram(int board_type)
|
||||||
dram_size *= ranks;
|
dram_size *= ranks;
|
||||||
debug("dram_size = %lu\n", dram_size);
|
debug("dram_size = %lu\n", dram_size);
|
||||||
|
|
||||||
/* Start the SDRAM controler */
|
/* Start the SDRAM controller */
|
||||||
mtsdram(DDR0_02, DDR0_02_START_ENCODE(1));
|
mtsdram(DDR0_02, DDR0_02_START_ENCODE(1));
|
||||||
denali_wait_for_dlllock();
|
denali_wait_for_dlllock();
|
||||||
|
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2015 Andreas Bießmann <andreas.devel@googlemail.com>
|
* Copyright (c) 2015 Andreas Bießmann <andreas@biessmann.org>
|
||||||
*
|
*
|
||||||
* Copyright (c) 2011 The Chromium OS Authors.
|
* Copyright (c) 2011 The Chromium OS Authors.
|
||||||
* (C) Copyright 2002-2006
|
* (C) Copyright 2002-2006
|
||||||
|
|
|
@ -8,7 +8,7 @@
|
||||||
#define __SOCFPGA_PINMUX_CONFIG_H__
|
#define __SOCFPGA_PINMUX_CONFIG_H__
|
||||||
|
|
||||||
const u8 sys_mgr_init_table[] = {
|
const u8 sys_mgr_init_table[] = {
|
||||||
3, /* EMACIO0 */
|
0, /* EMACIO0 */
|
||||||
2, /* EMACIO1 */
|
2, /* EMACIO1 */
|
||||||
2, /* EMACIO2 */
|
2, /* EMACIO2 */
|
||||||
2, /* EMACIO3 */
|
2, /* EMACIO3 */
|
||||||
|
@ -17,7 +17,7 @@ const u8 sys_mgr_init_table[] = {
|
||||||
2, /* EMACIO6 */
|
2, /* EMACIO6 */
|
||||||
2, /* EMACIO7 */
|
2, /* EMACIO7 */
|
||||||
2, /* EMACIO8 */
|
2, /* EMACIO8 */
|
||||||
3, /* EMACIO9 */
|
0, /* EMACIO9 */
|
||||||
2, /* EMACIO10 */
|
2, /* EMACIO10 */
|
||||||
2, /* EMACIO11 */
|
2, /* EMACIO11 */
|
||||||
2, /* EMACIO12 */
|
2, /* EMACIO12 */
|
||||||
|
@ -32,27 +32,27 @@ const u8 sys_mgr_init_table[] = {
|
||||||
0, /* FLASHIO1 */
|
0, /* FLASHIO1 */
|
||||||
3, /* FLASHIO2 */
|
3, /* FLASHIO2 */
|
||||||
3, /* FLASHIO3 */
|
3, /* FLASHIO3 */
|
||||||
3, /* FLASHIO4 */
|
0, /* FLASHIO4 */
|
||||||
3, /* FLASHIO5 */
|
0, /* FLASHIO5 */
|
||||||
3, /* FLASHIO6 */
|
0, /* FLASHIO6 */
|
||||||
3, /* FLASHIO7 */
|
0, /* FLASHIO7 */
|
||||||
0, /* FLASHIO8 */
|
0, /* FLASHIO8 */
|
||||||
3, /* FLASHIO9 */
|
3, /* FLASHIO9 */
|
||||||
3, /* FLASHIO10 */
|
3, /* FLASHIO10 */
|
||||||
3, /* FLASHIO11 */
|
3, /* FLASHIO11 */
|
||||||
0, /* GENERALIO0 */
|
3, /* GENERALIO0 */
|
||||||
1, /* GENERALIO1 */
|
3, /* GENERALIO1 */
|
||||||
1, /* GENERALIO2 */
|
3, /* GENERALIO2 */
|
||||||
0, /* GENERALIO3 */
|
3, /* GENERALIO3 */
|
||||||
0, /* GENERALIO4 */
|
3, /* GENERALIO4 */
|
||||||
1, /* GENERALIO5 */
|
3, /* GENERALIO5 */
|
||||||
1, /* GENERALIO6 */
|
3, /* GENERALIO6 */
|
||||||
1, /* GENERALIO7 */
|
3, /* GENERALIO7 */
|
||||||
1, /* GENERALIO8 */
|
3, /* GENERALIO8 */
|
||||||
0, /* GENERALIO9 */
|
3, /* GENERALIO9 */
|
||||||
0, /* GENERALIO10 */
|
3, /* GENERALIO10 */
|
||||||
0, /* GENERALIO11 */
|
3, /* GENERALIO11 */
|
||||||
0, /* GENERALIO12 */
|
3, /* GENERALIO12 */
|
||||||
2, /* GENERALIO13 */
|
2, /* GENERALIO13 */
|
||||||
2, /* GENERALIO14 */
|
2, /* GENERALIO14 */
|
||||||
3, /* GENERALIO15 */
|
3, /* GENERALIO15 */
|
||||||
|
|
|
@ -10,13 +10,13 @@
|
||||||
#define CONFIG_HPS_DBCTRL_STAYOSC1 1
|
#define CONFIG_HPS_DBCTRL_STAYOSC1 1
|
||||||
|
|
||||||
#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
|
#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
|
||||||
#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
|
#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73
|
||||||
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
|
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
|
||||||
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
|
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
|
||||||
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
|
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
|
||||||
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
|
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
|
||||||
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
|
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
|
||||||
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
|
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
|
||||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
|
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
|
||||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
|
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
|
||||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
|
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
|
||||||
|
@ -27,26 +27,26 @@
|
||||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
|
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
|
||||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
|
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
|
||||||
|
|
||||||
#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 1
|
#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
|
||||||
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
|
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
|
||||||
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
|
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
|
||||||
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
|
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
|
||||||
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
|
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
|
||||||
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
|
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
|
||||||
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
|
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
|
||||||
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
|
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
|
||||||
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
|
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
|
||||||
#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
|
#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
|
||||||
#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
|
#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
|
||||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
|
#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
|
||||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
|
#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
|
||||||
#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
|
#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
|
||||||
#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
|
#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
|
||||||
#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
|
#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
|
||||||
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
|
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
|
||||||
|
|
||||||
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
|
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
|
||||||
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79
|
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
|
||||||
#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
|
#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
|
||||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
|
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
|
||||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
|
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
|
||||||
|
@ -61,25 +61,25 @@
|
||||||
#define CONFIG_HPS_CLK_OSC2_HZ 25000000
|
#define CONFIG_HPS_CLK_OSC2_HZ 25000000
|
||||||
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
|
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
|
||||||
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
|
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
|
||||||
#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
|
#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000
|
||||||
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
|
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
|
||||||
#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
|
#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
|
||||||
#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
|
#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
|
||||||
#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
|
#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
|
||||||
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
|
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
|
||||||
#define CONFIG_HPS_CLK_NAND_HZ 50000000
|
#define CONFIG_HPS_CLK_NAND_HZ 50000000
|
||||||
#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
|
#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
|
||||||
#define CONFIG_HPS_CLK_QSPI_HZ 400000000
|
#define CONFIG_HPS_CLK_QSPI_HZ 370000000
|
||||||
#define CONFIG_HPS_CLK_SPIM_HZ 200000000
|
#define CONFIG_HPS_CLK_SPIM_HZ 200000000
|
||||||
#define CONFIG_HPS_CLK_CAN0_HZ 100000000
|
#define CONFIG_HPS_CLK_CAN0_HZ 100000000
|
||||||
#define CONFIG_HPS_CLK_CAN1_HZ 100000000
|
#define CONFIG_HPS_CLK_CAN1_HZ 12500000
|
||||||
#define CONFIG_HPS_CLK_GPIODB_HZ 32000
|
#define CONFIG_HPS_CLK_GPIODB_HZ 32000
|
||||||
#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
|
#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
|
||||||
#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
|
#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
|
||||||
|
|
||||||
#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
|
#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
|
||||||
#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
|
#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
|
||||||
#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
|
#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
|
||||||
|
|
||||||
|
|
||||||
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
|
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
AT91RM9200EK BOARD
|
AT91RM9200EK BOARD
|
||||||
M: Andreas Bießmann <andreas.devel@gmail.com>
|
M: Andreas Bießmann <andreas@biessmann.org>
|
||||||
S: Maintained
|
S: Maintained
|
||||||
F: board/atmel/at91rm9200ek/
|
F: board/atmel/at91rm9200ek/
|
||||||
F: include/configs/at91rm9200ek.h
|
F: include/configs/at91rm9200ek.h
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* (C) Copyright 2010 Andreas Bießmann <andreas.devel@gmail.com>
|
* (C) Copyright 2010 Andreas Bießmann <andreas@biessmann.org>
|
||||||
*
|
*
|
||||||
* derived from previous work
|
* derived from previous work
|
||||||
*
|
*
|
||||||
|
|
|
@ -4,7 +4,7 @@
|
||||||
* Ulf Samuelsson <ulf@atmel.com>
|
* Ulf Samuelsson <ulf@atmel.com>
|
||||||
*
|
*
|
||||||
* (C) Copyright 2010
|
* (C) Copyright 2010
|
||||||
* Andreas Bießmann <andreas.devel@gmail.com>
|
* Andreas Bießmann <andreas@biessmann.org>
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
ATNGW100MKII BOARD
|
ATNGW100MKII BOARD
|
||||||
M: Andreas Bießmann <andreas.devel@googlemail.com>
|
M: Andreas Bießmann <andreas@biessmann.org>
|
||||||
S: Maintained
|
S: Maintained
|
||||||
F: board/atmel/atngw100mkii/
|
F: board/atmel/atngw100mkii/
|
||||||
F: include/configs/atngw100mkii.h
|
F: include/configs/atngw100mkii.h
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (C) 2010 Atmel Corporation
|
* Copyright (C) 2010 Atmel Corporation
|
||||||
*
|
*
|
||||||
* Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
|
* Copyright (C) 2012 Andreas Bießmann <andreas@biessmann.org>
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -320,7 +320,7 @@ int poll_toggle_bit(long lOffset)
|
||||||
}
|
}
|
||||||
timeout--;
|
timeout--;
|
||||||
}
|
}
|
||||||
printf("Time out occured \n");
|
printf("Time out occurred \n");
|
||||||
if (timeout < 0)
|
if (timeout < 0)
|
||||||
return FLASH_FAIL;
|
return FLASH_FAIL;
|
||||||
}
|
}
|
||||||
|
|
|
@ -812,9 +812,9 @@ static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img)
|
||||||
}
|
}
|
||||||
/* haddr - Address of the header of image to be validated.
|
/* haddr - Address of the header of image to be validated.
|
||||||
* arg_hash_str - Option hash string. If provided, this
|
* arg_hash_str - Option hash string. If provided, this
|
||||||
* overides the key hash in the SFP fuses.
|
* overrides the key hash in the SFP fuses.
|
||||||
* img_addr_ptr - Optional pointer to address of image to be validated.
|
* img_addr_ptr - Optional pointer to address of image to be validated.
|
||||||
* If non zero addr, this overides the addr of image in header,
|
* If non zero addr, this overrides the addr of image in header,
|
||||||
* otherwise updated to image addr in header.
|
* otherwise updated to image addr in header.
|
||||||
* Acts as both input and output of function.
|
* Acts as both input and output of function.
|
||||||
* This pointer shouldn't be NULL.
|
* This pointer shouldn't be NULL.
|
||||||
|
|
|
@ -45,7 +45,7 @@ or
|
||||||
|
|
||||||
or
|
or
|
||||||
|
|
||||||
"make mx28evk_spi_config" - store enviroment variables into SPI NOR flash
|
"make mx28evk_spi_config" - store environment variables into SPI NOR flash
|
||||||
|
|
||||||
Choose the target accordingly.
|
Choose the target accordingly.
|
||||||
|
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
GRASSHOPPER BOARD
|
GRASSHOPPER BOARD
|
||||||
M: Andreas Bießmann <andreas.devel@googlemail.com>
|
M: Andreas Bießmann <andreas@biessmann.org>
|
||||||
S: Maintained
|
S: Maintained
|
||||||
F: board/in-circuit/grasshopper/
|
F: board/in-circuit/grasshopper/
|
||||||
F: include/configs/grasshopper.h
|
F: include/configs/grasshopper.h
|
||||||
|
|
|
@ -777,7 +777,7 @@ void print_pip405_info (void)
|
||||||
((sysman & 0x10) == 0x10) ? "" : "not ");
|
((sysman & 0x10) == 0x10) ? "" : "not ");
|
||||||
printf ("INIT asserts %sINT1# (NMI)\n",
|
printf ("INIT asserts %sINT1# (NMI)\n",
|
||||||
((sysman & 0x20) == 0x20) ? "" : "not ");
|
((sysman & 0x20) == 0x20) ? "" : "not ");
|
||||||
printf ("INIT occured %d\n", (sysman >> 6) & 0x1);
|
printf ("INIT occurred %d\n", (sysman >> 6) & 0x1);
|
||||||
printf ("SER1 is routed to %s\n",
|
printf ("SER1 is routed to %s\n",
|
||||||
((flashcom & 0x1) == 0x1) ? "RS485" : "RS232");
|
((flashcom & 0x1) == 0x1) ? "RS485" : "RS232");
|
||||||
printf ("COM2 is routed to %s\n",
|
printf ("COM2 is routed to %s\n",
|
||||||
|
|
|
@ -31,6 +31,9 @@ void pinmux_init(void)
|
||||||
|
|
||||||
pinmux_config_drvgrp_table(jetson_tk1_drvgrps,
|
pinmux_config_drvgrp_table(jetson_tk1_drvgrps,
|
||||||
ARRAY_SIZE(jetson_tk1_drvgrps));
|
ARRAY_SIZE(jetson_tk1_drvgrps));
|
||||||
|
|
||||||
|
pinmux_config_mipipadctrlgrp_table(jetson_tk1_mipipadctrlgrps,
|
||||||
|
ARRAY_SIZE(jetson_tk1_mipipadctrlgrps));
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_PCI_TEGRA
|
#ifdef CONFIG_PCI_TEGRA
|
||||||
|
|
|
@ -276,7 +276,6 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
|
||||||
PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||||
PINCFG(PWR_INT_N, PMI, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
PINCFG(PWR_INT_N, PMI, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||||
PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||||
PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL),
|
|
||||||
PINCFG(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
PINCFG(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||||
PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||||
};
|
};
|
||||||
|
@ -296,4 +295,15 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
|
||||||
static const struct pmux_drvgrp_config jetson_tk1_drvgrps[] = {
|
static const struct pmux_drvgrp_config jetson_tk1_drvgrps[] = {
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#define MIPIPADCTRLCFG(_grp, _mux) \
|
||||||
|
{ \
|
||||||
|
.grp = PMUX_MIPIPADCTRLGRP_##_grp, \
|
||||||
|
.func = PMUX_FUNC_##_mux, \
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct pmux_mipipadctrlgrp_config jetson_tk1_mipipadctrlgrps[] = {
|
||||||
|
/* grp, mux */
|
||||||
|
MIPIPADCTRLCFG(DSI_B, DSI_B),
|
||||||
|
};
|
||||||
|
|
||||||
#endif /* PINMUX_CONFIG_JETSON_TK1_H */
|
#endif /* PINMUX_CONFIG_JETSON_TK1_H */
|
||||||
|
|
|
@ -72,7 +72,7 @@ static int spi_transmit(unsigned char data)
|
||||||
spi->dr = data;
|
spi->dr = data;
|
||||||
/* wait for SPI transmission completed */
|
/* wait for SPI transmission completed */
|
||||||
while (!(spi->sr & 0x80)) {
|
while (!(spi->sr & 0x80)) {
|
||||||
if (spi->sr & 0x40) { /* if write collision occured */
|
if (spi->sr & 0x40) { /* if write collision occurred */
|
||||||
int dummy;
|
int dummy;
|
||||||
|
|
||||||
/* do dummy read to clear status register */
|
/* do dummy read to clear status register */
|
||||||
|
|
|
@ -37,6 +37,10 @@
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 8
|
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 8
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifndef I2C_RXTX_LEN
|
||||||
|
#define I2C_RXTX_LEN 128
|
||||||
|
#endif
|
||||||
|
|
||||||
#define EEPROM_PAGE_SIZE (1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
|
#define EEPROM_PAGE_SIZE (1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
|
||||||
#define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1))
|
#define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1))
|
||||||
|
|
||||||
|
|
|
@ -189,7 +189,7 @@ int wait_for_fdc_int(void)
|
||||||
while((read_fdc_reg(FDC_SRA)&0x80)==0) {
|
while((read_fdc_reg(FDC_SRA)&0x80)==0) {
|
||||||
timeout--;
|
timeout--;
|
||||||
udelay(10);
|
udelay(10);
|
||||||
if(timeout==0) /* timeout occured */
|
if(timeout==0) /* timeout occurred */
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
return true;
|
return true;
|
||||||
|
@ -205,7 +205,7 @@ int read_fdc_byte(void)
|
||||||
/* direction out and ready */
|
/* direction out and ready */
|
||||||
udelay(10);
|
udelay(10);
|
||||||
timeout--;
|
timeout--;
|
||||||
if(timeout==0) /* timeout occured */
|
if(timeout==0) /* timeout occurred */
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
return read_fdc_reg(FDC_FIFO);
|
return read_fdc_reg(FDC_FIFO);
|
||||||
|
@ -235,7 +235,7 @@ int write_fdc_byte(unsigned char val)
|
||||||
timeout--;
|
timeout--;
|
||||||
udelay(10);
|
udelay(10);
|
||||||
fdc_need_more_output();
|
fdc_need_more_output();
|
||||||
if(timeout==0) /* timeout occured */
|
if(timeout==0) /* timeout occurred */
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
write_fdc_reg(FDC_FIFO,val);
|
write_fdc_reg(FDC_FIFO,val);
|
||||||
|
@ -395,7 +395,7 @@ int fdc_terminate(FDC_COMMAND_STRUCT *pCMD)
|
||||||
int i;
|
int i;
|
||||||
for(i=0;i<100;i++)
|
for(i=0;i<100;i++)
|
||||||
udelay(500); /* wait 500usec for fifo overrun */
|
udelay(500); /* wait 500usec for fifo overrun */
|
||||||
while((read_fdc_reg(FDC_SRA)&0x80)==0x00); /* wait as long as no int has occured */
|
while((read_fdc_reg(FDC_SRA)&0x80)==0x00); /* wait as long as no int has occurred */
|
||||||
for(i=0;i<7;i++) {
|
for(i=0;i<7;i++) {
|
||||||
pCMD->result[i]=(unsigned char)read_fdc_byte();
|
pCMD->result[i]=(unsigned char)read_fdc_byte();
|
||||||
}
|
}
|
||||||
|
|
|
@ -1055,7 +1055,7 @@ static char fdt_help_text[] =
|
||||||
" <start> - addr of key blob\n"
|
" <start> - addr of key blob\n"
|
||||||
" default gd->fdt_blob\n"
|
" default gd->fdt_blob\n"
|
||||||
#endif
|
#endif
|
||||||
"NOTE: Dereference aliases by omiting the leading '/', "
|
"NOTE: Dereference aliases by omitting the leading '/', "
|
||||||
"e.g. fdt print ethernet0.";
|
"e.g. fdt print ethernet0.";
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
|
@ -313,7 +313,7 @@ static int do_mmcrpmb(cmd_tbl_t *cmdtp, int flag,
|
||||||
return CMD_RET_FAILURE;
|
return CMD_RET_FAILURE;
|
||||||
}
|
}
|
||||||
/* Switch to the RPMB partition */
|
/* Switch to the RPMB partition */
|
||||||
original_part = mmc->block_dev.part_num;
|
original_part = mmc->block_dev.hwpart;
|
||||||
if (mmc_select_hwpart(curr_device, MMC_PART_RPMB) != 0)
|
if (mmc_select_hwpart(curr_device, MMC_PART_RPMB) != 0)
|
||||||
return CMD_RET_FAILURE;
|
return CMD_RET_FAILURE;
|
||||||
ret = cp->cmd(cmdtp, flag, argc, argv);
|
ret = cp->cmd(cmdtp, flag, argc, argv);
|
||||||
|
|
|
@ -1742,7 +1742,7 @@ int mtdparts_init(void)
|
||||||
debug("last_partition : %s\n", last_partition);
|
debug("last_partition : %s\n", last_partition);
|
||||||
debug("env_partition : %s\n", current_partition);
|
debug("env_partition : %s\n", current_partition);
|
||||||
|
|
||||||
/* if mtdids varible is empty try to use defaults */
|
/* if mtdids variable is empty try to use defaults */
|
||||||
if (!ids) {
|
if (!ids) {
|
||||||
if (mtdids_default) {
|
if (mtdids_default) {
|
||||||
debug("mtdids variable not defined, using default\n");
|
debug("mtdids variable not defined, using default\n");
|
||||||
|
|
|
@ -467,23 +467,31 @@ int fdt_fixup_memory(void *blob, u64 start, u64 size)
|
||||||
|
|
||||||
void fdt_fixup_ethernet(void *fdt)
|
void fdt_fixup_ethernet(void *fdt)
|
||||||
{
|
{
|
||||||
int node, i, j;
|
int i, j, prop;
|
||||||
char *tmp, *end;
|
char *tmp, *end;
|
||||||
char mac[16];
|
char mac[16];
|
||||||
const char *path;
|
const char *path;
|
||||||
unsigned char mac_addr[6];
|
unsigned char mac_addr[6];
|
||||||
int offset;
|
int offset;
|
||||||
|
|
||||||
node = fdt_path_offset(fdt, "/aliases");
|
if (fdt_path_offset(fdt, "/aliases") < 0)
|
||||||
if (node < 0)
|
|
||||||
return;
|
return;
|
||||||
|
|
||||||
for (offset = fdt_first_property_offset(fdt, node);
|
/* Cycle through all aliases */
|
||||||
offset > 0;
|
for (prop = 0; ; prop++) {
|
||||||
offset = fdt_next_property_offset(fdt, offset)) {
|
|
||||||
const char *name;
|
const char *name;
|
||||||
int len = strlen("ethernet");
|
int len = strlen("ethernet");
|
||||||
|
|
||||||
|
/* FDT might have been edited, recompute the offset */
|
||||||
|
offset = fdt_first_property_offset(fdt,
|
||||||
|
fdt_path_offset(fdt, "/aliases"));
|
||||||
|
/* Select property number 'prop' */
|
||||||
|
for (i = 0; i < prop; i++)
|
||||||
|
offset = fdt_next_property_offset(fdt, offset);
|
||||||
|
|
||||||
|
if (offset < 0)
|
||||||
|
break;
|
||||||
|
|
||||||
path = fdt_getprop_by_offset(fdt, offset, &name, NULL);
|
path = fdt_getprop_by_offset(fdt, offset, &name, NULL);
|
||||||
if (!strncmp(name, "ethernet", len)) {
|
if (!strncmp(name, "ethernet", len)) {
|
||||||
i = trailing_strtol(name);
|
i = trailing_strtol(name);
|
||||||
|
|
|
@ -326,7 +326,7 @@ handle_exception (struct pt_regs *regs)
|
||||||
return (0);
|
return (0);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* probably should check which exception occured as well */
|
/* probably should check which exception occurred as well */
|
||||||
if (longjmp_on_fault) {
|
if (longjmp_on_fault) {
|
||||||
longjmp_on_fault = 0;
|
longjmp_on_fault = 0;
|
||||||
kgdb_longjmp(error_jmp_buf, KGDBERR_MEMFAULT);
|
kgdb_longjmp(error_jmp_buf, KGDBERR_MEMFAULT);
|
||||||
|
|
18
common/usb.c
18
common/usb.c
|
@ -1064,7 +1064,7 @@ static int usb_prepare_device(struct usb_device *dev, int addr, bool do_read,
|
||||||
|
|
||||||
int usb_select_config(struct usb_device *dev)
|
int usb_select_config(struct usb_device *dev)
|
||||||
{
|
{
|
||||||
unsigned char *tmpbuf = 0;
|
unsigned char *tmpbuf = NULL;
|
||||||
int err;
|
int err;
|
||||||
|
|
||||||
err = get_descriptor_len(dev, USB_DT_DEVICE_SIZE, USB_DT_DEVICE_SIZE);
|
err = get_descriptor_len(dev, USB_DT_DEVICE_SIZE, USB_DT_DEVICE_SIZE);
|
||||||
|
@ -1077,6 +1077,14 @@ int usb_select_config(struct usb_device *dev)
|
||||||
le16_to_cpus(&dev->descriptor.idProduct);
|
le16_to_cpus(&dev->descriptor.idProduct);
|
||||||
le16_to_cpus(&dev->descriptor.bcdDevice);
|
le16_to_cpus(&dev->descriptor.bcdDevice);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Kingston DT Ultimate 32GB USB 3.0 seems to be extremely sensitive
|
||||||
|
* about this first Get Descriptor request. If there are any other
|
||||||
|
* requests in the first microframe, the stick crashes. Wait about
|
||||||
|
* one microframe duration here (1mS for USB 1.x , 125uS for USB 2.0).
|
||||||
|
*/
|
||||||
|
mdelay(1);
|
||||||
|
|
||||||
/* only support for one config for now */
|
/* only support for one config for now */
|
||||||
err = usb_get_configuration_len(dev, 0);
|
err = usb_get_configuration_len(dev, 0);
|
||||||
if (err >= 0) {
|
if (err >= 0) {
|
||||||
|
@ -1107,6 +1115,14 @@ int usb_select_config(struct usb_device *dev)
|
||||||
"len %d, status %lX\n", dev->act_len, dev->status);
|
"len %d, status %lX\n", dev->act_len, dev->status);
|
||||||
return err;
|
return err;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Wait until the Set Configuration request gets processed by the
|
||||||
|
* device. This is required by at least SanDisk Cruzer Pop USB 2.0
|
||||||
|
* and Kingston DT Ultimate 32GB USB 3.0 on DWC2 OTG controller.
|
||||||
|
*/
|
||||||
|
mdelay(10);
|
||||||
|
|
||||||
debug("new device strings: Mfr=%d, Product=%d, SerialNumber=%d\n",
|
debug("new device strings: Mfr=%d, Product=%d, SerialNumber=%d\n",
|
||||||
dev->descriptor.iManufacturer, dev->descriptor.iProduct,
|
dev->descriptor.iManufacturer, dev->descriptor.iProduct,
|
||||||
dev->descriptor.iSerialNumber);
|
dev->descriptor.iSerialNumber);
|
||||||
|
|
|
@ -402,6 +402,7 @@ static int usb_scan_port(struct usb_device_scan *usb_scan)
|
||||||
free(usb_scan);
|
free(usb_scan);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
portstatus = le16_to_cpu(portsts->wPortStatus);
|
portstatus = le16_to_cpu(portsts->wPortStatus);
|
||||||
|
@ -475,7 +476,7 @@ static int usb_scan_port(struct usb_device_scan *usb_scan)
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
/* Otherwise the device will get removed */
|
/* Otherwise the device will get removed */
|
||||||
printf("Port %d over-current occured %d times\n", i + 1,
|
printf("Port %d over-current occurred %d times\n", i + 1,
|
||||||
hub->overcurrent_count[i]);
|
hub->overcurrent_count[i]);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -32,6 +32,7 @@ CONFIG_CMD_EXT2=y
|
||||||
CONFIG_CMD_EXT4=y
|
CONFIG_CMD_EXT4=y
|
||||||
CONFIG_CMD_FAT=y
|
CONFIG_CMD_FAT=y
|
||||||
CONFIG_CMD_FS_GENERIC=y
|
CONFIG_CMD_FS_GENERIC=y
|
||||||
|
CONFIG_AXP_ALDO3_VOLT=3300
|
||||||
CONFIG_USB_EHCI_HCD=y
|
CONFIG_USB_EHCI_HCD=y
|
||||||
CONFIG_USB_MUSB_GADGET=y
|
CONFIG_USB_MUSB_GADGET=y
|
||||||
CONFIG_USB_GADGET=y
|
CONFIG_USB_GADGET=y
|
||||||
|
|
|
@ -29,3 +29,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
|
||||||
CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
|
CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
|
||||||
CONFIG_G_DNL_VENDOR_NUM=0x1f3a
|
CONFIG_G_DNL_VENDOR_NUM=0x1f3a
|
||||||
CONFIG_G_DNL_PRODUCT_NUM=0x1010
|
CONFIG_G_DNL_PRODUCT_NUM=0x1010
|
||||||
|
CONFIG_USB_EHCI_HCD=y
|
||||||
|
|
|
@ -27,6 +27,7 @@ CONFIG_CMD_DHCP=y
|
||||||
CONFIG_CMD_MII=y
|
CONFIG_CMD_MII=y
|
||||||
CONFIG_CMD_PING=y
|
CONFIG_CMD_PING=y
|
||||||
CONFIG_CMD_CACHE=y
|
CONFIG_CMD_CACHE=y
|
||||||
|
CONFIG_CMD_TIME=y
|
||||||
CONFIG_CMD_EXT4=y
|
CONFIG_CMD_EXT4=y
|
||||||
CONFIG_CMD_EXT4_WRITE=y
|
CONFIG_CMD_EXT4_WRITE=y
|
||||||
CONFIG_CMD_FAT=y
|
CONFIG_CMD_FAT=y
|
||||||
|
|
|
@ -22,3 +22,4 @@ CONFIG_CMD_EXT2=y
|
||||||
CONFIG_CMD_EXT4=y
|
CONFIG_CMD_EXT4=y
|
||||||
CONFIG_CMD_EXT4_WRITE=y
|
CONFIG_CMD_EXT4_WRITE=y
|
||||||
CONFIG_CMD_FAT=y
|
CONFIG_CMD_FAT=y
|
||||||
|
CONFIG_OF_LIBFDT=y
|
||||||
|
|
|
@ -40,7 +40,7 @@ The method for updating
|
||||||
4. Convert arch, driver and boards file to new SoC
|
4. Convert arch, driver and boards file to new SoC
|
||||||
5. remove legacy code, if all boards and drives are ready
|
5. remove legacy code, if all boards and drives are ready
|
||||||
|
|
||||||
2013-10-30 Andreas Bießmann <andreas.devel@googlemail.com>:
|
2013-10-30 Andreas Bießmann <andreas@biessmann.org>:
|
||||||
|
|
||||||
The goal is almost reached, we could remove the CONFIG_AT91_LEGACY switch but
|
The goal is almost reached, we could remove the CONFIG_AT91_LEGACY switch but
|
||||||
remain the CONFIG_ATMEL_LEGACY switch until the GPIO disaster is fixed. The
|
remain the CONFIG_ATMEL_LEGACY switch until the GPIO disaster is fixed. The
|
||||||
|
|
|
@ -30,7 +30,7 @@ Take AT91SAM9X5EK as an example, the board definition file likes:
|
||||||
|
|
||||||
How to enable PMECC header for direct programmable boot.bin
|
How to enable PMECC header for direct programmable boot.bin
|
||||||
-----------------------------------------------------------
|
-----------------------------------------------------------
|
||||||
2014-05-19 Andreas Bießmann <andreas.devel@googlemail.com>
|
2014-05-19 Andreas Bießmann <andreas@biessmann.org>
|
||||||
|
|
||||||
The usual way to program SPL into NAND flash is to use the SAM-BA Atmel tool.
|
The usual way to program SPL into NAND flash is to use the SAM-BA Atmel tool.
|
||||||
This however is often not usable when doing field updates. To be able to
|
This however is often not usable when doing field updates. To be able to
|
||||||
|
|
|
@ -10,7 +10,7 @@ export has two subcommands:
|
||||||
fdt: exports the FDT
|
fdt: exports the FDT
|
||||||
|
|
||||||
Call is:
|
Call is:
|
||||||
spl export <ftd|atags> [kernel_addr] [initrd_addr] [fdt_addr if fdt]
|
spl export <fdt|atags> [kernel_addr] [initrd_addr] [fdt_addr if fdt]
|
||||||
|
|
||||||
|
|
||||||
TYPICAL CALL
|
TYPICAL CALL
|
||||||
|
|
|
@ -34,7 +34,7 @@ U-Boot MARUBUN MR-SHPC-01 PCMCIA controller driver
|
||||||
ex. #define CONFIG_PCMCIA_SLOT_A 1
|
ex. #define CONFIG_PCMCIA_SLOT_A 1
|
||||||
|
|
||||||
* CONFIG_SYS_MARUBUN_MRSHPC
|
* CONFIG_SYS_MARUBUN_MRSHPC
|
||||||
This is MR-SHPC-01 PCMCIA controler base address.
|
This is MR-SHPC-01 PCMCIA controller base address.
|
||||||
You should do the setting matched to your environment.
|
You should do the setting matched to your environment.
|
||||||
ex. #define CONFIG_SYS_MARUBUN_MRSHPC 0xb03fffe0
|
ex. #define CONFIG_SYS_MARUBUN_MRSHPC 0xb03fffe0
|
||||||
( for MS7722SE01 environment )
|
( for MS7722SE01 environment )
|
||||||
|
|
|
@ -219,7 +219,7 @@ There are two possibilities when preparing an image writable to NAND flash.
|
||||||
|
|
||||||
This script expects a working TFTP server containing the file
|
This script expects a working TFTP server containing the file
|
||||||
"u-boot.nand" in it's root directory. This can be changed by
|
"u-boot.nand" in it's root directory. This can be changed by
|
||||||
adjusting the "update_nand_full_filename" varible.
|
adjusting the "update_nand_full_filename" variable.
|
||||||
|
|
||||||
To update the system, run the following in U-Boot prompt:
|
To update the system, run the following in U-Boot prompt:
|
||||||
|
|
||||||
|
@ -242,7 +242,7 @@ There are two possibilities when preparing an image writable to NAND flash.
|
||||||
|
|
||||||
This script expects a working TFTP server containing the file
|
This script expects a working TFTP server containing the file
|
||||||
"u-boot.sb" in it's root directory. This can be changed by
|
"u-boot.sb" in it's root directory. This can be changed by
|
||||||
adjusting the "update_nand_firmware_filename" varible.
|
adjusting the "update_nand_firmware_filename" variable.
|
||||||
|
|
||||||
To update the system, run the following in U-Boot prompt:
|
To update the system, run the following in U-Boot prompt:
|
||||||
|
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
Sandbox SPI/SPI Flash Implementation
|
Sandbox SPI/SPI Flash Implementation
|
||||||
====================================
|
====================================
|
||||||
|
|
||||||
U-Boot supports SPI and SPI flash emuation in sandbox. This must be enabled
|
U-Boot supports SPI and SPI flash emulation in sandbox. This must be enabled
|
||||||
using the --spi_sf paramter when starting U-Boot.
|
using the --spi_sf paramter when starting U-Boot.
|
||||||
|
|
||||||
For example:
|
For example:
|
||||||
|
|
|
@ -31,7 +31,7 @@ Can be used in:
|
||||||
Memory mapped read mode
|
Memory mapped read mode
|
||||||
-----------------------
|
-----------------------
|
||||||
In this, SPI controller is configured using configuration port and then
|
In this, SPI controller is configured using configuration port and then
|
||||||
controler is switched to memory mapped port for data read.
|
controller is switched to memory mapped port for data read.
|
||||||
|
|
||||||
Driver
|
Driver
|
||||||
------
|
------
|
||||||
|
|
|
@ -11,7 +11,7 @@ alias u-boot uboot
|
||||||
# Maintainer aliases. Use the same alias here as patchwork to keep
|
# Maintainer aliases. Use the same alias here as patchwork to keep
|
||||||
# things simple and easy to look up/coordinate.
|
# things simple and easy to look up/coordinate.
|
||||||
alias aaribaud Albert Aribaud <albert.u.boot@aribaud.net>
|
alias aaribaud Albert Aribaud <albert.u.boot@aribaud.net>
|
||||||
alias abiessmann Andreas Bießmann <andreas.devel@googlemail.com>
|
alias abiessmann Andreas Bießmann <andreas@biessmann.org>
|
||||||
alias abrodkin Alexey Brodkin <alexey.brodkin@synopsys.com>
|
alias abrodkin Alexey Brodkin <alexey.brodkin@synopsys.com>
|
||||||
alias afleming Andy Fleming <afleming@gmail.com>
|
alias afleming Andy Fleming <afleming@gmail.com>
|
||||||
alias ag Anatolij Gustschin <agust@denx.de>
|
alias ag Anatolij Gustschin <agust@denx.de>
|
||||||
|
|
|
@ -97,8 +97,8 @@ Set XIP (execute in place) flag.
|
||||||
.B Create FIT image:
|
.B Create FIT image:
|
||||||
|
|
||||||
.TP
|
.TP
|
||||||
.BI "\-b
|
.BI "\-b [" "device tree file" "]
|
||||||
Specifies that the following arguments are device tree binary files (.dtb).
|
Appends the device tree binary file (.dtb) to the FIT.
|
||||||
|
|
||||||
.TP
|
.TP
|
||||||
.BI "\-c [" "comment" "]"
|
.BI "\-c [" "comment" "]"
|
||||||
|
@ -211,7 +211,7 @@ automatic mode. No .its file is required.
|
||||||
.B mkimage -f auto -A arm -O linux -T kernel -C none -a 43e00000 -e 0 \\\\
|
.B mkimage -f auto -A arm -O linux -T kernel -C none -a 43e00000 -e 0 \\\\
|
||||||
.br
|
.br
|
||||||
.B -c """Kernel 4.4 image for production devices""" -d vmlinuz \\\\
|
.B -c """Kernel 4.4 image for production devices""" -d vmlinuz \\\\
|
||||||
.B -b /path/to/rk3288-firefly.dtb /path/to/rk3288-jerry.dtb kernel.itb
|
.B -b /path/to/rk3288-firefly.dtb -b /path/to/rk3288-jerry.dtb kernel.itb
|
||||||
.fi
|
.fi
|
||||||
|
|
||||||
.SH HOMEPAGE
|
.SH HOMEPAGE
|
||||||
|
|
|
@ -241,7 +241,7 @@ no segment override. Address modes such as -3[BP] or 10[BP+SI] all refer to
|
||||||
addresses relative to SS (ie: on the stack). So, at the minimum, all
|
addresses relative to SS (ie: on the stack). So, at the minimum, all
|
||||||
decodings of addressing modes would have to set/clear a bit describing
|
decodings of addressing modes would have to set/clear a bit describing
|
||||||
whether the access is relative to DS or SS. That is the function of the
|
whether the access is relative to DS or SS. That is the function of the
|
||||||
cpu-state-varible M.x86.mode. There are several potential states:
|
cpu-state-variable M.x86.mode. There are several potential states:
|
||||||
|
|
||||||
repe prefix seen (handled elsewhere)
|
repe prefix seen (handled elsewhere)
|
||||||
repne prefix seen (ditto)
|
repne prefix seen (ditto)
|
||||||
|
|
|
@ -120,7 +120,7 @@
|
||||||
#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
|
#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
|
||||||
#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
|
#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
|
||||||
#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
|
#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
|
||||||
#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */
|
#define MV_INIT_ERROR (0x16) /* Error occurred while INIT process */
|
||||||
#define MV_HW_ERROR (0x17) /* Hardware error */
|
#define MV_HW_ERROR (0x17) /* Hardware error */
|
||||||
#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
|
#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
|
||||||
#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
|
#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
|
||||||
|
|
|
@ -41,7 +41,7 @@
|
||||||
#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
|
#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
|
||||||
#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
|
#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
|
||||||
#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
|
#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
|
||||||
#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */
|
#define MV_INIT_ERROR (0x16) /* Error occurred while INIT process */
|
||||||
#define MV_HW_ERROR (0x17) /* Hardware error */
|
#define MV_HW_ERROR (0x17) /* Hardware error */
|
||||||
#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
|
#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
|
||||||
#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
|
#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
|
||||||
|
|
|
@ -3,8 +3,8 @@ menu "DFU support"
|
||||||
config DFU_TFTP
|
config DFU_TFTP
|
||||||
bool "DFU via TFTP"
|
bool "DFU via TFTP"
|
||||||
help
|
help
|
||||||
This option allows performing update of DFU managed medium with data
|
This option allows performing update of DFU-managed medium with data
|
||||||
send via TFTP boot.
|
sent via TFTP boot.
|
||||||
Detailed description of this feature can be found at ./doc/README.dfutftp
|
|
||||||
|
|
||||||
|
Detailed description of this feature can be found at ./doc/README.dfutftp
|
||||||
endmenu
|
endmenu
|
||||||
|
|
|
@ -468,8 +468,10 @@ int dfu_config_entities(char *env, char *interface, char *devstr)
|
||||||
s = strsep(&env, ";");
|
s = strsep(&env, ";");
|
||||||
ret = dfu_fill_entity(&dfu[i], s, alt_num_cnt, interface,
|
ret = dfu_fill_entity(&dfu[i], s, alt_num_cnt, interface,
|
||||||
devstr);
|
devstr);
|
||||||
if (ret)
|
if (ret) {
|
||||||
|
free(dfu);
|
||||||
return -1;
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
list_add_tail(&dfu[i].list, &dfu_list);
|
list_add_tail(&dfu[i].list, &dfu_list);
|
||||||
alt_num_cnt++;
|
alt_num_cnt++;
|
||||||
|
|
|
@ -381,7 +381,7 @@ static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev,
|
||||||
return -EREMOTEIO;
|
return -EREMOTEIO;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Check if a timeout occured */
|
/* Check if a timeout occurred */
|
||||||
if (!time_left) {
|
if (!time_left) {
|
||||||
printf("completion timed out\n");
|
printf("completion timed out\n");
|
||||||
return -EREMOTEIO;
|
return -EREMOTEIO;
|
||||||
|
|
|
@ -106,7 +106,7 @@ static uint32_t gen_true_ecc(uint8_t *ecc_buf)
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* omap_correct_data - Compares the ecc read from nand spare area with ECC
|
* omap_correct_data - Compares the ecc read from nand spare area with ECC
|
||||||
* registers values and corrects one bit error if it has occured
|
* registers values and corrects one bit error if it has occurred
|
||||||
* Further details can be had from OMAP TRM and the following selected links:
|
* Further details can be had from OMAP TRM and the following selected links:
|
||||||
* http://en.wikipedia.org/wiki/Hamming_code
|
* http://en.wikipedia.org/wiki/Hamming_code
|
||||||
* http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
|
* http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
|
||||||
|
@ -479,7 +479,7 @@ static void omap_reverse_list(u8 *list, unsigned int length)
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* omap_correct_data_bch - Compares the ecc read from nand spare area
|
* omap_correct_data_bch - Compares the ecc read from nand spare area
|
||||||
* with ECC registers values and corrects one bit error if it has occured
|
* with ECC registers values and corrects one bit error if it has occurred
|
||||||
*
|
*
|
||||||
* @mtd: MTD device structure
|
* @mtd: MTD device structure
|
||||||
* @dat: page data
|
* @dat: page data
|
||||||
|
|
|
@ -1726,7 +1726,7 @@ static void mal_err (struct eth_device *dev, unsigned long isr,
|
||||||
mtdcr (MAL0_RXDEIR, 0x80000000);
|
mtdcr (MAL0_RXDEIR, 0x80000000);
|
||||||
|
|
||||||
#ifdef INFO_4XX_ENET
|
#ifdef INFO_4XX_ENET
|
||||||
printf("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx\n",
|
printf("\nMAL error occurred.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx\n",
|
||||||
isr, uic, maldef, mal_errr);
|
isr, uic, maldef, mal_errr);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -1740,7 +1740,7 @@ static void emac_err (struct eth_device *dev, unsigned long isr)
|
||||||
{
|
{
|
||||||
EMAC_4XX_HW_PST hw_p = dev->priv;
|
EMAC_4XX_HW_PST hw_p = dev->priv;
|
||||||
|
|
||||||
printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
|
printf ("EMAC%d error occurred.... ISR = %lx\n", hw_p->devnum, isr);
|
||||||
out_be32((void *)EMAC0_ISR + hw_p->hw_addr, isr);
|
out_be32((void *)EMAC0_ISR + hw_p->hw_addr, isr);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -381,7 +381,7 @@ static int enc_phy_link_wait(enc_dev_t *enc)
|
||||||
udelay(1000);
|
udelay(1000);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* timeout occured */
|
/* timeout occurred */
|
||||||
printf("%s: link down\n", enc->dev->name);
|
printf("%s: link down\n", enc->dev->name);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
|
@ -920,6 +920,7 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv)
|
||||||
struct dpni_tx_conf_cfg tx_conf_cfg;
|
struct dpni_tx_conf_cfg tx_conf_cfg;
|
||||||
int err = 0;
|
int err = 0;
|
||||||
|
|
||||||
|
memset(&pools_params, 0, sizeof(pools_params));
|
||||||
pools_params.num_dpbp = 1;
|
pools_params.num_dpbp = 1;
|
||||||
pools_params.pools[0].dpbp_id = (uint16_t)dflt_dpbp->dpbp_attr.id;
|
pools_params.pools[0].dpbp_id = (uint16_t)dflt_dpbp->dpbp_attr.id;
|
||||||
pools_params.pools[0].buffer_size = LDPAA_ETH_RX_BUFFER_SIZE;
|
pools_params.pools[0].buffer_size = LDPAA_ETH_RX_BUFFER_SIZE;
|
||||||
|
|
|
@ -120,7 +120,7 @@ static int macb_is_gem(struct macb_device *macb)
|
||||||
static int gem_is_gigabit_capable(struct macb_device *macb)
|
static int gem_is_gigabit_capable(struct macb_device *macb)
|
||||||
{
|
{
|
||||||
/*
|
/*
|
||||||
* The GEM controllers embeded in SAMA5D2 and SAMA5D4 are
|
* The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
|
||||||
* configured to support only 10/100.
|
* configured to support only 10/100.
|
||||||
*/
|
*/
|
||||||
return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
|
return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
|
||||||
|
|
|
@ -582,7 +582,7 @@ dp83902a_Overflow(void)
|
||||||
/*
|
/*
|
||||||
* Read in as many packets as we can and acknowledge any and receive
|
* Read in as many packets as we can and acknowledge any and receive
|
||||||
* interrupts. Since the buffer has overflowed, a receive event of
|
* interrupts. Since the buffer has overflowed, a receive event of
|
||||||
* some kind will have occured.
|
* some kind will have occurred.
|
||||||
*/
|
*/
|
||||||
dp83902a_RxEvent();
|
dp83902a_RxEvent();
|
||||||
DP_OUT(base, DP_ISR, DP_ISR_RxP|DP_ISR_RxE);
|
DP_OUT(base, DP_ISR, DP_ISR_RxP|DP_ISR_RxE);
|
||||||
|
@ -592,7 +592,7 @@ dp83902a_Overflow(void)
|
||||||
DP_OUT(base, DP_TCR, DP_TCR_NORMAL);
|
DP_OUT(base, DP_TCR, DP_TCR_NORMAL);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* If a transmit command was issued, but no transmit event has occured,
|
* If a transmit command was issued, but no transmit event has occurred,
|
||||||
* restart it here.
|
* restart it here.
|
||||||
*/
|
*/
|
||||||
DP_IN(base, DP_ISR, isr);
|
DP_IN(base, DP_ISR, isr);
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* sh_eth.c - Driver for Renesas ethernet controler.
|
* sh_eth.c - Driver for Renesas ethernet controller.
|
||||||
*
|
*
|
||||||
* Copyright (C) 2008, 2011 Renesas Solutions Corp.
|
* Copyright (C) 2008, 2011 Renesas Solutions Corp.
|
||||||
* Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
|
* Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* sh_eth.h - Driver for Renesas SuperH ethernet controler.
|
* sh_eth.h - Driver for Renesas SuperH ethernet controller.
|
||||||
*
|
*
|
||||||
* Copyright (C) 2008 - 2012 Renesas Solutions Corp.
|
* Copyright (C) 2008 - 2012 Renesas Solutions Corp.
|
||||||
* Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
|
* Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
|
||||||
|
|
|
@ -275,12 +275,17 @@ static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf,
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
return -EFAULT;
|
||||||
} else {
|
} else {
|
||||||
|
#ifdef CONFIG_TEGRA20
|
||||||
|
unsigned int dev = PCI_DEV(bdf);
|
||||||
|
if (dev != 0)
|
||||||
|
return -EFAULT;
|
||||||
|
#endif
|
||||||
|
|
||||||
*address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where);
|
*address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
return -EFAULT;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int pci_tegra_read_config(struct udevice *bus, pci_dev_t bdf,
|
static int pci_tegra_read_config(struct udevice *bus, pci_dev_t bdf,
|
||||||
|
@ -299,13 +304,15 @@ static int pci_tegra_read_config(struct udevice *bus, pci_dev_t bdf,
|
||||||
|
|
||||||
value = readl(address);
|
value = readl(address);
|
||||||
|
|
||||||
|
#ifdef CONFIG_TEGRA20
|
||||||
/* fixup root port class */
|
/* fixup root port class */
|
||||||
if (PCI_BUS(bdf) == 0) {
|
if (PCI_BUS(bdf) == 0) {
|
||||||
if (offset == PCI_CLASS_REVISION) {
|
if ((offset & ~3) == PCI_CLASS_REVISION) {
|
||||||
value &= ~0x00ff0000;
|
value &= ~0x00ff0000;
|
||||||
value |= PCI_CLASS_BRIDGE_PCI << 16;
|
value |= PCI_CLASS_BRIDGE_PCI << 16;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
done:
|
done:
|
||||||
*valuep = pci_conv_32_to_size(value, offset, size);
|
*valuep = pci_conv_32_to_size(value, offset, size);
|
||||||
|
@ -1041,11 +1048,3 @@ U_BOOT_DRIVER(pci_tegra) = {
|
||||||
.probe = pci_tegra_probe,
|
.probe = pci_tegra_probe,
|
||||||
.priv_auto_alloc_size = sizeof(struct tegra_pcie),
|
.priv_auto_alloc_size = sizeof(struct tegra_pcie),
|
||||||
};
|
};
|
||||||
|
|
||||||
int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
|
|
||||||
{
|
|
||||||
if (PCI_BUS(dev) != 0 && PCI_DEV(dev) > 0)
|
|
||||||
return 1;
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
|
@ -28,6 +28,7 @@
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/errno.h>
|
#include <asm/errno.h>
|
||||||
|
#include <wait_bit.h>
|
||||||
#include "cadence_qspi.h"
|
#include "cadence_qspi.h"
|
||||||
|
|
||||||
#define CQSPI_REG_POLL_US (1) /* 1us */
|
#define CQSPI_REG_POLL_US (1) /* 1us */
|
||||||
|
@ -192,128 +193,6 @@ static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
|
||||||
return addr;
|
return addr;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void cadence_qspi_apb_read_fifo_data(void *dest,
|
|
||||||
const void *src_ahb_addr, unsigned int bytes)
|
|
||||||
{
|
|
||||||
unsigned int temp;
|
|
||||||
int remaining = bytes;
|
|
||||||
unsigned int *dest_ptr = (unsigned int *)dest;
|
|
||||||
unsigned int *src_ptr = (unsigned int *)src_ahb_addr;
|
|
||||||
|
|
||||||
while (remaining >= sizeof(dest_ptr)) {
|
|
||||||
*dest_ptr = readl(src_ptr);
|
|
||||||
remaining -= sizeof(src_ptr);
|
|
||||||
dest_ptr++;
|
|
||||||
}
|
|
||||||
if (remaining) {
|
|
||||||
/* dangling bytes */
|
|
||||||
temp = readl(src_ptr);
|
|
||||||
memcpy(dest_ptr, &temp, remaining);
|
|
||||||
}
|
|
||||||
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
|
|
||||||
const void *src, unsigned int bytes)
|
|
||||||
{
|
|
||||||
unsigned int temp = 0;
|
|
||||||
int i;
|
|
||||||
int remaining = bytes;
|
|
||||||
unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;
|
|
||||||
unsigned int *src_ptr = (unsigned int *)src;
|
|
||||||
|
|
||||||
while (remaining >= CQSPI_FIFO_WIDTH) {
|
|
||||||
for (i = CQSPI_FIFO_WIDTH/sizeof(src_ptr) - 1; i >= 0; i--)
|
|
||||||
writel(*(src_ptr+i), dest_ptr+i);
|
|
||||||
src_ptr += CQSPI_FIFO_WIDTH/sizeof(src_ptr);
|
|
||||||
remaining -= CQSPI_FIFO_WIDTH;
|
|
||||||
}
|
|
||||||
if (remaining) {
|
|
||||||
/* dangling bytes */
|
|
||||||
i = remaining/sizeof(dest_ptr);
|
|
||||||
memcpy(&temp, src_ptr+i, remaining % sizeof(dest_ptr));
|
|
||||||
writel(temp, dest_ptr+i);
|
|
||||||
for (--i; i >= 0; i--)
|
|
||||||
writel(*(src_ptr+i), dest_ptr+i);
|
|
||||||
}
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Read from SRAM FIFO with polling SRAM fill level. */
|
|
||||||
static int qspi_read_sram_fifo_poll(const void *reg_base, void *dest_addr,
|
|
||||||
const void *src_addr, unsigned int num_bytes)
|
|
||||||
{
|
|
||||||
unsigned int remaining = num_bytes;
|
|
||||||
unsigned int retry;
|
|
||||||
unsigned int sram_level = 0;
|
|
||||||
unsigned char *dest = (unsigned char *)dest_addr;
|
|
||||||
|
|
||||||
while (remaining > 0) {
|
|
||||||
retry = CQSPI_REG_RETRY;
|
|
||||||
while (retry--) {
|
|
||||||
sram_level = CQSPI_GET_RD_SRAM_LEVEL(reg_base);
|
|
||||||
if (sram_level)
|
|
||||||
break;
|
|
||||||
udelay(1);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!retry) {
|
|
||||||
printf("QSPI: No receive data after polling for %d times\n",
|
|
||||||
CQSPI_REG_RETRY);
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
||||||
sram_level *= CQSPI_FIFO_WIDTH;
|
|
||||||
sram_level = sram_level > remaining ? remaining : sram_level;
|
|
||||||
|
|
||||||
/* Read data from FIFO. */
|
|
||||||
cadence_qspi_apb_read_fifo_data(dest, src_addr, sram_level);
|
|
||||||
dest += sram_level;
|
|
||||||
remaining -= sram_level;
|
|
||||||
udelay(1);
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Write to SRAM FIFO with polling SRAM fill level. */
|
|
||||||
static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat,
|
|
||||||
const void *src_addr, unsigned int num_bytes)
|
|
||||||
{
|
|
||||||
const void *reg_base = plat->regbase;
|
|
||||||
void *dest_addr = plat->ahbbase;
|
|
||||||
unsigned int retry = CQSPI_REG_RETRY;
|
|
||||||
unsigned int sram_level;
|
|
||||||
unsigned int wr_bytes;
|
|
||||||
unsigned char *src = (unsigned char *)src_addr;
|
|
||||||
int remaining = num_bytes;
|
|
||||||
unsigned int page_size = plat->page_size;
|
|
||||||
unsigned int sram_threshold_words = CQSPI_REG_SRAM_THRESHOLD_WORDS;
|
|
||||||
|
|
||||||
while (remaining > 0) {
|
|
||||||
retry = CQSPI_REG_RETRY;
|
|
||||||
while (retry--) {
|
|
||||||
sram_level = CQSPI_GET_WR_SRAM_LEVEL(reg_base);
|
|
||||||
if (sram_level <= sram_threshold_words)
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
if (!retry) {
|
|
||||||
printf("QSPI: SRAM fill level (0x%08x) not hit lower expected level (0x%08x)",
|
|
||||||
sram_level, sram_threshold_words);
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
/* Write a page or remaining bytes. */
|
|
||||||
wr_bytes = (remaining > page_size) ?
|
|
||||||
page_size : remaining;
|
|
||||||
|
|
||||||
cadence_qspi_apb_write_fifo_data(dest_addr, src, wr_bytes);
|
|
||||||
src += wr_bytes;
|
|
||||||
remaining -= wr_bytes;
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
void cadence_qspi_apb_controller_enable(void *reg_base)
|
void cadence_qspi_apb_controller_enable(void *reg_base)
|
||||||
{
|
{
|
||||||
unsigned int reg;
|
unsigned int reg;
|
||||||
|
@ -742,40 +621,84 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
|
static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)
|
||||||
unsigned int rxlen, u8 *rxbuf)
|
|
||||||
{
|
{
|
||||||
unsigned int reg;
|
u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
|
||||||
|
reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
|
||||||
|
return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
|
||||||
|
}
|
||||||
|
|
||||||
writel(rxlen, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
|
static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
|
||||||
|
{
|
||||||
|
unsigned int timeout = 10000;
|
||||||
|
u32 reg;
|
||||||
|
|
||||||
|
while (timeout--) {
|
||||||
|
reg = cadence_qspi_get_rd_sram_level(plat);
|
||||||
|
if (reg)
|
||||||
|
return reg;
|
||||||
|
udelay(1);
|
||||||
|
}
|
||||||
|
|
||||||
|
return -ETIMEDOUT;
|
||||||
|
}
|
||||||
|
|
||||||
|
int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
|
||||||
|
unsigned int n_rx, u8 *rxbuf)
|
||||||
|
{
|
||||||
|
unsigned int remaining = n_rx;
|
||||||
|
unsigned int bytes_to_read = 0;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
|
||||||
|
|
||||||
/* Start the indirect read transfer */
|
/* Start the indirect read transfer */
|
||||||
writel(CQSPI_REG_INDIRECTRD_START_MASK,
|
writel(CQSPI_REG_INDIRECTRD_START_MASK,
|
||||||
plat->regbase + CQSPI_REG_INDIRECTRD);
|
plat->regbase + CQSPI_REG_INDIRECTRD);
|
||||||
|
|
||||||
if (qspi_read_sram_fifo_poll(plat->regbase, (void *)rxbuf,
|
while (remaining > 0) {
|
||||||
(const void *)plat->ahbbase, rxlen))
|
ret = cadence_qspi_wait_for_data(plat);
|
||||||
goto failrd;
|
if (ret < 0) {
|
||||||
|
printf("Indirect write timed out (%i)\n", ret);
|
||||||
|
goto failrd;
|
||||||
|
}
|
||||||
|
|
||||||
/* Check flash indirect controller */
|
bytes_to_read = ret;
|
||||||
reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
|
|
||||||
if (!(reg & CQSPI_REG_INDIRECTRD_DONE_MASK)) {
|
while (bytes_to_read != 0) {
|
||||||
reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
|
bytes_to_read *= CQSPI_FIFO_WIDTH;
|
||||||
printf("QSPI: indirect completion status error with reg 0x%08x\n",
|
bytes_to_read = bytes_to_read > remaining ?
|
||||||
reg);
|
remaining : bytes_to_read;
|
||||||
|
/* Handle non-4-byte aligned access to avoid data abort. */
|
||||||
|
if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
|
||||||
|
readsb(plat->ahbbase, rxbuf, bytes_to_read);
|
||||||
|
else
|
||||||
|
readsl(plat->ahbbase, rxbuf, bytes_to_read >> 2);
|
||||||
|
rxbuf += bytes_to_read;
|
||||||
|
remaining -= bytes_to_read;
|
||||||
|
bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check indirect done status */
|
||||||
|
ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTRD,
|
||||||
|
CQSPI_REG_INDIRECTRD_DONE_MASK, 1, 10, 0);
|
||||||
|
if (ret) {
|
||||||
|
printf("Indirect read completion error (%i)\n", ret);
|
||||||
goto failrd;
|
goto failrd;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Clear indirect completion status */
|
/* Clear indirect completion status */
|
||||||
writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
|
writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
|
||||||
plat->regbase + CQSPI_REG_INDIRECTRD);
|
plat->regbase + CQSPI_REG_INDIRECTRD);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
failrd:
|
failrd:
|
||||||
/* Cancel the indirect read */
|
/* Cancel the indirect read */
|
||||||
writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
|
writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
|
||||||
plat->regbase + CQSPI_REG_INDIRECTRD);
|
plat->regbase + CQSPI_REG_INDIRECTRD);
|
||||||
return -1;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Opcode + Address (3/4 bytes) */
|
/* Opcode + Address (3/4 bytes) */
|
||||||
|
@ -810,48 +733,45 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
|
||||||
}
|
}
|
||||||
|
|
||||||
int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
|
int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
|
||||||
unsigned int txlen, const u8 *txbuf)
|
unsigned int n_tx, const u8 *txbuf)
|
||||||
{
|
{
|
||||||
unsigned int reg = 0;
|
unsigned int page_size = plat->page_size;
|
||||||
unsigned int retry;
|
unsigned int remaining = n_tx;
|
||||||
|
unsigned int write_bytes;
|
||||||
|
int ret;
|
||||||
|
|
||||||
/* Configure the indirect read transfer bytes */
|
/* Configure the indirect read transfer bytes */
|
||||||
writel(txlen, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
|
writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
|
||||||
|
|
||||||
/* Start the indirect write transfer */
|
/* Start the indirect write transfer */
|
||||||
writel(CQSPI_REG_INDIRECTWR_START_MASK,
|
writel(CQSPI_REG_INDIRECTWR_START_MASK,
|
||||||
plat->regbase + CQSPI_REG_INDIRECTWR);
|
plat->regbase + CQSPI_REG_INDIRECTWR);
|
||||||
|
|
||||||
if (qpsi_write_sram_fifo_push(plat, (const void *)txbuf, txlen))
|
while (remaining > 0) {
|
||||||
goto failwr;
|
write_bytes = remaining > page_size ? page_size : remaining;
|
||||||
|
/* Handle non-4-byte aligned access to avoid data abort. */
|
||||||
|
if (((uintptr_t)txbuf % 4) || (write_bytes % 4))
|
||||||
|
writesb(plat->ahbbase, txbuf, write_bytes);
|
||||||
|
else
|
||||||
|
writesl(plat->ahbbase, txbuf, write_bytes >> 2);
|
||||||
|
|
||||||
/* Wait until last write is completed (FIFO empty) */
|
ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL,
|
||||||
retry = CQSPI_REG_RETRY;
|
CQSPI_REG_SDRAMLEVEL_WR_MASK <<
|
||||||
while (retry--) {
|
CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
|
||||||
reg = CQSPI_GET_WR_SRAM_LEVEL(plat->regbase);
|
if (ret) {
|
||||||
if (reg == 0)
|
printf("Indirect write timed out (%i)\n", ret);
|
||||||
break;
|
goto failwr;
|
||||||
|
}
|
||||||
|
|
||||||
udelay(1);
|
txbuf += write_bytes;
|
||||||
|
remaining -= write_bytes;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (reg != 0) {
|
/* Check indirect done status */
|
||||||
printf("QSPI: timeout for indirect write\n");
|
ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTWR,
|
||||||
goto failwr;
|
CQSPI_REG_INDIRECTWR_DONE_MASK, 1, 10, 0);
|
||||||
}
|
if (ret) {
|
||||||
|
printf("Indirect write completion error (%i)\n", ret);
|
||||||
/* Check flash indirect controller status */
|
|
||||||
retry = CQSPI_REG_RETRY;
|
|
||||||
while (retry--) {
|
|
||||||
reg = readl(plat->regbase + CQSPI_REG_INDIRECTWR);
|
|
||||||
if (reg & CQSPI_REG_INDIRECTWR_DONE_MASK)
|
|
||||||
break;
|
|
||||||
udelay(1);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!(reg & CQSPI_REG_INDIRECTWR_DONE_MASK)) {
|
|
||||||
printf("QSPI: indirect completion status error with reg 0x%08x\n",
|
|
||||||
reg);
|
|
||||||
goto failwr;
|
goto failwr;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -864,7 +784,7 @@ failwr:
|
||||||
/* Cancel the indirect write */
|
/* Cancel the indirect write */
|
||||||
writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
|
writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
|
||||||
plat->regbase + CQSPI_REG_INDIRECTWR);
|
plat->regbase + CQSPI_REG_INDIRECTWR);
|
||||||
return -1;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
|
void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
config DM_THERMAL
|
config DM_THERMAL
|
||||||
bool "Driver support for thermal devices"
|
bool "Driver support for thermal devices"
|
||||||
help
|
help
|
||||||
Enable support for temporary-sensing devices. Some SoCs have on-chip
|
Enable support for temperature-sensing devices. Some SoCs have on-chip
|
||||||
temperature sensors to permit warnings, speed throttling or even
|
temperature sensors to permit warnings, speed throttling or even
|
||||||
automatic power-off when the temperature gets too high or low. Other
|
automatic power-off when the temperature gets too high or low. Other
|
||||||
devices may be discrete but connected on a suitable bus.
|
devices may be discrete but connected on a suitable bus.
|
||||||
|
|
|
@ -636,7 +636,7 @@ dfu_prepare_strings(struct f_dfu *f_dfu, int n)
|
||||||
|
|
||||||
f_dfu->strings = calloc(sizeof(struct usb_string), n + 1);
|
f_dfu->strings = calloc(sizeof(struct usb_string), n + 1);
|
||||||
if (!f_dfu->strings)
|
if (!f_dfu->strings)
|
||||||
goto enomem;
|
return -ENOMEM;
|
||||||
|
|
||||||
for (i = 0; i < n; ++i) {
|
for (i = 0; i < n; ++i) {
|
||||||
de = dfu_get_entity(i);
|
de = dfu_get_entity(i);
|
||||||
|
@ -647,14 +647,6 @@ dfu_prepare_strings(struct f_dfu *f_dfu, int n)
|
||||||
f_dfu->strings[i].s = NULL;
|
f_dfu->strings[i].s = NULL;
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
enomem:
|
|
||||||
while (i)
|
|
||||||
f_dfu->strings[--i].s = NULL;
|
|
||||||
|
|
||||||
free(f_dfu->strings);
|
|
||||||
|
|
||||||
return -ENOMEM;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int dfu_prepare_function(struct f_dfu *f_dfu, int n)
|
static int dfu_prepare_function(struct f_dfu *f_dfu, int n)
|
||||||
|
|
|
@ -170,7 +170,7 @@ int udc_init (void)
|
||||||
|
|
||||||
/* udc_irq
|
/* udc_irq
|
||||||
*
|
*
|
||||||
* Poll for whatever events may have occured
|
* Poll for whatever events may have occurred
|
||||||
*/
|
*/
|
||||||
void udc_irq (void)
|
void udc_irq (void)
|
||||||
{
|
{
|
||||||
|
|
|
@ -18,6 +18,8 @@
|
||||||
|
|
||||||
#include "dwc2.h"
|
#include "dwc2.h"
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
/* Use only HC channel 0. */
|
/* Use only HC channel 0. */
|
||||||
#define DWC2_HC_CHANNEL 0
|
#define DWC2_HC_CHANNEL 0
|
||||||
|
|
||||||
|
@ -39,6 +41,8 @@ struct dwc2_priv {
|
||||||
u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
|
u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
|
||||||
struct dwc2_core_regs *regs;
|
struct dwc2_core_regs *regs;
|
||||||
int root_hub_devnum;
|
int root_hub_devnum;
|
||||||
|
bool ext_vbus;
|
||||||
|
bool oc_disable;
|
||||||
};
|
};
|
||||||
|
|
||||||
#ifndef CONFIG_DM_USB
|
#ifndef CONFIG_DM_USB
|
||||||
|
@ -252,8 +256,9 @@ static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
|
||||||
*
|
*
|
||||||
* @param regs Programming view of the DWC_otg controller
|
* @param regs Programming view of the DWC_otg controller
|
||||||
*/
|
*/
|
||||||
static void dwc_otg_core_init(struct dwc2_core_regs *regs)
|
static void dwc_otg_core_init(struct dwc2_priv *priv)
|
||||||
{
|
{
|
||||||
|
struct dwc2_core_regs *regs = priv->regs;
|
||||||
uint32_t ahbcfg = 0;
|
uint32_t ahbcfg = 0;
|
||||||
uint32_t usbcfg = 0;
|
uint32_t usbcfg = 0;
|
||||||
uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
|
uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
|
||||||
|
@ -262,13 +267,15 @@ static void dwc_otg_core_init(struct dwc2_core_regs *regs)
|
||||||
usbcfg = readl(®s->gusbcfg);
|
usbcfg = readl(®s->gusbcfg);
|
||||||
|
|
||||||
/* Program the ULPI External VBUS bit if needed */
|
/* Program the ULPI External VBUS bit if needed */
|
||||||
#ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
|
if (priv->ext_vbus) {
|
||||||
usbcfg |= (DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV |
|
usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
|
||||||
DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
|
if (!priv->oc_disable) {
|
||||||
DWC2_GUSBCFG_INDICATOR_PASSTHROUGH);
|
usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
|
||||||
#else
|
DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
|
||||||
usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
|
}
|
||||||
#endif
|
} else {
|
||||||
|
usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
|
||||||
|
}
|
||||||
|
|
||||||
/* Set external TS Dline pulsing */
|
/* Set external TS Dline pulsing */
|
||||||
#ifdef CONFIG_DWC2_TS_DLINE
|
#ifdef CONFIG_DWC2_TS_DLINE
|
||||||
|
@ -1056,7 +1063,13 @@ static int dwc2_init_common(struct dwc2_priv *priv)
|
||||||
return -ENODEV;
|
return -ENODEV;
|
||||||
}
|
}
|
||||||
|
|
||||||
dwc_otg_core_init(regs);
|
#ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
|
||||||
|
priv->ext_vbus = 1;
|
||||||
|
#else
|
||||||
|
priv->ext_vbus = 0;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
dwc_otg_core_init(priv);
|
||||||
dwc_otg_core_host_init(regs);
|
dwc_otg_core_host_init(regs);
|
||||||
|
|
||||||
clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
|
clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
|
||||||
|
@ -1075,6 +1088,15 @@ static int dwc2_init_common(struct dwc2_priv *priv)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Add a 1 second delay here. This gives the host controller
|
||||||
|
* a bit time before the comminucation with the USB devices
|
||||||
|
* is started (the bus is scanned) and fixes the USB detection
|
||||||
|
* problems with some problematic USB keys.
|
||||||
|
*/
|
||||||
|
if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
|
||||||
|
mdelay(1000);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1169,6 +1191,7 @@ static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
|
||||||
static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
|
static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
|
||||||
{
|
{
|
||||||
struct dwc2_priv *priv = dev_get_priv(dev);
|
struct dwc2_priv *priv = dev_get_priv(dev);
|
||||||
|
const void *prop;
|
||||||
fdt_addr_t addr;
|
fdt_addr_t addr;
|
||||||
|
|
||||||
addr = dev_get_addr(dev);
|
addr = dev_get_addr(dev);
|
||||||
|
@ -1176,12 +1199,20 @@ static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
priv->regs = (struct dwc2_core_regs *)addr;
|
priv->regs = (struct dwc2_core_regs *)addr;
|
||||||
|
|
||||||
|
prop = fdt_getprop(gd->fdt_blob, dev->of_offset, "disable-over-current",
|
||||||
|
NULL);
|
||||||
|
if (prop)
|
||||||
|
priv->oc_disable = true;
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int dwc2_usb_probe(struct udevice *dev)
|
static int dwc2_usb_probe(struct udevice *dev)
|
||||||
{
|
{
|
||||||
struct dwc2_priv *priv = dev_get_priv(dev);
|
struct dwc2_priv *priv = dev_get_priv(dev);
|
||||||
|
struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
|
||||||
|
|
||||||
|
bus_priv->desc_before_addr = true;
|
||||||
|
|
||||||
return dwc2_init_common(priv);
|
return dwc2_init_common(priv);
|
||||||
}
|
}
|
||||||
|
|
|
@ -254,7 +254,7 @@ static void usb_oc_config(int index)
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* board_ehci_hcd_init - override usb phy mode
|
* board_usb_phy_mode - override usb phy mode
|
||||||
* @port: usb host/otg port
|
* @port: usb host/otg port
|
||||||
*
|
*
|
||||||
* Target board specific, override usb_phy_mode.
|
* Target board specific, override usb_phy_mode.
|
||||||
|
@ -310,6 +310,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
|
||||||
#endif
|
#endif
|
||||||
struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
|
struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
|
||||||
(controller_spacing * index));
|
(controller_spacing * index));
|
||||||
|
int ret;
|
||||||
|
|
||||||
if (index > 3)
|
if (index > 3)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
@ -317,7 +318,9 @@ int ehci_hcd_init(int index, enum usb_init_type init,
|
||||||
mdelay(1);
|
mdelay(1);
|
||||||
|
|
||||||
/* Do board specific initialization */
|
/* Do board specific initialization */
|
||||||
board_ehci_hcd_init(index);
|
ret = board_ehci_hcd_init(index);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
usb_power_config(index);
|
usb_power_config(index);
|
||||||
usb_oc_config(index);
|
usb_oc_config(index);
|
||||||
|
|
|
@ -73,9 +73,9 @@ static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* This function checks if RxStall has occured on the endpoint. If a RxStall
|
* This function checks if RxStall has occurred on the endpoint. If a RxStall
|
||||||
* has occured, the RxStall is cleared and 1 is returned. If RxStall has
|
* has occurred, the RxStall is cleared and 1 is returned. If RxStall has
|
||||||
* not occured, 0 is returned.
|
* not occurred, 0 is returned.
|
||||||
*/
|
*/
|
||||||
static u8 check_stall(u8 ep, u8 dir_out)
|
static u8 check_stall(u8 ep, u8 dir_out)
|
||||||
{
|
{
|
||||||
|
|
|
@ -5,7 +5,7 @@
|
||||||
* minimal framebuffer driver for TI's AM335x SoC to be compatible with
|
* minimal framebuffer driver for TI's AM335x SoC to be compatible with
|
||||||
* Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c)
|
* Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c)
|
||||||
*
|
*
|
||||||
* - supporting only 24bit RGB/TFT raster Mode (not using palette)
|
* - supporting 16/24/32bit RGB/TFT raster Mode (not using palette)
|
||||||
* - sets up LCD controller as in 'am335x_lcdpanel' struct given
|
* - sets up LCD controller as in 'am335x_lcdpanel' struct given
|
||||||
* - starts output DMA from gd->fb_base buffer
|
* - starts output DMA from gd->fb_base buffer
|
||||||
*
|
*
|
||||||
|
@ -106,6 +106,8 @@ int lcd_get_size(int *line_length)
|
||||||
|
|
||||||
int am335xfb_init(struct am335x_lcdpanel *panel)
|
int am335xfb_init(struct am335x_lcdpanel *panel)
|
||||||
{
|
{
|
||||||
|
u32 raster_ctrl = 0;
|
||||||
|
|
||||||
if (0 == gd->fb_base) {
|
if (0 == gd->fb_base) {
|
||||||
printf("ERROR: no valid fb_base stored in GLOBAL_DATA_PTR!\n");
|
printf("ERROR: no valid fb_base stored in GLOBAL_DATA_PTR!\n");
|
||||||
return -1;
|
return -1;
|
||||||
|
@ -115,6 +117,21 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* We can already set the bits for the raster_ctrl in this check */
|
||||||
|
switch (panel->bpp) {
|
||||||
|
case 16:
|
||||||
|
break;
|
||||||
|
case 32:
|
||||||
|
raster_ctrl |= LCD_TFT_24BPP_UNPACK;
|
||||||
|
/* fallthrough */
|
||||||
|
case 24:
|
||||||
|
raster_ctrl |= LCD_TFT_24BPP_MODE;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
error("am335x-fb: invalid bpp value: %d\n", panel->bpp);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
debug("setting up LCD-Controller for %dx%dx%d (hfp=%d,hbp=%d,hsw=%d / ",
|
debug("setting up LCD-Controller for %dx%dx%d (hfp=%d,hbp=%d,hsw=%d / ",
|
||||||
panel->hactive, panel->vactive, panel->bpp,
|
panel->hactive, panel->vactive, panel->bpp,
|
||||||
panel->hfp, panel->hbp, panel->hsw);
|
panel->hfp, panel->hbp, panel->hsw);
|
||||||
|
@ -126,6 +143,8 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
|
||||||
/* palette default entry */
|
/* palette default entry */
|
||||||
memset((void *)gd->fb_base, 0, 0x20);
|
memset((void *)gd->fb_base, 0, 0x20);
|
||||||
*(unsigned int *)gd->fb_base = 0x4000;
|
*(unsigned int *)gd->fb_base = 0x4000;
|
||||||
|
/* point fb behind palette */
|
||||||
|
gd->fb_base += 0x20;
|
||||||
|
|
||||||
/* turn ON display through powercontrol function if accessible */
|
/* turn ON display through powercontrol function if accessible */
|
||||||
if (0 != panel->panel_power_ctrl)
|
if (0 != panel->panel_power_ctrl)
|
||||||
|
@ -137,9 +156,9 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
|
||||||
lcdhw->raster_ctrl = 0;
|
lcdhw->raster_ctrl = 0;
|
||||||
lcdhw->ctrl = LCD_CLK_DIVISOR(panel->pxl_clk_div) | LCD_RASTER_MODE;
|
lcdhw->ctrl = LCD_CLK_DIVISOR(panel->pxl_clk_div) | LCD_RASTER_MODE;
|
||||||
lcdhw->lcddma_fb0_base = gd->fb_base;
|
lcdhw->lcddma_fb0_base = gd->fb_base;
|
||||||
lcdhw->lcddma_fb0_ceiling = gd->fb_base + FBSIZE(panel) + 0x20;
|
lcdhw->lcddma_fb0_ceiling = gd->fb_base + FBSIZE(panel);
|
||||||
lcdhw->lcddma_fb1_base = gd->fb_base;
|
lcdhw->lcddma_fb1_base = gd->fb_base;
|
||||||
lcdhw->lcddma_fb1_ceiling = gd->fb_base + FBSIZE(panel) + 0x20;
|
lcdhw->lcddma_fb1_ceiling = gd->fb_base + FBSIZE(panel);
|
||||||
lcdhw->lcddma_ctrl = LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
|
lcdhw->lcddma_ctrl = LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
|
||||||
|
|
||||||
lcdhw->raster_timing0 = LCD_HORLSB(panel->hactive) |
|
lcdhw->raster_timing0 = LCD_HORLSB(panel->hactive) |
|
||||||
|
@ -157,14 +176,11 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
|
||||||
LCD_HBPMSB(panel->hbp) |
|
LCD_HBPMSB(panel->hbp) |
|
||||||
LCD_HFPMSB(panel->hfp) |
|
LCD_HFPMSB(panel->hfp) |
|
||||||
0x0000FF00; /* clk cycles for ac-bias */
|
0x0000FF00; /* clk cycles for ac-bias */
|
||||||
lcdhw->raster_ctrl = LCD_TFT_24BPP_MODE |
|
lcdhw->raster_ctrl = raster_ctrl |
|
||||||
LCD_TFT_24BPP_UNPACK |
|
|
||||||
LCD_PALMODE_RAWDATA |
|
LCD_PALMODE_RAWDATA |
|
||||||
LCD_TFT_MODE |
|
LCD_TFT_MODE |
|
||||||
LCD_RASTER_ENABLE;
|
LCD_RASTER_ENABLE;
|
||||||
|
|
||||||
gd->fb_base += 0x20; /* point fb behind palette */
|
|
||||||
|
|
||||||
debug("am335x-fb: waiting picture to be stable.\n.");
|
debug("am335x-fb: waiting picture to be stable.\n.");
|
||||||
mdelay(panel->pon_delay);
|
mdelay(panel->pon_delay);
|
||||||
|
|
||||||
|
|
|
@ -2040,7 +2040,7 @@ static char *ext4fs_read_symlink(struct ext2fs_node *node)
|
||||||
if (!symlink)
|
if (!symlink)
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
if (__le32_to_cpu(diro->inode.size) <= 60) {
|
if (__le32_to_cpu(diro->inode.size) < sizeof(diro->inode.b.symlink)) {
|
||||||
strncpy(symlink, diro->inode.b.symlink,
|
strncpy(symlink, diro->inode.b.symlink,
|
||||||
__le32_to_cpu(diro->inode.size));
|
__le32_to_cpu(diro->inode.size));
|
||||||
} else {
|
} else {
|
||||||
|
|
|
@ -83,7 +83,7 @@
|
||||||
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||||
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
||||||
#define CONFIG_PCI /* Enable PCI/PCIE */
|
#define CONFIG_PCI /* Enable PCI/PCIE */
|
||||||
#define CONFIG_PCIE1 /* PCIE controler 1 */
|
#define CONFIG_PCIE1 /* PCIE controller 1 */
|
||||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||||
|
|
||||||
|
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue