Introduce CONFIG_RTL8139 in Kconfig and move over boards' defconfig
to use that.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
[trini: Fixup MPC8641HPCN* and r2dplus configs]
Signed-off-by: Tom Rini <trini@konsulko.com>
Some boards' defconfig files are out of order. Clean this up.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch makes the following changes to the SR1500 board port:
- Update defconfig to support SPI NOR (use make savedefconfig).
- Increase SPI speed to a maximum of 100MHz for faster system
bootup.
- Change environment location, so that its not between SPL and
main U-Boot. This way the combined SPL / U-Boot image can
be used for updates.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Now that the drivers used by sandbox support CONFIG_BLK, we can switch
sandbox over to use driver model for block devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM,
installed on the congatec Qseven 2.0 evaluation carrier board
(conga-QEVAL).
Its port is very similar to the MinnowboardMAX port and also uses
the Intel FSP as described in doc/README.x86.
Currently supported are the following interfaces / devices:
- UART (via Winbond legacy SuperIO chip on carrier board)
- Ethernet (PCIe Intel I210 / E1000)
- SPI including SPI NOR as boot-device
- USB 2.0
- SATA via U-Boot SCSI IF
- eMMC
- Video (HDMI output @ 800x600)
- PCIe
Not supported yet is:
- I2C
- USB 3.0
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This adds basic support for chromebook_samus. This is the 2015 Pixel and
is based on an Intel broadwell platform.
Supported so far are:
- Serial
- SPI flash
- SDRAM init (with MRC cache)
- SATA
- Video (on the internal LCD panel)
- Keyboard
Various less-visible drivers are provided to make the above work (e.g. PCH,
power control and LPC).
The platform requires various binary blobs which are documented in the
README. The major missing feature is USB3 since the existing U-Boot support
does not work correctly with Intel XHCI controllers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Rather than setting up the pin configuration in the GPIO driver, use the
new pinctrl driver to do it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Now that we have all the bits and pieces ready for EFI payload loading
support, hook them up in Makefiles and KConfigs so that we can build.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
[trini: Enable only when we of OF_LIBFDT, disable on kwb and colibri_pxa270]
Signed-off-by: Tom Rini <trini@konsulko.com>
This adds support for the MUSB USB dual-role controller in peripheral mode,
with configuration options for the fastboot USB gadget.
At this point, flashing the internal eMMC is support.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
The Amazon Kindle Fire (first generation) codename kc1 is a tablet that was
released by Amazon back in 2011.
It is using an OMAP4430 SoC GP version, which allows running U-Boot and the
U-Boot SPL from the ground up.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This is based on the davinci da850evm. It can boot from either the
on-board 16MB flash or from a microSD card. It also reads board
information from an I2C EEPROM.
The EV3 itself initally boots from write-protected EEPROM, so no
u-boot SPL is needed.
Signed-off-by: David Lechner <david@lechnology.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Enable support for PMMC the TI power processor on K2G. This processor
manages all power management related activities on the SoC and and
allows the Operating Systems on compute processors such as ARM, DSP to
offload the power logic away into the power processor.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
There are already two FIT options in Kconfig but the CONFIG options are
still in the header files. We need to do a proper move to fix this.
Move these options to Kconfig and tidy up board configuration:
CONFIG_FIT
CONFIG_OF_BOARD_SETUP
CONFIG_OF_SYSTEM_SETUP
CONFIG_FIT_SIGNATURE
CONFIG_FIT_BEST_MATCH
CONFIG_FIT_VERBOSE
CONFIG_OF_STDOUT_VIA_ALIAS
CONFIG_RSA
Unfortunately the first one is a little complicated. We need to make sure
this option is not enabled in SPL by this change. Also this option is
enabled automatically in the host builds by defining CONFIG_FIT in the
image.h file. To solve this, add a new IMAGE_USE_FIT #define which can
be used in files that are built on the host but must also build for U-Boot
and SPL.
Note: Masahiro's moveconfig.py script is amazing.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add microblaze change, various configs/ re-applies]
Signed-off-by: Tom Rini <trini@konsulko.com>
Kconfig options must defined in the defconfig files. Since RSA_SOFTWARE_EXP
relies on CONFIG_DM, unless it is set in kconfig we cannot enable RSA.
Remove the hacks which enable CONFIG_DM in header files and update the
defconfig.
Signed-off-by: Simon Glass <sjg@chromium.org>
Various boards have the wrong Kconfig ordering now. To avoid a misleading
diff in the next patch, reorder the configuration correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
MIPS EL boards should define CONFIG_USE_PRIVATE_LIBGCC=y to work
with EB-only toolchains like the one from kernel.org. If one do
not globally set CONFIG_USE_PRIVATE_LIBGCC=y, the build fails with:
/opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_lshrdi3.o): compiled for a big endian system and target is little endian
/opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_lshrdi3.o): endianness incompatible with that of the selected emulation
/opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: failed to merge target specific data of file /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_lshrdi3.o)
/opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o): compiled for a big endian system and target is little endian
/opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o): endianness incompatible with that of the selected emulation
/opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: failed to merge target specific data of file /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o)
/work/git-trees/u-boot-mips/Makefile:1171: recipe for target 'u-boot' failed
One example for a failing build is Travis CI.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Purna Chandra Mandal <purna.mandal@microchip.com>
This introduces some minor cleanups, regarding aspects such as board name, code
and headers organization as well as deprecated and missing config options.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
The chains of "depends on <SoC_name>" in the current Kconfig is
clumsy. The idea here is to allow users to choose a SoC group first
(SoC group consists of some SoCs that can coexist in one binary).
Then, allow to enable/disable each SoC support in the selected SoC
group. This makes the Kconfig menu clearer.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
PH1-Pro5 support and ProXstream2/PH1-LD6b support can coexist in one
image and there is bit more room in SPL to accommodate all of them.
Merge uniphier_pro5_defconfig into uniphier_pxs2_defconfig.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Enable the driver in all UniPhier defconfig files and add some
needed defines to the common files.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Define prompt for cm-t43.
Cc: Tom Rini <trini@konsulko.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add full support for SPI flash chips to future-proof U-Boot for cm-t43.
Cc: Tom Rini <trini@konsulko.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move CONFIG_DM_SERIAL to cm_t43_defconfig. This forces us to update the
CONFIG_SYS_NS16550_REG_SIZE value for SPL.
Cc: Tom Rini <trini@konsulko.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
We drop everything possible things from board headerfiles and replace
this functionality with responsible settings in Kconfig (_defconfig).
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Tom Rini <trini@konsulko.com>
There is no need to have some specific prompt, so we drop this within
defconfigs.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Tom Rini <trini@konsulko.com>
As QSPI and IFC are pin-multiplexed on LS1021A, only IFC is supported
in SD boot now. For the customer's demand, QSPI needs to be supported
in SD boot too.
This patch adds QSPI or IFC support in SD boot according to the
corresponding defconfig. For detail, ls1021aqds_sdcard_ifc_defconfig
is used to support IFC in SD boot and ls1021aqds_sdcard_qspi_defconfig
is used to support QSPI in SD boot.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Convert ls1021aqds_nor_lpuart and ls1021aqds_ddr4_nor_lpuart
to driver model suport. Enable lpuart port driver.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Alison Wang <alison.wang@nxp.com>
CC: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
Add support for phy 1-3.
Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
[hdegoede@redhat.com: use setclrbits_le32 instead of read-modify-write]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
SY8106A is a PMIC which is used on the Allwinner
H3 Orange Pi Pc and Plus board. The VOUT1_SEL register is
implemented to set the default V-CPU voltage to 1200 mV.
This driver is required to ensure the SY8106A V-CPU
voltage is set to 1200 mV after a software reset. On cold
boot the default SY8106A output voltage is selected to be
1200 mV by a pair of resistors on the Orange Pi PC and Plus.
Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Split duart configuration as device tree file. Move /chosen node
out of board commone device tree. Convert ls1021aqds nor and SD
configurations to driver model support (qspi already uses DM).
Enable ns16550 DM serial driver for nor configurations.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Alison Wang <alison.wang@nxp.com>
CC: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
enable dma driver model for am437x_sk_evm as ti-edma3 supports
driver model
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
In current design, if any peripheral was assigned to both A7 and M4,
it will receive ipg_stop or ipg_wait when any of the 2 platforms
enter low power mode. We will have a risk that, if A7 enter wait,
M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait
asserted same time. Also if M4 enters stop mode, A7 will have no
chance to access the peripheral.
There are 26 peripherals affected by this IC issue:
SIM2(sim2/emvsim2)
SIM1(sim1/emvsim1)
UART1/UART2/UART3/UART4/UART5/UART6/UART7
SAI1/SAI2/SAI3
WDOG1/WDOG2/WDOG3/WDOG4
GPT1/GPT2/GPT3/GPT4
PWM1/PWM2/PWM3/PWM4
ENET1/ENET2
Software Workaround:
The solution is to set the peripherals to Domain0 by A core, since A core
in Domain0. The peripherals which will be used by M4, will be set to Domain1
by M4.
For example, A core set WDOG4 to domain0, but when M4 boots up, M4 will
set WDOG4 to domain1, because M4 will use WDOG4.
So the peripherals are not shared by them. This way requires
the uboot implemented the RDC driver and set the 26 IPs above
to domain 0 only. M4 image will set the M4 to domain 1 and
set peripheral which it will use to domain 1.
This patch enables the CONFIG_IMX_RDC and CONFIG_IMX_BOOTAUX for
i.MX7D SABRESD board, and setup the 26 IP resources to domain 0.
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This adds basic support to Intel Cougar Canyon 2 board, a board
based on Chief River platform with an Ivy Bridge processor and
a Panther Point chipset.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
ARC core could be configured with different L1 and L2 (AKA SLC) cache
line lengths. At least these values are possible and were really used:
32, 64 or 128 bytes.
Current implementation requires cache line to be selected upon U-Boot
configuration and then it will only work on matching hardware. Indeed
this is quite efficient because cache line length gets hardcoded during
code compilation. But OTOH it makes binary less portable.
With this commit we allow U-Boot to determine real L1 cache line length
early in runtime and use this value later on. This extends portability
of U-Boot binary a lot.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
The Versatile Industrial Communication platform is a community oriented
board from Landis + Gyr. It comes with:
- an RS-485 port
- 2 Ethernet ports
- a wireless M-BUS
- a 4G modem
- a 4MB SPI flash
- a 4GB eMMC
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
[rebase on current TOT]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Add support for DENX MA5D4 SoM and MA5D4EVK board, based on the
Atmel SAMA5D4 SoC. The SoM contains the SoC, eMMC, SPI NOR, SPI
CAN controllers and DRAM, the baseboard contains UART connectors,
ethernet port, microSD slot, LCD header, 2x CAN connector and a
lot of expansion headers.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Bin Meng