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Move gmlan_alt to TIM12 to fix concurrency issue with IR PWM (#627) 

* Moved gmlan_alt to TIM12

* forgot some stuff
master
robbederks 2021-02-01 15:53:04 +01:00 committed by GitHub
parent 97cd401abf
commit f2446c35d6
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 19 additions and 18 deletions
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3
board/boards/common.h
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@ -59,9 +59,10 @@ void peripherals_init(void){
RCC->APB1ENR |= RCC_APB1ENR_DACEN; RCC->APB1ENR |= RCC_APB1ENR_DACEN;
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // main counter RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // main counter
RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; // pedal and fan PWM RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; // pedal and fan PWM
RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; // gmlan_alt and IR PWM RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; // IR PWM
RCC->APB1ENR |= RCC_APB1ENR_TIM5EN; // k-line init RCC->APB1ENR |= RCC_APB1ENR_TIM5EN; // k-line init
RCC->APB1ENR |= RCC_APB1ENR_TIM6EN; // interrupt timer RCC->APB1ENR |= RCC_APB1ENR_TIM6EN; // interrupt timer
RCC->APB1ENR |= RCC_APB1ENR_TIM12EN; // gmlan_alt
RCC->APB1ENR |= RCC_APB1ENR_PWREN; // for RTC config RCC->APB1ENR |= RCC_APB1ENR_PWREN; // for RTC config
RCC->APB2ENR |= RCC_APB2ENR_USART1EN; RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN; RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;

34
board/drivers/gmlan_alt.h
View File

@ -122,23 +122,23 @@ int get_bit_message(char *out, CAN_FIFOMailBox_TypeDef *to_bang) {
return len; return len;
} }
void TIM4_IRQ_Handler(void); void TIM12_IRQ_Handler(void);
void setup_timer4(void) { void setup_timer(void) {
// register interrupt // register interrupt
REGISTER_INTERRUPT(TIM4_IRQn, TIM4_IRQ_Handler, 40000U, FAULT_INTERRUPT_RATE_GMLAN) REGISTER_INTERRUPT(TIM8_BRK_TIM12_IRQn, TIM12_IRQ_Handler, 40000U, FAULT_INTERRUPT_RATE_GMLAN)
// setup // setup
register_set(&(TIM4->PSC), (48-1), 0xFFFFU); // Tick on 1 us register_set(&(TIM12->PSC), (48-1), 0xFFFFU); // Tick on 1 us
register_set(&(TIM4->CR1), TIM_CR1_CEN, 0x3FU); // Enable register_set(&(TIM12->CR1), TIM_CR1_CEN, 0x3FU); // Enable
register_set(&(TIM4->ARR), (30-1), 0xFFFFU); // 33.3 kbps register_set(&(TIM12->ARR), (30-1), 0xFFFFU); // 33.3 kbps
// in case it's disabled // in case it's disabled
NVIC_EnableIRQ(TIM4_IRQn); NVIC_EnableIRQ(TIM8_BRK_TIM12_IRQn);
// run the interrupt // run the interrupt
register_set(&(TIM4->DIER), TIM_DIER_UIE, 0x5F5FU); // Update interrupt register_set(&(TIM12->DIER), TIM_DIER_UIE, 0x5F5FU); // Update interrupt
TIM4->SR = 0; TIM12->SR = 0;
} }
int gmlan_timeout_counter = GMLAN_TICKS_PER_TIMEOUT_TICKLE; //GMLAN transceiver times out every 17ms held high; tickle every 15ms int gmlan_timeout_counter = GMLAN_TICKS_PER_TIMEOUT_TICKLE; //GMLAN transceiver times out every 17ms held high; tickle every 15ms
@ -154,7 +154,7 @@ void gmlan_switch_init(int timeout_enable) {
gmlan_switch_below_timeout = 1; gmlan_switch_below_timeout = 1;
set_gpio_mode(GPIOB, 13, MODE_OUTPUT); set_gpio_mode(GPIOB, 13, MODE_OUTPUT);
setup_timer4(); setup_timer();
inverted_bit_to_send = GMLAN_LOW; //We got initialized, set the output low inverted_bit_to_send = GMLAN_LOW; //We got initialized, set the output low
} }
@ -192,9 +192,9 @@ int gmlan_fail_count = 0;
#define REQUIRED_SILENT_TIME 10 #define REQUIRED_SILENT_TIME 10
#define MAX_FAIL_COUNT 10 #define MAX_FAIL_COUNT 10
void TIM4_IRQ_Handler(void) { void TIM12_IRQ_Handler(void) {
if (gmlan_alt_mode == BITBANG) { if (gmlan_alt_mode == BITBANG) {
if ((TIM4->SR & TIM_SR_UIF) && (gmlan_sendmax != -1)) { if ((TIM12->SR & TIM_SR_UIF) && (gmlan_sendmax != -1)) {
int read = get_gpio_input(GPIOB, 12); int read = get_gpio_input(GPIOB, 12);
if (gmlan_silent_count < REQUIRED_SILENT_TIME) { if (gmlan_silent_count < REQUIRED_SILENT_TIME) {
if (read == 0) { if (read == 0) {
@ -236,13 +236,13 @@ void TIM4_IRQ_Handler(void) {
if ((gmlan_sending == gmlan_sendmax) || (gmlan_fail_count == MAX_FAIL_COUNT)) { if ((gmlan_sending == gmlan_sendmax) || (gmlan_fail_count == MAX_FAIL_COUNT)) {
set_bitbanged_gmlan(1); // recessive set_bitbanged_gmlan(1); // recessive
set_gpio_mode(GPIOB, 13, MODE_INPUT); set_gpio_mode(GPIOB, 13, MODE_INPUT);
register_clear_bits(&(TIM4->DIER), TIM_DIER_UIE); // No update interrupt register_clear_bits(&(TIM12->DIER), TIM_DIER_UIE); // No update interrupt
register_set(&(TIM4->CR1), 0U, 0x3FU); // Disable timer register_set(&(TIM12->CR1), 0U, 0x3FU); // Disable timer
gmlan_sendmax = -1; // exit gmlan_sendmax = -1; // exit
} }
} }
} else if (gmlan_alt_mode == GPIO_SWITCH) { } else if (gmlan_alt_mode == GPIO_SWITCH) {
if ((TIM4->SR & TIM_SR_UIF) && (gmlan_switch_below_timeout != -1)) { if ((TIM12->SR & TIM_SR_UIF) && (gmlan_switch_below_timeout != -1)) {
if ((can_timeout_counter == 0) && gmlan_switch_timeout_enable) { if ((can_timeout_counter == 0) && gmlan_switch_timeout_enable) {
//it has been more than 1 second since timeout was reset; disable timer and restore the GMLAN output //it has been more than 1 second since timeout was reset; disable timer and restore the GMLAN output
set_gpio_output(GPIOB, 13, GMLAN_LOW); set_gpio_output(GPIOB, 13, GMLAN_LOW);
@ -266,7 +266,7 @@ void TIM4_IRQ_Handler(void) {
} else { } else {
// Invalid GMLAN mode. Do not put a print statement here, way too fast to keep up with // Invalid GMLAN mode. Do not put a print statement here, way too fast to keep up with
} }
TIM4->SR = 0; TIM12->SR = 0;
} }
bool bitbang_gmlan(CAN_FIFOMailBox_TypeDef *to_bang) { bool bitbang_gmlan(CAN_FIFOMailBox_TypeDef *to_bang) {
@ -284,7 +284,7 @@ bool bitbang_gmlan(CAN_FIFOMailBox_TypeDef *to_bang) {
set_gpio_mode(GPIOB, 13, MODE_OUTPUT); set_gpio_mode(GPIOB, 13, MODE_OUTPUT);
// 33kbps // 33kbps
setup_timer4(); setup_timer();
} }
return gmlan_send_ok; return gmlan_send_ok;
} }