Move gmlan_alt to TIM12 to fix concurrency issue with IR PWM (#627)
* Moved gmlan_alt to TIM12 * forgot some stuffmaster
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97cd401abf
commit
f2446c35d6
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@ -59,9 +59,10 @@ void peripherals_init(void){
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RCC->APB1ENR |= RCC_APB1ENR_DACEN;
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RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // main counter
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; // pedal and fan PWM
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RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; // gmlan_alt and IR PWM
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RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; // IR PWM
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RCC->APB1ENR |= RCC_APB1ENR_TIM5EN; // k-line init
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RCC->APB1ENR |= RCC_APB1ENR_TIM6EN; // interrupt timer
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RCC->APB1ENR |= RCC_APB1ENR_TIM12EN; // gmlan_alt
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RCC->APB1ENR |= RCC_APB1ENR_PWREN; // for RTC config
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RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
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RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
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@ -122,23 +122,23 @@ int get_bit_message(char *out, CAN_FIFOMailBox_TypeDef *to_bang) {
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return len;
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}
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void TIM4_IRQ_Handler(void);
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void TIM12_IRQ_Handler(void);
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void setup_timer4(void) {
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void setup_timer(void) {
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// register interrupt
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REGISTER_INTERRUPT(TIM4_IRQn, TIM4_IRQ_Handler, 40000U, FAULT_INTERRUPT_RATE_GMLAN)
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REGISTER_INTERRUPT(TIM8_BRK_TIM12_IRQn, TIM12_IRQ_Handler, 40000U, FAULT_INTERRUPT_RATE_GMLAN)
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// setup
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register_set(&(TIM4->PSC), (48-1), 0xFFFFU); // Tick on 1 us
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register_set(&(TIM4->CR1), TIM_CR1_CEN, 0x3FU); // Enable
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register_set(&(TIM4->ARR), (30-1), 0xFFFFU); // 33.3 kbps
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register_set(&(TIM12->PSC), (48-1), 0xFFFFU); // Tick on 1 us
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register_set(&(TIM12->CR1), TIM_CR1_CEN, 0x3FU); // Enable
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register_set(&(TIM12->ARR), (30-1), 0xFFFFU); // 33.3 kbps
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// in case it's disabled
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NVIC_EnableIRQ(TIM4_IRQn);
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NVIC_EnableIRQ(TIM8_BRK_TIM12_IRQn);
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// run the interrupt
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register_set(&(TIM4->DIER), TIM_DIER_UIE, 0x5F5FU); // Update interrupt
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TIM4->SR = 0;
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register_set(&(TIM12->DIER), TIM_DIER_UIE, 0x5F5FU); // Update interrupt
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TIM12->SR = 0;
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}
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int gmlan_timeout_counter = GMLAN_TICKS_PER_TIMEOUT_TICKLE; //GMLAN transceiver times out every 17ms held high; tickle every 15ms
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@ -154,7 +154,7 @@ void gmlan_switch_init(int timeout_enable) {
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gmlan_switch_below_timeout = 1;
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set_gpio_mode(GPIOB, 13, MODE_OUTPUT);
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setup_timer4();
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setup_timer();
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inverted_bit_to_send = GMLAN_LOW; //We got initialized, set the output low
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}
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@ -192,9 +192,9 @@ int gmlan_fail_count = 0;
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#define REQUIRED_SILENT_TIME 10
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#define MAX_FAIL_COUNT 10
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void TIM4_IRQ_Handler(void) {
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void TIM12_IRQ_Handler(void) {
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if (gmlan_alt_mode == BITBANG) {
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if ((TIM4->SR & TIM_SR_UIF) && (gmlan_sendmax != -1)) {
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if ((TIM12->SR & TIM_SR_UIF) && (gmlan_sendmax != -1)) {
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int read = get_gpio_input(GPIOB, 12);
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if (gmlan_silent_count < REQUIRED_SILENT_TIME) {
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if (read == 0) {
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@ -236,13 +236,13 @@ void TIM4_IRQ_Handler(void) {
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if ((gmlan_sending == gmlan_sendmax) || (gmlan_fail_count == MAX_FAIL_COUNT)) {
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set_bitbanged_gmlan(1); // recessive
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set_gpio_mode(GPIOB, 13, MODE_INPUT);
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register_clear_bits(&(TIM4->DIER), TIM_DIER_UIE); // No update interrupt
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register_set(&(TIM4->CR1), 0U, 0x3FU); // Disable timer
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register_clear_bits(&(TIM12->DIER), TIM_DIER_UIE); // No update interrupt
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register_set(&(TIM12->CR1), 0U, 0x3FU); // Disable timer
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gmlan_sendmax = -1; // exit
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}
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}
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} else if (gmlan_alt_mode == GPIO_SWITCH) {
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if ((TIM4->SR & TIM_SR_UIF) && (gmlan_switch_below_timeout != -1)) {
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if ((TIM12->SR & TIM_SR_UIF) && (gmlan_switch_below_timeout != -1)) {
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if ((can_timeout_counter == 0) && gmlan_switch_timeout_enable) {
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//it has been more than 1 second since timeout was reset; disable timer and restore the GMLAN output
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set_gpio_output(GPIOB, 13, GMLAN_LOW);
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@ -266,7 +266,7 @@ void TIM4_IRQ_Handler(void) {
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} else {
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// Invalid GMLAN mode. Do not put a print statement here, way too fast to keep up with
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}
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TIM4->SR = 0;
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TIM12->SR = 0;
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}
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bool bitbang_gmlan(CAN_FIFOMailBox_TypeDef *to_bang) {
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@ -284,7 +284,7 @@ bool bitbang_gmlan(CAN_FIFOMailBox_TypeDef *to_bang) {
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set_gpio_mode(GPIOB, 13, MODE_OUTPUT);
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// 33kbps
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setup_timer4();
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setup_timer();
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}
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return gmlan_send_ok;
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}
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