Added support for Sample generator camera controller frame detector
gaurav
parent
2efe376768
commit
aa5b83fb73
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@ -43,7 +43,7 @@ begin
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if (state_time_counter == 0)
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begin
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camera_state <= camera_state + (camera_state != state_idle); //go to next state if state is not equal to state_active
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camera_state <= camera_state + (camera_state != state_idle); //go to next state if state is not equal to state_idle
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case(camera_state)
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state_reset:
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@ -17,7 +17,7 @@ Takes MIPI Clock and 4 Data lane as input convert into Parallel YUV output
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Ouputs 32bit YUV data with Frame sync, lsync and pixel clock
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*/
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module mipi_csi_16_nx( //reset_in,
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module mipi_csi_16_nx( reset_in,
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mipi_clk_p_in,
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mipi_clk_n_in,
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mipi_data_p_in,
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@ -32,15 +32,27 @@ module mipi_csi_16_nx( //reset_in,
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pclk_o, //data output on pos edge , should be latching into receiver on negedge
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data_o,
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fsync_o, //active high
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lsync_o //active high
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lsync_o, //active high
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//these pins may or many not be needed depeding on hardware config
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cam_ctrl_in, //control camera control input from host
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cam_pwr_en_o, //enable camera power
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cam_reset_o, //camera reset to camera
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cam_xmaster_o //camera master or slave
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);
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parameter MIPI_LANES = 2; //number of mipi lanes with camera. Only 2 or 4
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parameter MIPI_GEAR = 8; //deserializer gearing ratio. Only 8 or 16
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parameter MIPI_PIXEL_PER_CLOCK = 2; // number of pixels pipeline process in one clock cycle. With 2 Lanes and Gear 8 only 2 or 4, With 4 Lanes only 4 or 8
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parameter MIPI_PIXEL_PER_CLOCK = 2; // number of pixels pipeline process in one clock cycle. With 2 Lanes and Gear 8 only 2 or 4 with gear 16 only 4 , With 4 Lanes only 4 or 8
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parameter MAX_PIXEL_WIDTH = 12; //max pixel width , 14bit (RAW14) , IMX219 has 10bit while IMX477 has 12bit and IMX294 has 14bit
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//input reset_in;
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parameter FRAME_DETECT = 1; //if 1 MIPI start frame packet will be detected and used as frame sync rather than mipi_clk_lp , used for sensor whoes clock does not go into lp while frame sync is inactive
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//this should never be active unless testing
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parameter SAMPLE_GENERATOR = 0; //if 1 a ROM based sample generator will be activated for testing, Sample generator uses 2 ROM lines as that is what mipimum needed to an image with correct enough colors, ROM file are first.rom and second.rom
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input reset_in;
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input cam_ctrl_in;
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input mipi_clk_p_in;
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input mipi_clk_n_in;
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input [MIPI_LANES-1:0]mipi_data_p_in;
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@ -50,6 +62,10 @@ input mipi_clk_n_in1;
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input [MIPI_LANES-1:0]mipi_data_p_in1;
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input [MIPI_LANES-1:0]mipi_data_n_in1;
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output cam_pwr_en_o;
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output cam_reset_o;
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output cam_xmaster_o;
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output pclk_o;
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output [31:0]data_o;
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output fsync_o;
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@ -70,14 +86,15 @@ wire is_decoded_valid;
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wire is_raw_line_valid;
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wire is_unpacked_valid;
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wire is_rgb_valid;
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wire is_rgb_corrected_valid;
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wire is_yuv_valid;
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wire is_yuv_line_valid;
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wire mipi_out_clk;
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wire [31 :0]mipi_data_raw_hw;
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wire [31 :0]mipi_data_raw;
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//wire [((MIPI_LANES * MIPI_GEAR) - 1) :0]mipi_data_raw_hw;
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//wire [((MIPI_LANES * MIPI_GEAR) - 1) :0]mipi_data_raw;
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wire [((MIPI_LANES * MIPI_GEAR) - 1) :0]byte_aligned;
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wire [((MIPI_LANES * MIPI_GEAR) - 1) :0]lane_aligned;
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wire [((MIPI_LANES * MIPI_GEAR) - 1) :0]decoded_data;
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@ -85,35 +102,23 @@ wire [2:0]packet_type;
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wire [15:0]packet_length;
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wire [((MAX_PIXEL_WIDTH * MIPI_PIXEL_PER_CLOCK ) - 1 ):0]unpacked_data;
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wire [((MAX_PIXEL_WIDTH * MIPI_PIXEL_PER_CLOCK * 3) - 1 ):0]rgb_data;
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wire [((MAX_PIXEL_WIDTH * MIPI_PIXEL_PER_CLOCK * 3) - 1 ):0]rgb_corrected;
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wire [((MIPI_PIXEL_PER_CLOCK * 8 * 2 ) - 1 ):0]yuv_data;
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//wire frame_sync_in;
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wire line_reset;
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wire frame_sync;
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wire [1:0] sync_pulse;
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wire hf_clk;
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int_osc int_osc_ins1(.hf_out_en_i(1'b1),
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.hf_clk_out_o(mipi_out_clk),
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.lf_clk_out_o(osc_clk));
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wire ready;
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wire [15:0]debug_16;
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wire [7:0]debug_aligner;
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//&& (byte_aligned[23:16] == 8'hb8 ) && (byte_aligned[39:32] == 8'hb8 ) && (byte_aligned[55:48] == 8'hb8 )
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wire line_reset;
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wire [1:0] sync_pulse;
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//assign data_o = mipi_data_raw_hw;
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//assign mipi_out_clk = ; //yellow
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//assign lsync_o = !frame_sync; //green
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//assign fsync_o = mipi_out_clk & out_lsync ; //orange
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//assign data_o[1] = is_yuv_valid; //blue
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//assign data_o[3] = out_lsync;
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//assign data_o = {3'b111,1'b1, yuv_line_valid , is_yuv_valid, lsync_o & mipi_out_clk, is_yuv_valid & mipi_byte_clock , 3'b0, lane_aligned[7:0] == 8'hB8, is_lane_aligned_valid, is_decoded_valid & mipi_byte_clock, is_decoded_valid, mipi_byte_clock, 3'b0, debug_16[10:6], 2'b0, debug_16[5:0]};
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//wirere [15:0]debug_word;
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//assign debug_16 = {packet_length[15:2]};
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//Lattice FPGA Engineering sample chip does not allow manual PHY pin assignment* for PHY and our hardware uses PHY1 rather than PHY0, this instance with go to PHY0 while our actual instance will go to PHY 1
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//*Lattice Does allow manual pin assignment but when you assign manually PHY will not work at all. Appears to be ES chip bug.
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//As i am using Lattice ES chips i need to use Radiant 2.0 , DPHY IP has been changed a little with Radiant 3.1
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dphy_dummy mipi_csi_phy_inst0(.sync_clk_i(osc_clk),
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.sync_rst_i(1'b0),
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.lmmi_clk_i(1'b0),
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@ -126,9 +131,9 @@ dphy_dummy mipi_csi_phy_inst0(.sync_clk_i(osc_clk),
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.lmmi_rdata_o(),
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.lmmi_rdata_valid_o(),
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.hs_rx_en_i(1'b1),
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//.hs_rx_clk_en_i(1'b1), //new
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//.hs_rx_data_en_i(1'b1), //new
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//.hs_data_des_en_i(1'b1), //new
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//.hs_rx_clk_en_i(1'b1),
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//.hs_rx_data_en_i(1'b1),
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//.hs_data_des_en_i(1'b1),
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.hs_rx_data_o(dummy_out),
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//.hs_rx_data_sy nc_o(),
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.lp_rx_en_i(1'b1),
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@ -178,7 +183,7 @@ csi_dphy mipi_csi_phy_inst1(.sync_clk_i(osc_clk),
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.ready_o()) ;
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/*
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generate
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generate //if hardware mipi lane n does not match to FPGA PHY lane n then adjust here because Lattice ES chip does not allow manual pin assigment
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if ( (MIPI_GEAR == 16) && (MIPI_LANES == 4))
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begin
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assign mipi_data_raw = {mipi_data_raw_hw[15:0], mipi_data_raw_hw[31:16], mipi_data_raw_hw[63:48] ,mipi_data_raw_hw[47:32]}; //If schematic lane 0 may not connected PHY lane 0 , May need to swap here because its not possible to do before PHY IP, because Radiant auto assign PHY ports
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@ -200,32 +205,81 @@ endgenerate */
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assign mipi_data_raw = mipi_data_raw_hw;
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camera_controller camera_controller_ins0( .sclk_i(osc_clk),
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.reset_i(reset_in),
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.cam_ctrl_in(cam_ctrl_in),
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.cam_pwr_en_o(cam_pwr_en_o),
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.cam_reset_o(cam_reset_o),
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.cam_xmaster_o(cam_xmaster_o)
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);
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line_reset_generator line_reset_generator_ins1(.clk_i(mipi_byte_clock),
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line_reset_generator line_reset_generator_ins0(.clk_i(mipi_byte_clock),
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.lp_data_i(lp_rx_data_p[0]),
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.line_reset_o(line_reset));
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assign frame_sync = lp_rx_clk_p;
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genvar i;
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generate
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for (i = 0;i < MIPI_LANES; i = i +1) begin
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genvar i;
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if (SAMPLE_GENERATOR)
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begin
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wire dummy_byte_valid; //sample generator should neve be active unless debugging
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assign is_byte_valid = {dummy_byte_valid,dummy_byte_valid};
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sample_generator sample_generator_ins( .framesync_i(frame_sync),
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.clk_i(mipi_byte_clock),
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.reset_i(line_reset),
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.byte_o(byte_aligned),
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.byte_valid_o(dummy_byte_valid));
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mipi_csi_rx_byte_aligner #(.MIPI_GEAR(MIPI_GEAR))mipi_rx_byte_aligner_0( .clk_i(mipi_byte_clock),
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end
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else
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begin
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for (i = 0;i < MIPI_LANES; i = i +1)
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begin
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mipi_csi_rx_byte_aligner #(.MIPI_GEAR(MIPI_GEAR))mipi_rx_byte_aligner_0(.clk_i(mipi_byte_clock),
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.reset_i(line_reset),
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.byte_i(mipi_data_raw[(MIPI_GEAR * i) +: MIPI_GEAR]),
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.byte_o( byte_aligned[(MIPI_GEAR * i) +: MIPI_GEAR]),
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.byte_valid_o(is_byte_valid[i]));
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end
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end
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endgenerate
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generate
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if (FRAME_DETECT)
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begin
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frame_detector #(.MIPI_GEAR(MIPI_GEAR)) frame_detector_ins0( .reset_i(reset_in),
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.clk_i(mipi_byte_clock),
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.data_valid_i(is_byte_valid[0]),
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.data_lane0_i(byte_aligned[0 +: MIPI_GEAR]),
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.detected_frame_sync_o(frame_sync));
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end
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else
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begin
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assign frame_sync = lp_rx_clk_p;
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end
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endgenerate
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mipi_csi_rx_lane_aligner #(.MIPI_GEAR(MIPI_GEAR), .MIPI_LANES(MIPI_LANES))mipi_rx_lane_aligner( .clk_i(mipi_byte_clock),
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.reset_i(line_reset),
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.bytes_valid_i(is_byte_valid),
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.byte_i(byte_aligned),
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.lane_valid_o(is_lane_aligned_valid),
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.lane_byte_o(lane_aligned));
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generate
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if ( (MIPI_GEAR == 16) && (MIPI_LANES == 4))
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@ -236,8 +290,7 @@ generate
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.output_valid_o(is_decoded_valid),
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.data_o(decoded_data),
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.packet_length_o(),
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.packet_type_o(packet_type),
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.debug_o());
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.packet_type_o(packet_type));
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mipi_csi_rx_raw_depacker_16b4lane #(.PIXEL_WIDTH(MAX_PIXEL_WIDTH)) mipi_csi_rx_raw_depacker_0( .clk_i(mipi_byte_clock),
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.data_valid_i(is_decoded_valid),
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@ -256,8 +309,7 @@ generate
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.output_valid_o(is_decoded_valid),
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.data_o(decoded_data),
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.packet_length_o(),
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.packet_type_o(packet_type),
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.debug_o());
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.packet_type_o(packet_type));
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@ -278,8 +330,7 @@ generate
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.output_valid_o(is_decoded_valid),
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.data_o(decoded_data),
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.packet_length_o(),
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.packet_type_o(packet_type),
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.debug_o());
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.packet_type_o(packet_type));
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mipi_csi_rx_raw_depacker_8b4lane #(.PIXEL_WIDTH(MAX_PIXEL_WIDTH)) mipi_csi_rx_raw_depacker_0( .clk_i(mipi_byte_clock),
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.data_valid_i(is_decoded_valid),
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@ -300,8 +351,7 @@ generate
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.output_valid_o(is_decoded_valid),
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.data_o(decoded_data),
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.packet_length_o(),
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.packet_type_o(packet_type),
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.debug_o());
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.packet_type_o(packet_type));
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if (( MIPI_PIXEL_PER_CLOCK == 4) )
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@ -340,6 +390,25 @@ debayer_filter #(.PIXEL_WIDTH(MAX_PIXEL_WIDTH), .PIXEL_PER_CLK(MIPI_PIXEL_PER_CL
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.data_valid_i(is_unpacked_valid),
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.output_o(rgb_data),
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.output_valid_o(is_rgb_valid));
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/*
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color_correction_matrix #(.PIXEL_WIDTH(MAX_PIXEL_WIDTH), .PIXEL_PER_CLK(MIPI_PIXEL_PER_CLOCK))color_correction_matrix_0(
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.clk_i(mipi_byte_clock),
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.reset_i(frame_sync),
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.line_valid_i(is_raw_line_valid),
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.data_i(rgb_data),
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.data_valid_i(is_rgb_valid),
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.output_o(rgb_corrected),
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.output_valid_o(is_rgb_corrected_valid));
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rgb_to_yuv #(.PIXEL_WIDTH(MAX_PIXEL_WIDTH), .PIXEL_PER_CLK(MIPI_PIXEL_PER_CLOCK))rgb_to_yuv_0( .clk_i(mipi_byte_clock),
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.rgb_i(rgb_corrected),
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.rgb_valid_i(is_rgb_corrected_valid),
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.line_valid_i(is_raw_line_valid),
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.yuv_o(yuv_data),
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.yuv_valid_o(is_yuv_valid),
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.yuv_line_o(yuv_line_valid));
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*/
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rgb_to_yuv #(.PIXEL_WIDTH(MAX_PIXEL_WIDTH), .PIXEL_PER_CLK(MIPI_PIXEL_PER_CLOCK))rgb_to_yuv_0( .clk_i(mipi_byte_clock),
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.rgb_i(rgb_data),
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@ -348,7 +417,7 @@ rgb_to_yuv #(.PIXEL_WIDTH(MAX_PIXEL_WIDTH), .PIXEL_PER_CLK(MIPI_PIXEL_PER_CLOCK)
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.yuv_o(yuv_data),
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.yuv_valid_o(is_yuv_valid),
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.yuv_line_o(yuv_line_valid));
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//wire line_wire;
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output_reformatter #(.PIXEL_PER_CLK(MIPI_PIXEL_PER_CLOCK))out_reformatter_0( .clk_i(mipi_byte_clock),
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.line_sync_i(yuv_line_valid),
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@ -362,5 +431,5 @@ output_reformatter #(.PIXEL_PER_CLK(MIPI_PIXEL_PER_CLOCK))out_reformatter_0( .cl
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assign pclk_o = mipi_out_clk; //output clock always available
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assign fsync_o = !frame_sync; //activate fsync Active high
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//assign lsync_o = line_wire & mipi_out_clk;
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//assign lsync_o = is_yuv_valid;
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endmodule
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