609 lines
14 KiB
Plaintext
609 lines
14 KiB
Plaintext
{
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"board": {
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"design_settings": {
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"defaults": {
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"board_outline_line_width": 0.049999999999999996,
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"copper_line_width": 0.19999999999999998,
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"copper_text_italic": false,
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"copper_text_size_h": 1.5,
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"dimension_precision": 4,
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"dimension_units": 3,
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"dimensions": {
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"pads": {
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"height": 1.524,
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"width": 1.524
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},
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}
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},
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"meta": {
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"version": 2
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},
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"rule_severities": {
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"annular_width": "error",
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"clearance": "error",
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"courtyards_overlap": "error",
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"diff_pair_gap_out_of_range": "error",
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"diff_pair_uncoupled_length_too_long": "error",
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"drill_out_of_range": "error",
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"duplicate_footprints": "warning",
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"extra_footprint": "warning",
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"footprint_type_mismatch": "error",
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"hole_clearance": "error",
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"hole_near_hole": "error",
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"invalid_outline": "error",
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"item_on_disabled_layer": "error",
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"items_not_allowed": "error",
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"length_out_of_range": "error",
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"malformed_courtyard": "error",
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"microvia_drill_out_of_range": "error",
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"missing_courtyard": "ignore",
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"missing_footprint": "warning",
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"net_conflict": "warning",
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"npth_inside_courtyard": "ignore",
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"padstack": "error",
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"pth_inside_courtyard": "ignore",
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"shorting_items": "error",
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"silk_over_copper": "warning",
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"silk_overlap": "warning",
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"skew_out_of_range": "error",
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"through_hole_pad_without_hole": "error",
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"too_many_vias": "error",
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"track_dangling": "warning",
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"track_width": "error",
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"tracks_crossing": "error",
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"unconnected_items": "error",
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"via_dangling": "warning",
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"zone_has_empty_net": "error",
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"zones_intersect": "error"
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"track_widths": [],
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},
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"layer_presets": []
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"boards": [],
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"cvpcb": {
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"equivalence_files": []
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"erc": {
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"no_connect_connected": "warning",
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"MIPI0_D3_P"
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"name": "MIPI1",
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"MIPI1_CLK_N",
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"MIPI1_CLK_P",
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"MIPI1_D0_N",
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"MIPI1_D0_P",
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"MIPI1_D1_N",
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"MIPI1_D1_P",
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"MIPI1_D2_N",
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"MIPI1_D2_P",
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"MIPI1_D3_N",
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"MIPI1_D3_P"
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],
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},
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{
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"name": "pram0",
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"nets": [
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"PS0_CK_N",
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"PS0_CK_P",
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"PS0_DQ0",
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"PS0_DQ1",
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"PS0_DQ2",
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"PS0_DQ3",
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"PS0_DQ4",
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"PS0_DQ5",
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"PS0_DQ6",
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"PS0_DQ7",
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"PS0_RW"
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],
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"wire_width": 6.0
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},
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{
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"microvia_drill": 0.1,
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"name": "pram1",
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"nets": [
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"PS1_CK_N",
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"PS1_CK_P",
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"PS1_DQ0",
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"PS1_DQ1",
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"PS1_DQ2",
|
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"PS1_DQ3",
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"PS1_DQ4",
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"PS1_DQ5",
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"PS1_DQ6",
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"PS1_DQ7",
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"PS1_RW"
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],
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.25,
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"via_drill": 0.4,
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"wire_width": 6.0
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}
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],
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"meta": {
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"version": 2
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},
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"net_colors": null
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},
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"pcbnew": {
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"last_paths": {
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"gencad": "",
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