339 lines
9.1 KiB
Plaintext
339 lines
9.1 KiB
Plaintext
{
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"board": {
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"design_settings": {
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"defaults": {
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"board_outline_line_width": 0.049999999999999996,
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"copper_line_width": 0.19999999999999998,
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"copper_text_italic": false,
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"copper_text_size_h": 1.5,
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"copper_text_size_v": 1.5,
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"copper_text_thickness": 0.3,
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"copper_text_upright": false,
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"courtyard_line_width": 0.049999999999999996,
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"dimension_precision": 4,
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"dimension_units": 3,
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"dimensions": {
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"arrow_length": 1270000,
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"extension_offset": 500000,
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"keep_text_aligned": true,
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"suppress_zeroes": false,
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"text_position": 0,
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"units_format": 1
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},
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"fab_line_width": 0.09999999999999999,
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"fab_text_italic": false,
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"fab_text_size_h": 1.0,
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"fab_text_size_v": 1.0,
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"fab_text_thickness": 0.15,
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"fab_text_upright": false,
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"other_line_width": 0.09999999999999999,
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"other_text_italic": false,
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"other_text_size_h": 1.0,
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"other_text_size_v": 1.0,
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"other_text_thickness": 0.15,
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"other_text_upright": false,
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"pads": {
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"drill": 0.762,
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"height": 1.524,
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"width": 1.524
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},
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"silk_line_width": 0.12,
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"silk_text_italic": false,
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"silk_text_size_h": 1.0,
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"silk_text_size_v": 1.0,
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"silk_text_thickness": 0.15,
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"silk_text_upright": false,
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"zones": {
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"45_degree_only": false,
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"min_clearance": 0.508
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}
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},
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"diff_pair_dimensions": [],
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"drc_exclusions": [],
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"meta": {
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"version": 2
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},
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"rule_severities": {
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"annular_width": "error",
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"clearance": "error",
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"copper_edge_clearance": "error",
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"courtyards_overlap": "error",
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"diff_pair_gap_out_of_range": "error",
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"diff_pair_uncoupled_length_too_long": "error",
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"drill_out_of_range": "error",
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"duplicate_footprints": "warning",
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"extra_footprint": "warning",
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"footprint_type_mismatch": "error",
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"hole_clearance": "error",
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"hole_near_hole": "error",
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"invalid_outline": "error",
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"item_on_disabled_layer": "error",
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"items_not_allowed": "error",
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"length_out_of_range": "error",
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"malformed_courtyard": "error",
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"microvia_drill_out_of_range": "error",
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"missing_courtyard": "ignore",
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"missing_footprint": "warning",
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"net_conflict": "warning",
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"npth_inside_courtyard": "ignore",
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"padstack": "error",
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"pth_inside_courtyard": "ignore",
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"shorting_items": "error",
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"silk_over_copper": "warning",
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"silk_overlap": "warning",
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"skew_out_of_range": "error",
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"through_hole_pad_without_hole": "error",
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"too_many_vias": "error",
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"track_dangling": "warning",
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"track_width": "error",
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"tracks_crossing": "error",
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"unconnected_items": "error",
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"unresolved_variable": "error",
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"via_dangling": "warning",
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"zone_has_empty_net": "error",
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"zones_intersect": "error"
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},
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"rules": {
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"allow_blind_buried_vias": false,
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"allow_microvias": false,
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"max_error": 0.005,
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"min_clearance": 0.0,
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"min_copper_edge_clearance": 0.01,
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"min_hole_clearance": 0.25,
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"min_hole_to_hole": 0.25,
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"min_microvia_diameter": 0.19999999999999998,
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"min_microvia_drill": 0.09999999999999999,
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"min_silk_clearance": 0.0,
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"min_through_hole_diameter": 0.3,
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"min_track_width": 0.19999999999999998,
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"min_via_annular_width": 0.049999999999999996,
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"min_via_diameter": 0.39999999999999997,
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"use_height_for_length_calcs": true
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},
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"track_widths": [],
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"via_dimensions": [],
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"zones_allow_external_fillets": false,
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"zones_use_no_outline": true
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},
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"layer_presets": []
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},
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"boards": [],
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"cvpcb": {
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"equivalence_files": []
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},
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"libraries": {
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"pinned_footprint_libs": [],
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"pinned_symbol_libs": []
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},
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"meta": {
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"filename": "cam_FX3.kicad_pro",
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"version": 1
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},
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"net_settings": {
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"classes": [
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{
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"bus_width": 12.0,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "Default",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.25,
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"via_diameter": 0.8,
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"via_drill": 0.4,
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"wire_width": 6.0
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},
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{
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"bus_width": 12.0,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "All Nets",
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"nets": [],
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.25,
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"via_diameter": 0.8,
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"via_drill": 0.4,
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"wire_width": 6.0
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},
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{
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"bus_width": 12.0,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "GPIF",
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"nets": [
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"FPGA_CLK",
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"FPGA_CTL0",
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"FPGA_CTL1",
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"FPGA_D0",
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"FPGA_D1",
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"FPGA_D10",
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"FPGA_D11",
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"FPGA_D12",
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"FPGA_D13",
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"FPGA_D14",
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"FPGA_D15",
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"FPGA_D16",
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"FPGA_D17",
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"FPGA_D18",
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"FPGA_D19",
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"FPGA_D2",
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"FPGA_D20",
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"FPGA_D21",
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"FPGA_D22",
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"FPGA_D23",
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"FPGA_D24",
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"FPGA_D25",
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"FPGA_D26",
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"FPGA_D27",
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"FPGA_D28",
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"FPGA_D29",
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"FPGA_D3",
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"FPGA_D30",
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"FPGA_D31",
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"FPGA_D4",
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"FPGA_D5",
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"FPGA_D6",
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"FPGA_D7",
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"FPGA_D8",
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"FPGA_D9",
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"NetU13_H7",
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"NetU13_K7"
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],
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.25,
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"via_diameter": 0.8,
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"via_drill": 0.4,
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"wire_width": 6.0
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},
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{
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"bus_width": 12.0,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "USB2",
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"nets": [
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"SS_D_N",
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"SS_D_P"
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],
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.25,
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"via_diameter": 0.8,
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"via_drill": 0.4,
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"wire_width": 6.0
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},
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{
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"bus_width": 12.0,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "USB3FX",
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"nets": [
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"FX3_SSRX_N",
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"FX3_SSRX_P",
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"FX3_SSTX_N",
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"FX3_SSTX_P"
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],
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.25,
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"via_diameter": 0.8,
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"via_drill": 0.4,
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"wire_width": 6.0
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},
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{
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"bus_width": 12.0,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "USB3_1",
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"nets": [
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"SS_RX1_N",
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"SS_RX1_P",
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"SS_TX1_N",
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"SS_TX1_P"
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],
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.25,
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"via_diameter": 0.8,
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"via_drill": 0.4,
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"wire_width": 6.0
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},
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{
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"bus_width": 12.0,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "USB3_2",
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"nets": [
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"SS_RX2_N",
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"SS_RX2_P",
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"SS_TX2_N",
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"SS_TX2_P"
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],
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.25,
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"via_diameter": 0.8,
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"via_drill": 0.4,
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"wire_width": 6.0
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}
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],
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"meta": {
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"version": 2
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},
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"net_colors": null
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},
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"pcbnew": {
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"last_paths": {
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"gencad": "",
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"idf": "",
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"netlist": "",
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"specctra_dsn": "",
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"step": "",
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"vrml": ""
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},
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"page_layout_descr_file": ""
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},
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"schematic": {
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"legacy_lib_dir": "",
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"legacy_lib_list": []
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},
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"sheets": [],
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"text_variables": {}
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}
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