17 lines
421 B
Verilog
17 lines
421 B
Verilog
//MIPI Data line HS to LP transition can cause gragage data into bus,
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//This moduel holds reset a little longer before stable data comes throw
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module line_reset_generator(clk_i, lp_data_i, line_reset_o);
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input clk_i;
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input lp_data_i;
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output line_reset_o;
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reg [10:0]shift_reg;
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always @(posedge clk_i)
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begin
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shift_reg <= {shift_reg[9:0] , lp_data_i};
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end
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assign line_reset_o = shift_reg[10];
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endmodule |