93 lines
2.9 KiB
Verilog
93 lines
2.9 KiB
Verilog
`timescale 1ns/1ns
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/*
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MIPI CSI RX to Parallel Bridge (c) by Gaurav Singh www.CircuitValley.com
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MIPI CSI RX to Parallel Bridge is licensed under a
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Creative Commons Attribution 3.0 Unported License.
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You should have received a copy of the license along with this
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work. If not, see <http://creativecommons.org/licenses/by/3.0/>.
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*/
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/*
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Basically a packet Stripper, removes header and footer from packet
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Takes lane aligned data from lane aligner @ mipi byte clock
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looks for specific packet types, in this case RAW10bit 0x2B RAW12bit 0x2C and RAW14bit 0x2D , Packet type is also output to be used in next modules
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outputs Stripped bytes in exactly the way they were received.
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this module also fetch packet length and output_valid is active as long as input data is valid and packet length is still valid.
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V1.1 Sep 2020 Timing optimizations
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*/
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module mipi_csi_rx_packet_decoder_8b4lane(
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clk_i,
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data_valid_i,
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data_i,
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output_valid_o,
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data_o,
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packet_length_o,
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packet_type_o
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);
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localparam [7:0]MIPI_GEAR = 8;
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localparam [3:0]LANES = 3'h4;
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localparam [7:0]SYNC_BYTE = 8'hB8;
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localparam [7:0]MIPI_CSI_PACKET_10bRAW = 8'h2B;
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localparam [7:0]MIPI_CSI_PACKET_12bRAW = 8'h2C;
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localparam [7:0]MIPI_CSI_PACKET_14bRAW = 8'h2D;
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input clk_i;
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input data_valid_i;
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input [((MIPI_GEAR * LANES) - 1'h1):0]data_i;
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output reg [((MIPI_GEAR * LANES) - 1'h1):0]data_o;
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output reg output_valid_o;
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output reg [15:0]packet_length_o;
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output reg [2:0]packet_type_o;
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reg [15:0]packet_length_reg;
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reg [((MIPI_GEAR * LANES) - 1'h1):0]data_reg;
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//packet format <SYNC_BYTE> <DataID> <WCount 8bit> <WCount8bit> <ECC8bit>
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always @(posedge clk_i)
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begin
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if (data_valid_i)
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begin
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output_valid_o <= |packet_length_reg;
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if (packet_length_reg >= (LANES))
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begin
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packet_length_reg <= packet_length_reg - (LANES);
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end
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else if (data_o[7:0] == SYNC_BYTE && (data_reg[7:0] == MIPI_CSI_PACKET_10bRAW || data_reg[7:0] == MIPI_CSI_PACKET_12bRAW || data_reg[7:0] == MIPI_CSI_PACKET_14bRAW))
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begin
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packet_type_o <= data_reg[2:0];
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packet_length_o <= data_reg[23:8];
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packet_length_reg <= data_reg[23:8];
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end
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else
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begin
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packet_length_reg <= 16'h0;
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packet_type_o <= 3'h0;
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packet_length_o <= 16'h0;
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end
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end
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else
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begin
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packet_type_o <= 3'h0;
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packet_length_o <= 16'h0;
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packet_length_reg <= 16'h0;
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output_valid_o <= 1'h0;
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end
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end
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always @(posedge clk_i)
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begin
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data_reg <= data_i;
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data_o <= data_reg;
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end
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endmodule
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