75 lines
1.3 KiB
Verilog
75 lines
1.3 KiB
Verilog
module sample_generator(clk_i,
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reset_i,
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framesync_i,
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byte_o,
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byte_valid_o);
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input reset_i;
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input clk_i;
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input framesync_i;
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output [15:0]byte_o;
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output reg byte_valid_o;
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reg [11:0]sample_counter;
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wire [15:0]output_first;
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wire [15:0]output_second;
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rom_sec romsec_ins(.rd_clk_i(clk_i),
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.rst_i(reset_i),
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.rd_en_i(1'b1),
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.rd_clk_en_i(1'b1),
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.rd_addr_i(sample_counter),
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.rd_data_o(output_second)) ;
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debug_rom debug_rom_ins(.rd_clk_i(clk_i),
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.rst_i(reset_i),
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.rd_en_i(1'b1),
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.rd_clk_en_i(1'b1),
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.rd_addr_i(sample_counter),
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.rd_data_o(output_first)) ;
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reg [9:0]line_counter;
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assign byte_o = line_counter[0]?output_second:output_first;
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always @(posedge framesync_i or negedge reset_i)
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begin
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if (framesync_i)
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begin
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line_counter <= 0;
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end
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else
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begin
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line_counter <= line_counter + 1'h1;
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end
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end
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always @(negedge clk_i)
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begin
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if (reset_i)
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begin
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sample_counter <= 16'h0;
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end
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else
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begin
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sample_counter <= sample_counter + 1'h1;
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end
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end
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always @(*)
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begin
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if (reset_i)
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begin
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byte_valid_o = 1'b0;
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end
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else
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begin
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if ((line_counter > 10'h3) && (line_counter < 10'd994) && byte_o[7:0] == 8'hB8)
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begin
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byte_valid_o = 1'b1;
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end
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end
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end
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endmodule |