31 lines
426 B
Verilog
31 lines
426 B
Verilog
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`timescale 1ns/1ns
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module pll_tb;
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wire clk_o;
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wire clks_o;
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wire lock;
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wire reset_g;
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GSR
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GSR_INST (
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.GSR_N(1'b1),
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.CLK(1'b0)
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);
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wire hf_clk;
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int_osc int_osc_ins1(.hf_out_en_i(1'b1),
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.hf_clk_out_o(hf_clk),
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.lf_clk_out_o(osc_clk));
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out_pll inst1( .clki_i(hf_clk),
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.rstn_i(1'b1),
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.clkop_o(clk_o),
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.clkos_o(clks_o),
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.lock_o(lock));
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endmodule |