openpilot v0.8.8 release
parent
444aace15f
commit
baffaeee93
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@ -49,7 +49,6 @@ def phone_steps(String device_type, steps) {
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pipeline {
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agent none
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environment {
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COMMA_JWT = credentials('athena-test-jwt')
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TEST_DIR = "/data/openpilot"
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SOURCE_DIR = "/data/openpilot_source/"
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}
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12
README.md
12
README.md
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@ -67,8 +67,8 @@ Supported Cars
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| Acura | ILX 2016-19 | AcuraWatch Plus | openpilot | 25mph<sup>1</sup> | 25mph |
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| Acura | RDX 2016-18 | AcuraWatch Plus | openpilot | 25mph<sup>1</sup> | 12mph |
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| Acura | RDX 2019-21 | All | Stock | 0mph | 3mph |
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| Honda | Accord 2018-20 | All | Stock | 0mph | 3mph |
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| Honda | Accord Hybrid 2018-20 | All | Stock | 0mph | 3mph |
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| Honda | Accord 2018-21 | All | Stock | 0mph | 3mph |
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| Honda | Accord Hybrid 2018-21 | All | Stock | 0mph | 3mph |
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| Honda | Civic Hatchback 2017-21 | Honda Sensing | Stock | 0mph | 12mph |
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| Honda | Civic Coupe 2016-18 | Honda Sensing | openpilot | 0mph | 12mph |
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| Honda | Civic Coupe 2019-20 | All | Stock | 0mph | 2mph<sup>2</sup> |
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@ -110,7 +110,7 @@ Supported Cars
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| Toyota | C-HR 2017-20 | All | Stock | 0mph | 0mph |
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| Toyota | C-HR Hybrid 2017-19 | All | Stock | 0mph | 0mph |
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| Toyota | Corolla 2017-19 | All | Stock<sup>3</sup>| 20mph<sup>1</sup> | 0mph |
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| Toyota | Corolla 2020-21 | All | openpilot | 0mph | 0mph |
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| Toyota | Corolla 2020-22 | All | openpilot | 0mph | 0mph |
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| Toyota | Corolla Hatchback 2019-21 | All | openpilot | 0mph | 0mph |
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| Toyota | Corolla Hybrid 2020-21 | All | openpilot | 0mph | 0mph |
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| Toyota | Highlander 2017-19 | All | Stock<sup>3</sup>| 0mph | 0mph |
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@ -163,13 +163,16 @@ Community Maintained Cars and Features
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| Hyundai | Ioniq PHEV 2020 | SCC + LKAS | Stock | 0mph | 0mph |
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| Hyundai | Kona 2020 | SCC + LKAS | Stock | 0mph | 0mph |
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| Hyundai | Kona EV 2019 | SCC + LKAS | Stock | 0mph | 0mph |
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| Hyundai | Kona Hybrid 2020 | SCC + LKAS | Stock | 0mph | 0mph |
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| Hyundai | Santa Fe 2019-20 | All | Stock | 0mph | 0mph |
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| Hyundai | Sonata 2018-2019 | SCC + LKAS | Stock | 0mph | 0mph |
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| Hyundai | Sonata Hybrid 2021 | All | Stock | 0mph | 0mph |
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| Hyundai | Veloster 2019-20 | SCC + LKAS | Stock | 5mph | 0mph |
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| Jeep | Grand Cherokee 2016-18 | Adaptive Cruise | Stock | 0mph | 9mph |
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| Jeep | Grand Cherokee 2019-20 | Adaptive Cruise | Stock | 0mph | 39mph |
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| Kia | Forte 2018-2021 | SCC + LKAS | Stock | 0mph | 0mph |
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| Kia | Niro EV 2020 | SCC + LKAS | Stock | 0mph | 0mph |
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| Kia | Niro Hybrid 2021 | SCC + LKAS | Stock | 0mph | 0mph |
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| Kia | Niro PHEV 2019 | SCC + LKAS | Stock | 10mph | 32mph |
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| Kia | Optima 2017 | SCC + LKAS | Stock | 0mph | 32mph |
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| Kia | Optima 2019 | SCC + LKAS | Stock | 0mph | 0mph |
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@ -177,6 +180,7 @@ Community Maintained Cars and Features
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| Kia | Sorento 2018-19 | SCC + LKAS | Stock | 0mph | 0mph |
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| Kia | Stinger 2018 | SCC + LKAS | Stock | 0mph | 0mph |
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| Kia | Ceed 2019 | SCC + LKAS | Stock | 0mph | 0mph |
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| Kia | Telluride 2020 | SCC + LKAS | Stock | 0mph | 0mph |
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| Nissan | Altima 2019-20 | ProPILOT | Stock | 0mph | 0mph |
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| Nissan | Leaf 2018-20 | ProPILOT | Stock | 0mph | 0mph |
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| Nissan | Rogue 2018-20 | ProPILOT | Stock | 0mph | 0mph |
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@ -184,7 +188,7 @@ Community Maintained Cars and Features
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| SEAT | Ateca 2018 | Driver Assistance | Stock | 0mph | 0mph |
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| SEAT | Leon 2014-2020 | Driver Assistance | Stock | 0mph | 0mph |
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| Škoda | Kodiaq 2018 | Driver Assistance | Stock | 0mph | 0mph |
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| Škoda | Octavia 2015, 2019 | Driver Assistance | Stock | 0mph | 0mph |
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| Škoda | Octavia 2015, 2018-19 | Driver Assistance | Stock | 0mph | 0mph |
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| Škoda | Octavia RS 2016 | Driver Assistance | Stock | 0mph | 0mph |
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| Škoda | Scala 2020 | Driver Assistance | Stock | 0mph | 0mph |
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| Škoda | Superb 2015-18 | Driver Assistance | Stock | 0mph | 0mph |
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16
RELEASES.md
16
RELEASES.md
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@ -1,3 +1,19 @@
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Version 0.8.8 (2021-08-27)
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========================
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* New driving model with improved laneless performance
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* Trained on 5000+ hours of diverse driving data from 3000+ users in 40+ countries
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* Better anti-cheating methods during simulator training ensure the model hugs less when in laneless mode
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* All new desire ground-truthing stack makes the model better at lane changes
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* New driver monitoring model: improved performance on comma three
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* NEOS 18 for comma two: update packages
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* AGNOS 1.3 for comma three: fix display init at high temperatures
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* Improved auto-exposure on comma three
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* Honda Accord 2021 support thanks to csouers!
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* Honda Accord Hybrid 2021 support thanks to csouers!
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* Hyundai Kona Hybrid 2020 support thanks to haram-KONA!
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* Hyundai Sonata Hybrid 2021 support thanks to Matt-Wash-Burn!
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* Kia Niro Hybrid 2021 support thanks to tetious!
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Version 0.8.7 (2021-07-31)
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========================
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* comma three support!
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@ -15,7 +15,7 @@ used safely** and openpilot is provided with no warranty of fitness for any purp
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openpilot is developed in good faith to be compliant with FMVSS requirements and to follow
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industry standards of safety for Level 2 Driver Assistance Systems. In particular, we observe
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ISO26262 guidelines, including those from [pertinent documents](https://www.nhtsa.gov/sites/nhtsa.dot.gov/files/documents/13498a_812_573_alcsystemreport.pdf)
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released by NHTSA. In addition, we impose strict coding guidelines (like [MISRA C : 2012](https://www.misra.org.uk/MISRAHome/MISRAC2012/tabid/196/Default.aspx))
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released by NHTSA. In addition, we impose strict coding guidelines (like [MISRA C : 2012](https://www.misra.org.uk/what-is-misra/))
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on parts of openpilot that are safety relevant. We also perform software-in-the-loop,
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hardware-in-the-loop and in-vehicle tests before each software release.
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28
SConstruct
28
SConstruct
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@ -166,6 +166,10 @@ else:
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if arch != "Darwin":
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ldflags += ["-Wl,--as-needed"]
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# Enable swaglog include in submodules
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cflags += ["-DSWAGLOG"]
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cxxflags += ["-DSWAGLOG"]
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# change pythonpath to this
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lenv["PYTHONPATH"] = Dir("#").path
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@ -344,6 +348,17 @@ if GetOption("clazy"):
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Export('env', 'qt_env', 'arch', 'real_arch', 'SHARED', 'USE_WEBCAM')
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SConscript(['selfdrive/common/SConscript'])
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Import('_common', '_gpucommon', '_gpu_libs')
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if SHARED:
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common, gpucommon = abspath(common), abspath(gpucommon)
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else:
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common = [_common, 'json11']
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gpucommon = [_gpucommon] + _gpu_libs
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Export('common', 'gpucommon')
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# cereal and messaging are shared with the system
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SConscript(['cereal/SConscript'])
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if SHARED:
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@ -354,18 +369,7 @@ else:
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messaging = [File('#cereal/libmessaging.a')]
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visionipc = [File('#cereal/libvisionipc.a')]
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Export('cereal', 'messaging')
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SConscript(['selfdrive/common/SConscript'])
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Import('_common', '_gpucommon', '_gpu_libs')
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if SHARED:
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common, gpucommon = abspath(common), abspath(gpucommon)
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else:
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common = [_common, 'json11']
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gpucommon = [_gpucommon] + _gpu_libs
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Export('common', 'gpucommon', 'visionipc')
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Export('cereal', 'messaging', 'visionipc')
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# Build rednose library and ekf models
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@ -1,4 +1,4 @@
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Import('env', 'envCython', 'arch')
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Import('env', 'envCython', 'arch', 'common')
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import shutil
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@ -40,10 +40,10 @@ messaging_objects = env.SharedObject([
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messaging_lib = env.Library('messaging', messaging_objects)
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Depends('messaging/impl_zmq.cc', services_h)
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env.Program('messaging/bridge', ['messaging/bridge.cc'], LIBS=[messaging_lib, 'zmq'])
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env.Program('messaging/bridge', ['messaging/bridge.cc'], LIBS=[messaging_lib, 'zmq', common])
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Depends('messaging/bridge.cc', services_h)
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envCython.Program('messaging/messaging_pyx.so', 'messaging/messaging_pyx.pyx', LIBS=envCython["LIBS"]+[messaging_lib, "zmq"])
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envCython.Program('messaging/messaging_pyx.so', 'messaging/messaging_pyx.pyx', LIBS=envCython["LIBS"]+[messaging_lib, "zmq", common])
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# Build Vision IPC
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@ -63,7 +63,7 @@ vipc_objects = env.SharedObject(vipc_sources)
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vipc = env.Library('visionipc', vipc_objects)
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libs = envCython["LIBS"]+["OpenCL", "zmq", vipc, messaging_lib]
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libs = envCython["LIBS"]+["OpenCL", "zmq", vipc, messaging_lib, common]
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if arch == "aarch64":
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libs += ["adreno_utils"]
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if arch == "Darwin":
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@ -73,5 +73,5 @@ envCython.Program('visionipc/visionipc_pyx.so', 'visionipc/visionipc_pyx.pyx', L
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if GetOption('test'):
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env.Program('messaging/test_runner', ['messaging/test_runner.cc', 'messaging/msgq_tests.cc'], LIBS=[messaging_lib])
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env.Program('visionipc/test_runner', ['visionipc/test_runner.cc', 'visionipc/visionipc_tests.cc'], LIBS=[vipc, messaging_lib, 'zmq', 'pthread', 'OpenCL'])
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env.Program('messaging/test_runner', ['messaging/test_runner.cc', 'messaging/msgq_tests.cc'], LIBS=[messaging_lib, common])
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env.Program('visionipc/test_runner', ['visionipc/test_runner.cc', 'visionipc/visionipc_tests.cc'], LIBS=[vipc, messaging_lib, 'zmq', 'pthread', 'OpenCL', common])
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@ -108,6 +108,7 @@ struct CarEvent @0x9b1657f34caf3ad3 {
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driverCameraError @101;
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wideRoadCameraError @102;
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localizerMalfunction @103;
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highCpuUsage @105;
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driverMonitorLowAccDEPRECATED @68;
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radarCanErrorDEPRECATED @15;
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@ -156,6 +157,7 @@ struct CarState {
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# steering wheel
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steeringAngleDeg @7 :Float32;
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steeringAngleOffsetDeg @37 :Float32; # Offset betweens sensors in case there multiple
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steeringRateDeg @15 :Float32;
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steeringTorque @8 :Float32; # TODO: standardize units
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steeringTorqueEps @27 :Float32; # TODO: standardize units
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@ -302,6 +304,7 @@ struct CarControl {
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# range from -1.0 - 1.0
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steer @2: Float32;
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steeringAngleDeg @3: Float32;
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accel @4: Float32; # m/s^2
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}
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struct CruiseControl {
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@ -289,15 +289,11 @@ struct CanData {
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}
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struct DeviceState @0xa4d8b5af2aa492eb {
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freeSpacePercent @7 :Float32;
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memoryUsagePercent @19 :Int8;
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cpuUsagePercent @20 :Int8;
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gpuUsagePercent @33 :Int8;
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usbOnline @12 :Bool;
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networkType @22 :NetworkType;
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networkInfo @31 :NetworkInfo;
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offroadPowerUsageUwh @23 :UInt32;
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networkStrength @24 :NetworkStrength;
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offroadPowerUsageUwh @23 :UInt32;
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carBatteryCapacityUwh @25 :UInt32;
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fanSpeedPercentDesired @10 :UInt16;
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@ -306,6 +302,12 @@ struct DeviceState @0xa4d8b5af2aa492eb {
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lastAthenaPingTime @32 :UInt64;
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# system utilization
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freeSpacePercent @7 :Float32;
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memoryUsagePercent @19 :Int8;
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gpuUsagePercent @33 :Int8;
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cpuUsagePercent @34 :List(Int8); # per-core cpu usage
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# power
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batteryPercent @8 :Int16;
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batteryStatus @9 :Text;
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@ -365,6 +367,7 @@ struct DeviceState @0xa4d8b5af2aa492eb {
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gpuDEPRECATED @5 :UInt16;
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batDEPRECATED @6 :UInt32;
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pa0DEPRECATED @21 :UInt16;
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cpuUsagePercentDEPRECATED @20 :Int8;
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}
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struct PandaState @0xa7649e2575e4591e {
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@ -432,7 +435,7 @@ struct PandaState @0xa7649e2575e4591e {
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pedal @4;
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uno @5;
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dos @6;
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red @7;
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redPanda @7;
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}
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enum UsbPowerMode {
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@ -934,7 +937,7 @@ struct LiveLocationKalman {
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angularVelocityDevice @8 : Measurement;
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# orientationNEDCalibrated transforms to rot matrix: NED_from_calibrated
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orientationNEDCalibrated @9 : Measurement;
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calibratedOrientationNED @9 : Measurement;
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# Calibrated frame is simply device frame
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# aligned with the vehicle
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@ -0,0 +1,20 @@
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#pragma once
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#ifdef SWAGLOG
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#include "selfdrive/common/swaglog.h"
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#else
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#define CLOUDLOG_DEBUG 10
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#define CLOUDLOG_INFO 20
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#define CLOUDLOG_WARNING 30
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#define CLOUDLOG_ERROR 40
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#define CLOUDLOG_CRITICAL 50
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#define cloudlog(lvl, fmt, ...) printf(fmt "\n", ## __VA_ARGS__)
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#define LOGD(fmt, ...) cloudlog(CLOUDLOG_DEBUG, fmt, ## __VA_ARGS__)
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#define LOG(fmt, ...) cloudlog(CLOUDLOG_INFO, fmt, ## __VA_ARGS__)
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#define LOGW(fmt, ...) cloudlog(CLOUDLOG_WARNING, fmt, ## __VA_ARGS__)
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#define LOGE(fmt, ...) cloudlog(CLOUDLOG_ERROR, fmt, ## __VA_ARGS__)
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#endif
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@ -13,6 +13,7 @@ from cereal.services import service_list
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assert MultiplePublishersError
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assert MessagingError
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NO_TRAVERSAL_LIMIT = 2**64-1
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AVG_FREQ_HISTORY = 100
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SIMULATION = "SIMULATION" in os.environ
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@ -26,6 +27,9 @@ except ImportError:
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context = Context()
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def log_from_bytes(dat: bytes) -> capnp.lib.capnp._DynamicStructReader:
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return log.Event.from_bytes(dat, traversal_limit_in_words=NO_TRAVERSAL_LIMIT)
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def new_message(service: Optional[str] = None, size: Optional[int] = None) -> capnp.lib.capnp._DynamicStructBuilder:
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dat = log.Event.new_message()
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dat.logMonoTime = int(sec_since_boot() * 1e9)
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@ -83,7 +87,7 @@ def drain_sock(sock: SubSocket, wait_for_one: bool = False) -> List[capnp.lib.ca
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if dat is None: # Timeout hit
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break
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dat = log.Event.from_bytes(dat)
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dat = log_from_bytes(dat)
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ret.append(dat)
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return ret
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@ -106,20 +110,20 @@ def recv_sock(sock: SubSocket, wait: bool = False) -> Union[None, capnp.lib.capn
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dat = rcv
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if dat is not None:
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dat = log.Event.from_bytes(dat)
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dat = log_from_bytes(dat)
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return dat
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def recv_one(sock: SubSocket) -> Union[None, capnp.lib.capnp._DynamicStructReader]:
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dat = sock.receive()
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if dat is not None:
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dat = log.Event.from_bytes(dat)
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dat = log_from_bytes(dat)
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return dat
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def recv_one_or_none(sock: SubSocket) -> Union[None, capnp.lib.capnp._DynamicStructReader]:
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dat = sock.receive(non_blocking=True)
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if dat is not None:
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dat = log.Event.from_bytes(dat)
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dat = log_from_bytes(dat)
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return dat
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def recv_one_retry(sock: SubSocket) -> capnp.lib.capnp._DynamicStructReader:
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@ -127,7 +131,7 @@ def recv_one_retry(sock: SubSocket) -> capnp.lib.capnp._DynamicStructReader:
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while True:
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dat = sock.receive()
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if dat is not None:
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return log.Event.from_bytes(dat)
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return log_from_bytes(dat)
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class SubMaster():
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def __init__(self, services: List[str], poll: Optional[List[str]] = None,
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@ -69,7 +69,7 @@ public:
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SubMaster(const std::vector<const char *> &service_list,
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const char *address = nullptr, const std::vector<const char *> &ignore_alive = {});
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void update(int timeout = 1000);
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void update_msgs(uint64_t current_time, std::vector<std::pair<std::string, cereal::Event::Reader>> messages);
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void update_msgs(uint64_t current_time, const std::vector<std::pair<std::string, cereal::Event::Reader>> &messages);
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inline bool allAlive(const std::vector<const char *> &service_list = {}) { return all_(service_list, false, true); }
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inline bool allValid(const std::vector<const char *> &service_list = {}) { return all_(service_list, true, false); }
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inline bool allAliveAndValid(const std::vector<const char *> &service_list = {}) { return all_(service_list, true, true); }
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@ -92,7 +92,9 @@ void SubMaster::update(int timeout) {
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SubMessage *m = messages_.at(s);
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m->msg_reader->~FlatArrayMessageReader();
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m->msg_reader = new (m->allocated_msg_reader) capnp::FlatArrayMessageReader(m->aligned_buf.align(msg));
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capnp::ReaderOptions options;
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options.traversalLimitInWords = kj::maxValue; // Don't limit
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m->msg_reader = new (m->allocated_msg_reader) capnp::FlatArrayMessageReader(m->aligned_buf.align(msg), options);
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delete msg;
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messages.push_back({m->name, m->msg_reader->getRoot<cereal::Event>()});
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}
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@ -100,7 +102,7 @@ void SubMaster::update(int timeout) {
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update_msgs(current_time, messages);
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}
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|
||||
void SubMaster::update_msgs(uint64_t current_time, std::vector<std::pair<std::string, cereal::Event::Reader>> messages){
|
||||
void SubMaster::update_msgs(uint64_t current_time, const std::vector<std::pair<std::string, cereal::Event::Reader>> &messages){
|
||||
if (++frame == UINT64_MAX) frame = 1;
|
||||
|
||||
for(auto &kv : messages) {
|
||||
|
|
|
@ -61,6 +61,9 @@ services = {
|
|||
"modelV2": (True, 20., 40),
|
||||
"managerState": (True, 2., 1),
|
||||
"uploaderState": (True, 0., 1),
|
||||
|
||||
# debug
|
||||
"testJoystick": (False, 0.),
|
||||
}
|
||||
service_list = {name: Service(new_port(idx), *vals) for # type: ignore
|
||||
idx, (name, vals) in enumerate(services.items())}
|
||||
|
|
|
@ -55,8 +55,8 @@ class VisionBuf {
|
|||
void init_cl(cl_device_id device_id, cl_context ctx);
|
||||
void init_rgb(size_t width, size_t height, size_t stride);
|
||||
void init_yuv(size_t width, size_t height);
|
||||
void sync(int dir);
|
||||
void free();
|
||||
int sync(int dir);
|
||||
int free();
|
||||
};
|
||||
|
||||
void visionbuf_compute_aligned_width_and_height(int width, int height, int *aligned_w, int *aligned_h);
|
||||
|
|
|
@ -60,27 +60,36 @@ void VisionBuf::import(){
|
|||
}
|
||||
|
||||
|
||||
void VisionBuf::sync(int dir) {
|
||||
int VisionBuf::sync(int dir) {
|
||||
int err = 0;
|
||||
if (!this->buf_cl) return;
|
||||
if (!this->buf_cl) return 0;
|
||||
|
||||
if (dir == VISIONBUF_SYNC_FROM_DEVICE) {
|
||||
err = clEnqueueReadBuffer(this->copy_q, this->buf_cl, CL_FALSE, 0, this->len, this->addr, 0, NULL, NULL);
|
||||
} else {
|
||||
err = clEnqueueWriteBuffer(this->copy_q, this->buf_cl, CL_FALSE, 0, this->len, this->addr, 0, NULL, NULL);
|
||||
}
|
||||
assert(err == 0);
|
||||
clFinish(this->copy_q);
|
||||
}
|
||||
|
||||
void VisionBuf::free() {
|
||||
if (this->buf_cl){
|
||||
int err = clReleaseMemObject(this->buf_cl);
|
||||
assert(err == 0);
|
||||
|
||||
clReleaseCommandQueue(this->copy_q);
|
||||
if (err == 0){
|
||||
err = clFinish(this->copy_q);
|
||||
}
|
||||
|
||||
munmap(this->addr, this->len);
|
||||
close(this->fd);
|
||||
return err;
|
||||
}
|
||||
|
||||
int VisionBuf::free() {
|
||||
int err = 0;
|
||||
if (this->buf_cl){
|
||||
err = clReleaseMemObject(this->buf_cl);
|
||||
if (err != 0) return err;
|
||||
|
||||
err = clReleaseCommandQueue(this->copy_q);
|
||||
if (err != 0) return err;
|
||||
}
|
||||
|
||||
err = munmap(this->addr, this->len);
|
||||
if (err != 0) return err;
|
||||
|
||||
err = close(this->fd);
|
||||
return err;
|
||||
}
|
||||
|
|
|
@ -104,9 +104,7 @@ void VisionBuf::init_cl(cl_device_id device_id, cl_context ctx) {
|
|||
}
|
||||
|
||||
|
||||
void VisionBuf::sync(int dir) {
|
||||
int err;
|
||||
|
||||
int VisionBuf::sync(int dir) {
|
||||
struct ion_flush_data flush_data = {0};
|
||||
flush_data.handle = this->handle;
|
||||
flush_data.vaddr = this->addr;
|
||||
|
@ -124,19 +122,23 @@ void VisionBuf::sync(int dir) {
|
|||
ION_IOC_INV_CACHES : ION_IOC_CLEAN_CACHES;
|
||||
|
||||
custom_data.arg = (unsigned long)&flush_data;
|
||||
err = ioctl(ion_fd, ION_IOC_CUSTOM, &custom_data);
|
||||
assert(err == 0);
|
||||
return ioctl(ion_fd, ION_IOC_CUSTOM, &custom_data);
|
||||
}
|
||||
|
||||
void VisionBuf::free() {
|
||||
int VisionBuf::free() {
|
||||
int err = 0;
|
||||
|
||||
if (this->buf_cl){
|
||||
int err = clReleaseMemObject(this->buf_cl);
|
||||
assert(err == 0);
|
||||
err = clReleaseMemObject(this->buf_cl);
|
||||
if (err != 0) return err;
|
||||
}
|
||||
|
||||
munmap(this->addr, this->mmap_len);
|
||||
close(this->fd);
|
||||
err = munmap(this->addr, this->mmap_len);
|
||||
if (err != 0) return err;
|
||||
|
||||
err = close(this->fd);
|
||||
if (err != 0) return err;
|
||||
|
||||
struct ion_handle_data handle_data = {.handle = this->handle};
|
||||
ioctl(ion_fd, ION_IOC_FREE, &handle_data);
|
||||
return ioctl(ion_fd, ION_IOC_FREE, &handle_data);
|
||||
}
|
||||
|
|
|
@ -3,9 +3,10 @@
|
|||
#include <iostream>
|
||||
#include <thread>
|
||||
|
||||
#include "ipc.h"
|
||||
#include "visionipc_client.h"
|
||||
#include "visionipc_server.h"
|
||||
#include "visionipc/ipc.h"
|
||||
#include "visionipc/visionipc_client.h"
|
||||
#include "visionipc/visionipc_server.h"
|
||||
#include "logger/logger.h"
|
||||
|
||||
VisionIpcClient::VisionIpcClient(std::string name, VisionStreamType type, bool conflate, cl_device_id device_id, cl_context ctx) : name(name), type(type), device_id(device_id), ctx(ctx) {
|
||||
msg_ctx = Context::create();
|
||||
|
@ -21,8 +22,11 @@ bool VisionIpcClient::connect(bool blocking){
|
|||
|
||||
// Cleanup old buffers on reconnect
|
||||
for (size_t i = 0; i < num_buffers; i++){
|
||||
buffers[i].free();
|
||||
if (buffers[i].free() != 0) {
|
||||
LOGE("Failed to free buffer %zu", i);
|
||||
}
|
||||
}
|
||||
|
||||
num_buffers = 0;
|
||||
|
||||
// Connect to server socket and ask for all FDs of type
|
||||
|
@ -101,7 +105,10 @@ VisionBuf * VisionIpcClient::recv(VisionIpcBufExtra * extra, const int timeout_m
|
|||
*extra = packet->extra;
|
||||
}
|
||||
|
||||
buf->sync(VISIONBUF_SYNC_TO_DEVICE);
|
||||
if (buf->sync(VISIONBUF_SYNC_TO_DEVICE) != 0) {
|
||||
LOGE("Failed to sync buffer");
|
||||
}
|
||||
|
||||
delete r;
|
||||
return buf;
|
||||
}
|
||||
|
@ -110,7 +117,9 @@ VisionBuf * VisionIpcClient::recv(VisionIpcBufExtra * extra, const int timeout_m
|
|||
|
||||
VisionIpcClient::~VisionIpcClient(){
|
||||
for (size_t i = 0; i < num_buffers; i++){
|
||||
buffers[i].free();
|
||||
if (buffers[i].free() != 0) {
|
||||
LOGE("Failed to free buffer %zu", i);
|
||||
}
|
||||
}
|
||||
|
||||
delete sock;
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
#include "messaging/messaging.h"
|
||||
#include "visionipc/ipc.h"
|
||||
#include "visionipc/visionipc_server.h"
|
||||
#include "logger/logger.h"
|
||||
|
||||
std::string get_endpoint_name(std::string name, VisionStreamType type){
|
||||
if (messaging_use_zmq()){
|
||||
|
@ -145,7 +146,11 @@ VisionBuf * VisionIpcServer::get_buffer(VisionStreamType type){
|
|||
}
|
||||
|
||||
void VisionIpcServer::send(VisionBuf * buf, VisionIpcBufExtra * extra, bool sync){
|
||||
if (sync) buf->sync(VISIONBUF_SYNC_FROM_DEVICE);
|
||||
if (sync) {
|
||||
if (buf->sync(VISIONBUF_SYNC_FROM_DEVICE) != 0) {
|
||||
LOGE("Failed to sync buffer");
|
||||
}
|
||||
}
|
||||
assert(buffers.count(buf->type));
|
||||
assert(buf->idx < buffers[buf->type].size());
|
||||
|
||||
|
@ -165,7 +170,9 @@ VisionIpcServer::~VisionIpcServer(){
|
|||
// VisionBuf cleanup
|
||||
for( auto const& [type, buf] : buffers ) {
|
||||
for (VisionBuf* b : buf){
|
||||
b->free();
|
||||
if (b->free() != 0) {
|
||||
LOGE("Failed to free buffer");
|
||||
}
|
||||
delete b;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -1,9 +1,12 @@
|
|||
import jwt
|
||||
import os
|
||||
import requests
|
||||
from datetime import datetime, timedelta
|
||||
from common.basedir import PERSIST
|
||||
from selfdrive.version import version
|
||||
|
||||
API_HOST = os.getenv('API_HOST', 'https://api.commadotai.com')
|
||||
|
||||
class Api():
|
||||
def __init__(self, dongle_id):
|
||||
self.dongle_id = dongle_id
|
||||
|
@ -34,12 +37,10 @@ class Api():
|
|||
|
||||
|
||||
def api_get(endpoint, method='GET', timeout=None, access_token=None, **params):
|
||||
backend = "https://api.commadotai.com/"
|
||||
|
||||
headers = {}
|
||||
if access_token is not None:
|
||||
headers['Authorization'] = "JWT "+access_token
|
||||
|
||||
headers['User-Agent'] = "openpilot-" + version
|
||||
|
||||
return requests.request(method, backend+endpoint, timeout=timeout, headers=headers, params=params)
|
||||
return requests.request(method, API_HOST + "/" + endpoint, timeout=timeout, headers=headers, params=params)
|
||||
|
|
|
@ -79,6 +79,25 @@ class NamedTemporaryDir():
|
|||
self.close()
|
||||
|
||||
|
||||
class CallbackReader:
|
||||
"""Wraps a file, but overrides the read method to also
|
||||
call a callback function with the number of bytes read so far."""
|
||||
def __init__(self, f, callback, *args):
|
||||
self.f = f
|
||||
self.callback = callback
|
||||
self.cb_args = args
|
||||
self.total_read = 0
|
||||
|
||||
def __getattr__(self, attr):
|
||||
return getattr(self.f, attr)
|
||||
|
||||
def read(self, *args, **kwargs):
|
||||
chunk = self.f.read(*args, **kwargs)
|
||||
self.total_read += len(chunk)
|
||||
self.callback(*self.cb_args, self.total_read)
|
||||
return chunk
|
||||
|
||||
|
||||
def _get_fileobject_func(writer, temp_dir):
|
||||
def _get_fileobject():
|
||||
file_obj = writer.get_fileobject(dir=temp_dir)
|
||||
|
|
|
@ -1,9 +1,13 @@
|
|||
class FirstOrderFilter():
|
||||
class FirstOrderFilter:
|
||||
# first order filter
|
||||
def __init__(self, x0, ts, dt):
|
||||
self.k = (dt / ts) / (1. + dt / ts)
|
||||
def __init__(self, x0, rc, dt):
|
||||
self.x = x0
|
||||
self.dt = dt
|
||||
self.update_alpha(rc)
|
||||
|
||||
def update_alpha(self, rc):
|
||||
self.alpha = self.dt / (rc + self.dt)
|
||||
|
||||
def update(self, x):
|
||||
self.x = (1. - self.k) * self.x + self.k * x
|
||||
self.x = (1. - self.alpha) * self.x + self.alpha * x
|
||||
return self.x
|
||||
|
|
|
@ -17,7 +17,7 @@ cdef extern from "selfdrive/common/params.h":
|
|||
ALL
|
||||
|
||||
cdef cppclass Params:
|
||||
Params(bool) nogil
|
||||
Params() nogil
|
||||
Params(string) nogil
|
||||
string get(string, bool) nogil
|
||||
bool getBool(string) nogil
|
||||
|
|
|
@ -30,11 +30,11 @@ class UnknownKeyName(Exception):
|
|||
cdef class Params:
|
||||
cdef c_Params* p
|
||||
|
||||
def __cinit__(self, d=None, bool persistent_params=False):
|
||||
def __cinit__(self, d=None):
|
||||
cdef string path
|
||||
if d is None:
|
||||
with nogil:
|
||||
self.p = new c_Params(persistent_params)
|
||||
self.p = new c_Params()
|
||||
else:
|
||||
path = <string>d.encode()
|
||||
with nogil:
|
||||
|
|
|
@ -1,4 +0,0 @@
|
|||
#!/usr/bin/bash
|
||||
|
||||
cd /data/openpilot
|
||||
exec ./launch_openpilot.sh
|
|
@ -1,7 +1,7 @@
|
|||
{
|
||||
"ota_url": "https://commadist.azureedge.net/neosupdate/ota-signed-c4f56c62c5603c86e2ae9d83008a8d42a91319979661d0c42fb97b85d9112266.zip",
|
||||
"ota_hash": "c4f56c62c5603c86e2ae9d83008a8d42a91319979661d0c42fb97b85d9112266",
|
||||
"recovery_url": "https://commadist.azureedge.net/neosupdate/recovery-c5db3790c3b09756e8e896187ddb3f1258315eb0a86030468baa187b84a3bbf5.img",
|
||||
"recovery_len": 15209772,
|
||||
"recovery_hash": "c5db3790c3b09756e8e896187ddb3f1258315eb0a86030468baa187b84a3bbf5"
|
||||
"ota_url": "https://commadist.azureedge.net/neosupdate/ota-signed-5dc2575d713977666a8e14ae1b43a04d7f63123934c80fa10751d949a107653e.zip",
|
||||
"ota_hash": "5dc2575d713977666a8e14ae1b43a04d7f63123934c80fa10751d949a107653e",
|
||||
"recovery_url": "https://commadist.azureedge.net/neosupdate/recovery-f01a55c9ba52ca57668d1684c6bf4118efd31916b04f8c1fcd8495013d3677eb.img",
|
||||
"recovery_len": 15222060,
|
||||
"recovery_hash": "f01a55c9ba52ca57668d1684c6bf4118efd31916b04f8c1fcd8495013d3677eb"
|
||||
}
|
||||
|
|
|
@ -10,11 +10,21 @@ DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null && pwd )"
|
|||
|
||||
function two_init {
|
||||
|
||||
# Wifi scan
|
||||
wpa_cli IFNAME=wlan0 SCAN
|
||||
# set IO scheduler
|
||||
setprop sys.io.scheduler noop
|
||||
for f in /sys/block/*/queue/scheduler; do
|
||||
echo noop > $f
|
||||
done
|
||||
|
||||
# *** shield cores 2-3 ***
|
||||
|
||||
# TODO: should we enable this?
|
||||
# offline cores 2-3 to force recurring timers onto the other cores
|
||||
#echo 0 > /sys/devices/system/cpu/cpu2/online
|
||||
#echo 0 > /sys/devices/system/cpu/cpu3/online
|
||||
#echo 1 > /sys/devices/system/cpu/cpu2/online
|
||||
#echo 1 > /sys/devices/system/cpu/cpu3/online
|
||||
|
||||
# android gets two cores
|
||||
echo 0-1 > /dev/cpuset/background/cpus
|
||||
echo 0-1 > /dev/cpuset/system-background/cpus
|
||||
|
@ -75,6 +85,9 @@ function two_init {
|
|||
# disable bluetooth
|
||||
service call bluetooth_manager 8
|
||||
|
||||
# wifi scan
|
||||
wpa_cli IFNAME=wlan0 SCAN
|
||||
|
||||
# Check for NEOS update
|
||||
if [ $(< /VERSION) != "$REQUIRED_NEOS_VERSION" ]; then
|
||||
if [ -f "$DIR/scripts/continue.sh" ]; then
|
||||
|
|
|
@ -7,11 +7,11 @@ export OPENBLAS_NUM_THREADS=1
|
|||
export VECLIB_MAXIMUM_THREADS=1
|
||||
|
||||
if [ -z "$REQUIRED_NEOS_VERSION" ]; then
|
||||
export REQUIRED_NEOS_VERSION="17"
|
||||
export REQUIRED_NEOS_VERSION="18"
|
||||
fi
|
||||
|
||||
if [ -z "$AGNOS_VERSION" ]; then
|
||||
export AGNOS_VERSION="1.2"
|
||||
export AGNOS_VERSION="1.3"
|
||||
fi
|
||||
|
||||
if [ -z "$PASSIVE" ]; then
|
||||
|
|
Binary file not shown.
Binary file not shown.
|
@ -1 +0,0 @@
|
|||
v1.7.5
|
|
@ -1,3 +1,9 @@
|
|||
# flake8: noqa
|
||||
# pylint: skip-file
|
||||
from .python import Panda, PandaWifiStreaming, PandaDFU, flash_release, BASEDIR, ensure_st_up_to_date, PandaSerial
|
||||
from .python import Panda, PandaWifiStreaming, PandaDFU, flash_release, \
|
||||
BASEDIR, ensure_st_up_to_date, PandaSerial, \
|
||||
DEFAULT_FW_FN, DEFAULT_H7_FW_FN, MCU_TYPE_H7, MCU_TYPE_F4
|
||||
|
||||
from .python.config import BOOTSTUB_ADDRESS, BLOCK_SIZE_FX, APP_ADDRESS_FX, \
|
||||
BLOCK_SIZE_H7, APP_ADDRESS_H7, DEVICE_SERIAL_NUMBER_ADDR_H7, \
|
||||
DEVICE_SERIAL_NUMBER_ADDR_FX
|
||||
|
|
|
@ -8,6 +8,7 @@ if os.getenv("PEDAL"):
|
|||
PROJECT = "pedal"
|
||||
STARTUP_FILE = "stm32fx/startup_stm32f205xx.s"
|
||||
LINKER_SCRIPT = "stm32fx/stm32fx_flash.ld"
|
||||
APP_START_ADDRESS = "0x8004000"
|
||||
MAIN = "pedal/main.c"
|
||||
PROJECT_FLAGS = [
|
||||
"-mcpu=cortex-m3",
|
||||
|
@ -18,12 +19,32 @@ if os.getenv("PEDAL"):
|
|||
"-DPEDAL",
|
||||
]
|
||||
if os.getenv("PEDAL_USB"):
|
||||
PROJECT = "pedal_usb"
|
||||
PROJECT_FLAGS.append("-DPEDAL_USB")
|
||||
|
||||
elif os.getenv("PANDA_H7"):
|
||||
PROJECT = "panda_h7"
|
||||
STARTUP_FILE = "stm32h7/startup_stm32h7x5xx.s"
|
||||
LINKER_SCRIPT = "stm32h7/stm32h7x5_flash.ld"
|
||||
APP_START_ADDRESS = "0x8020000"
|
||||
MAIN = "main.c"
|
||||
PROJECT_FLAGS = [
|
||||
"-mcpu=cortex-m7",
|
||||
"-mhard-float",
|
||||
"-DSTM32H7",
|
||||
"-DSTM32H725xx",
|
||||
"-mfpu=fpv5-d16",
|
||||
"-fsingle-precision-constant",
|
||||
"-Os",
|
||||
"-g",
|
||||
"-DPANDA",
|
||||
]
|
||||
|
||||
else:
|
||||
PROJECT = "panda"
|
||||
STARTUP_FILE = "stm32fx/startup_stm32f413xx.s"
|
||||
LINKER_SCRIPT = "stm32fx/stm32fx_flash.ld"
|
||||
APP_START_ADDRESS = "0x8004000"
|
||||
MAIN = "main.c"
|
||||
PROJECT_FLAGS = [
|
||||
"-mcpu=cortex-m4",
|
||||
|
@ -39,13 +60,11 @@ else:
|
|||
|
||||
|
||||
def get_version(builder, build_type):
|
||||
version_file = File('../VERSION').srcnode().abspath
|
||||
version = open(version_file).read()
|
||||
try:
|
||||
git = subprocess.check_output(["git", "rev-parse", "--short=8", "HEAD"], encoding='utf8').strip()
|
||||
except subprocess.CalledProcessError:
|
||||
git = "unknown"
|
||||
return f"{version}-{builder}-{git}-{build_type}"
|
||||
return f"{builder}-{git}-{build_type}"
|
||||
|
||||
|
||||
def to_c_uint32(x):
|
||||
|
@ -110,6 +129,7 @@ else:
|
|||
|
||||
includes = [
|
||||
"stm32fx/inc",
|
||||
"stm32h7/inc",
|
||||
"..",
|
||||
".",
|
||||
]
|
||||
|
@ -150,7 +170,7 @@ bootstub_bin = panda_env.Objcopy(f"obj/bootstub.{PROJECT}.bin", bootstub_elf)
|
|||
|
||||
# Build main
|
||||
main_elf = panda_env.Program(f"obj/{PROJECT}.elf", [startup, MAIN],
|
||||
LINKFLAGS=["-Wl,--section-start,.isr_vector=0x8004000"] + flags)
|
||||
LINKFLAGS=[f"-Wl,--section-start,.isr_vector={APP_START_ADDRESS}"] + flags)
|
||||
main_bin = panda_env.Objcopy(f"obj/{PROJECT}.bin", main_elf)
|
||||
|
||||
# Sign main
|
||||
|
|
|
@ -127,41 +127,11 @@ void black_set_can_mode(uint8_t mode){
|
|||
}
|
||||
}
|
||||
|
||||
void black_usb_power_mode_tick(uint32_t uptime){
|
||||
UNUSED(uptime);
|
||||
// Not applicable
|
||||
}
|
||||
|
||||
bool black_check_ignition(void){
|
||||
// ignition is checked through harness
|
||||
return harness_check_ignition();
|
||||
}
|
||||
|
||||
uint32_t black_read_current(void){
|
||||
// No current sense on black panda
|
||||
return 0U;
|
||||
}
|
||||
|
||||
void black_set_ir_power(uint8_t percentage){
|
||||
UNUSED(percentage);
|
||||
}
|
||||
|
||||
void black_set_fan_power(uint8_t percentage){
|
||||
UNUSED(percentage);
|
||||
}
|
||||
|
||||
void black_set_phone_power(bool enabled){
|
||||
UNUSED(enabled);
|
||||
}
|
||||
|
||||
void black_set_clock_source_mode(uint8_t mode){
|
||||
UNUSED(mode);
|
||||
}
|
||||
|
||||
void black_set_siren(bool enabled){
|
||||
UNUSED(enabled);
|
||||
}
|
||||
|
||||
void black_init(void) {
|
||||
common_init_gpio();
|
||||
|
||||
|
@ -244,12 +214,12 @@ const board board_black = {
|
|||
.set_usb_power_mode = black_set_usb_power_mode,
|
||||
.set_gps_mode = black_set_gps_mode,
|
||||
.set_can_mode = black_set_can_mode,
|
||||
.usb_power_mode_tick = black_usb_power_mode_tick,
|
||||
.usb_power_mode_tick = unused_usb_power_mode_tick,
|
||||
.check_ignition = black_check_ignition,
|
||||
.read_current = black_read_current,
|
||||
.set_fan_power = black_set_fan_power,
|
||||
.set_ir_power = black_set_ir_power,
|
||||
.set_phone_power = black_set_phone_power,
|
||||
.set_clock_source_mode = black_set_clock_source_mode,
|
||||
.set_siren = black_set_siren
|
||||
.read_current = unused_read_current,
|
||||
.set_fan_power = unused_set_fan_power,
|
||||
.set_ir_power = unused_set_ir_power,
|
||||
.set_phone_power = unused_set_phone_power,
|
||||
.set_clock_source_mode = unused_set_clock_source_mode,
|
||||
.set_siren = unused_set_siren
|
||||
};
|
||||
|
|
|
@ -49,6 +49,7 @@ struct board {
|
|||
#define HW_TYPE_PEDAL 4U
|
||||
#define HW_TYPE_UNO 5U
|
||||
#define HW_TYPE_DOS 6U
|
||||
#define HW_TYPE_RED_PANDA 7U
|
||||
|
||||
// LED colors
|
||||
#define LED_RED 0U
|
||||
|
|
|
@ -49,18 +49,10 @@ void dos_set_led(uint8_t color, bool enabled) {
|
|||
}
|
||||
}
|
||||
|
||||
void dos_set_gps_load_switch(bool enabled) {
|
||||
UNUSED(enabled);
|
||||
}
|
||||
|
||||
void dos_set_bootkick(bool enabled){
|
||||
set_gpio_output(GPIOC, 4, !enabled);
|
||||
}
|
||||
|
||||
void dos_set_phone_power(bool enabled){
|
||||
UNUSED(enabled);
|
||||
}
|
||||
|
||||
void dos_set_usb_power_mode(uint8_t mode) {
|
||||
bool valid = false;
|
||||
switch (mode) {
|
||||
|
@ -81,10 +73,6 @@ void dos_set_usb_power_mode(uint8_t mode) {
|
|||
}
|
||||
}
|
||||
|
||||
void dos_set_gps_mode(uint8_t mode) {
|
||||
UNUSED(mode);
|
||||
}
|
||||
|
||||
void dos_set_can_mode(uint8_t mode){
|
||||
switch (mode) {
|
||||
case CAN_MODE_NORMAL:
|
||||
|
@ -113,10 +101,6 @@ void dos_set_can_mode(uint8_t mode){
|
|||
}
|
||||
}
|
||||
|
||||
void dos_usb_power_mode_tick(uint32_t uptime){
|
||||
UNUSED(uptime);
|
||||
}
|
||||
|
||||
bool dos_check_ignition(void){
|
||||
// ignition is checked through harness
|
||||
return harness_check_ignition();
|
||||
|
@ -136,11 +120,6 @@ void dos_set_fan_power(uint8_t percentage){
|
|||
fan_set_power(percentage);
|
||||
}
|
||||
|
||||
uint32_t dos_read_current(void){
|
||||
// No current sense on Dos
|
||||
return 0U;
|
||||
}
|
||||
|
||||
void dos_set_clock_source_mode(uint8_t mode){
|
||||
clock_source_init(mode);
|
||||
}
|
||||
|
@ -235,14 +214,14 @@ const board board_dos = {
|
|||
.enable_can_transceivers = dos_enable_can_transceivers,
|
||||
.set_led = dos_set_led,
|
||||
.set_usb_power_mode = dos_set_usb_power_mode,
|
||||
.set_gps_mode = dos_set_gps_mode,
|
||||
.set_gps_mode = unused_set_gps_mode,
|
||||
.set_can_mode = dos_set_can_mode,
|
||||
.usb_power_mode_tick = dos_usb_power_mode_tick,
|
||||
.usb_power_mode_tick = unused_usb_power_mode_tick,
|
||||
.check_ignition = dos_check_ignition,
|
||||
.read_current = dos_read_current,
|
||||
.read_current = unused_read_current,
|
||||
.set_fan_power = dos_set_fan_power,
|
||||
.set_ir_power = dos_set_ir_power,
|
||||
.set_phone_power = dos_set_phone_power,
|
||||
.set_phone_power = unused_set_phone_power,
|
||||
.set_clock_source_mode = dos_set_clock_source_mode,
|
||||
.set_siren = dos_set_siren
|
||||
};
|
||||
|
|
|
@ -48,12 +48,12 @@ const board board_grey = {
|
|||
.set_usb_power_mode = white_set_usb_power_mode,
|
||||
.set_gps_mode = grey_set_gps_mode,
|
||||
.set_can_mode = white_set_can_mode,
|
||||
.usb_power_mode_tick = white_usb_power_mode_tick,
|
||||
.usb_power_mode_tick = unused_usb_power_mode_tick,
|
||||
.check_ignition = white_check_ignition,
|
||||
.read_current = white_read_current,
|
||||
.set_fan_power = white_set_fan_power,
|
||||
.set_ir_power = white_set_ir_power,
|
||||
.set_phone_power = white_set_phone_power,
|
||||
.set_clock_source_mode = white_set_clock_source_mode,
|
||||
.set_siren = white_set_siren
|
||||
.set_fan_power = unused_set_fan_power,
|
||||
.set_ir_power = unused_set_ir_power,
|
||||
.set_phone_power = unused_set_phone_power,
|
||||
.set_clock_source_mode = unused_set_clock_source_mode,
|
||||
.set_siren = unused_set_siren
|
||||
};
|
||||
|
|
|
@ -50,41 +50,11 @@ void pedal_set_can_mode(uint8_t mode){
|
|||
}
|
||||
}
|
||||
|
||||
void pedal_usb_power_mode_tick(uint32_t uptime){
|
||||
UNUSED(uptime);
|
||||
// Not applicable
|
||||
}
|
||||
|
||||
bool pedal_check_ignition(void){
|
||||
// not supported on pedal
|
||||
return false;
|
||||
}
|
||||
|
||||
uint32_t pedal_read_current(void){
|
||||
// No current sense on pedal
|
||||
return 0U;
|
||||
}
|
||||
|
||||
void pedal_set_ir_power(uint8_t percentage){
|
||||
UNUSED(percentage);
|
||||
}
|
||||
|
||||
void pedal_set_fan_power(uint8_t percentage){
|
||||
UNUSED(percentage);
|
||||
}
|
||||
|
||||
void pedal_set_phone_power(bool enabled){
|
||||
UNUSED(enabled);
|
||||
}
|
||||
|
||||
void pedal_set_clock_source_mode(uint8_t mode){
|
||||
UNUSED(mode);
|
||||
}
|
||||
|
||||
void pedal_set_siren(bool enabled){
|
||||
UNUSED(enabled);
|
||||
}
|
||||
|
||||
void pedal_init(void) {
|
||||
common_init_gpio();
|
||||
|
||||
|
@ -121,12 +91,12 @@ const board board_pedal = {
|
|||
.set_usb_power_mode = pedal_set_usb_power_mode,
|
||||
.set_gps_mode = pedal_set_gps_mode,
|
||||
.set_can_mode = pedal_set_can_mode,
|
||||
.usb_power_mode_tick = pedal_usb_power_mode_tick,
|
||||
.usb_power_mode_tick = unused_usb_power_mode_tick,
|
||||
.check_ignition = pedal_check_ignition,
|
||||
.read_current = pedal_read_current,
|
||||
.set_fan_power = pedal_set_fan_power,
|
||||
.set_ir_power = pedal_set_ir_power,
|
||||
.set_phone_power = pedal_set_phone_power,
|
||||
.set_clock_source_mode = pedal_set_clock_source_mode,
|
||||
.set_siren = pedal_set_siren
|
||||
.read_current = unused_read_current,
|
||||
.set_fan_power = unused_set_fan_power,
|
||||
.set_ir_power = unused_set_ir_power,
|
||||
.set_phone_power = unused_set_phone_power,
|
||||
.set_clock_source_mode = unused_set_clock_source_mode,
|
||||
.set_siren = unused_set_siren
|
||||
};
|
||||
|
|
|
@ -0,0 +1,202 @@
|
|||
// ///////////////////// //
|
||||
// Red Panda + Harness //
|
||||
// ///////////////////// //
|
||||
|
||||
void red_enable_can_transceiver(uint8_t transceiver, bool enabled) {
|
||||
switch (transceiver) {
|
||||
case 1U:
|
||||
set_gpio_output(GPIOG, 11, !enabled);
|
||||
break;
|
||||
case 2U:
|
||||
set_gpio_output(GPIOB, 3, !enabled);
|
||||
break;
|
||||
case 3U:
|
||||
set_gpio_output(GPIOD, 7, !enabled);
|
||||
break;
|
||||
case 4U:
|
||||
set_gpio_output(GPIOB, 4, !enabled);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void red_enable_can_transceivers(bool enabled) {
|
||||
uint8_t main_bus = (car_harness_status == HARNESS_STATUS_FLIPPED) ? 3U : 1U;
|
||||
for (uint8_t i=1U; i<=4U; i++) {
|
||||
// Leave main CAN always on for CAN-based ignition detection
|
||||
if (i == main_bus) {
|
||||
red_enable_can_transceiver(i, true);
|
||||
} else {
|
||||
red_enable_can_transceiver(i, enabled);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void red_set_led(uint8_t color, bool enabled) {
|
||||
switch (color) {
|
||||
case LED_RED:
|
||||
set_gpio_output(GPIOE, 4, !enabled);
|
||||
break;
|
||||
case LED_GREEN:
|
||||
set_gpio_output(GPIOE, 3, !enabled);
|
||||
break;
|
||||
case LED_BLUE:
|
||||
set_gpio_output(GPIOE, 2, !enabled);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void red_set_usb_load_switch(bool enabled) {
|
||||
set_gpio_output(GPIOB, 14, !enabled);
|
||||
}
|
||||
|
||||
void red_set_usb_power_mode(uint8_t mode) {
|
||||
bool valid = false;
|
||||
switch (mode) {
|
||||
case USB_POWER_CLIENT:
|
||||
red_set_usb_load_switch(false);
|
||||
valid = true;
|
||||
break;
|
||||
case USB_POWER_CDP:
|
||||
red_set_usb_load_switch(true);
|
||||
valid = true;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
if (valid) {
|
||||
usb_power_mode = mode;
|
||||
}
|
||||
}
|
||||
|
||||
void red_set_can_mode(uint8_t mode) {
|
||||
switch (mode) {
|
||||
case CAN_MODE_NORMAL:
|
||||
case CAN_MODE_OBD_CAN2:
|
||||
if ((bool)(mode == CAN_MODE_NORMAL) != (bool)(car_harness_status == HARNESS_STATUS_FLIPPED)) {
|
||||
// B12,B13: disable normal mode
|
||||
set_gpio_pullup(GPIOB, 12, PULL_NONE);
|
||||
set_gpio_mode(GPIOB, 12, MODE_ANALOG);
|
||||
|
||||
set_gpio_pullup(GPIOB, 13, PULL_NONE);
|
||||
set_gpio_mode(GPIOB, 13, MODE_ANALOG);
|
||||
|
||||
// B5,B6: FDCAN2 mode
|
||||
set_gpio_pullup(GPIOB, 5, PULL_NONE);
|
||||
set_gpio_alternate(GPIOB, 5, GPIO_AF9_FDCAN2);
|
||||
|
||||
set_gpio_pullup(GPIOB, 6, PULL_NONE);
|
||||
set_gpio_alternate(GPIOB, 6, GPIO_AF9_FDCAN2);
|
||||
} else {
|
||||
// B5,B6: disable normal mode
|
||||
set_gpio_pullup(GPIOB, 5, PULL_NONE);
|
||||
set_gpio_mode(GPIOB, 5, MODE_ANALOG);
|
||||
|
||||
set_gpio_pullup(GPIOB, 6, PULL_NONE);
|
||||
set_gpio_mode(GPIOB, 6, MODE_ANALOG);
|
||||
// B12,B13: FDCAN2 mode
|
||||
set_gpio_pullup(GPIOB, 12, PULL_NONE);
|
||||
set_gpio_alternate(GPIOB, 12, GPIO_AF9_FDCAN2);
|
||||
|
||||
set_gpio_pullup(GPIOB, 13, PULL_NONE);
|
||||
set_gpio_alternate(GPIOB, 13, GPIO_AF9_FDCAN2);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
bool red_check_ignition(void) {
|
||||
// ignition is checked through harness
|
||||
return harness_check_ignition();
|
||||
}
|
||||
|
||||
void red_init(void) {
|
||||
common_init_gpio();
|
||||
|
||||
//C4,A1: OBD_SBU1, OBD_SBU2
|
||||
set_gpio_pullup(GPIOC, 4, PULL_NONE);
|
||||
set_gpio_mode(GPIOC, 4, MODE_ANALOG);
|
||||
|
||||
set_gpio_pullup(GPIOA, 1, PULL_NONE);
|
||||
set_gpio_mode(GPIOA, 1, MODE_ANALOG);
|
||||
|
||||
//C10,C11 : OBD_SBU1_RELAY, OBD_SBU2_RELAY
|
||||
set_gpio_output_type(GPIOC, 10, OUTPUT_TYPE_OPEN_DRAIN);
|
||||
set_gpio_pullup(GPIOC, 10, PULL_NONE);
|
||||
set_gpio_mode(GPIOC, 10, MODE_OUTPUT);
|
||||
set_gpio_output(GPIOC, 10, 1);
|
||||
|
||||
set_gpio_output_type(GPIOC, 11, OUTPUT_TYPE_OPEN_DRAIN);
|
||||
set_gpio_pullup(GPIOC, 11, PULL_NONE);
|
||||
set_gpio_mode(GPIOC, 11, MODE_OUTPUT);
|
||||
set_gpio_output(GPIOC, 11, 1);
|
||||
|
||||
// Turn on USB load switch.
|
||||
red_set_usb_load_switch(true);
|
||||
|
||||
// Set right power mode
|
||||
red_set_usb_power_mode(USB_POWER_CDP);
|
||||
|
||||
// Initialize harness
|
||||
harness_init();
|
||||
|
||||
// Enable CAN transceivers
|
||||
red_enable_can_transceivers(true);
|
||||
|
||||
// Disable LEDs
|
||||
red_set_led(LED_RED, false);
|
||||
red_set_led(LED_GREEN, false);
|
||||
red_set_led(LED_BLUE, false);
|
||||
|
||||
// Set normal CAN mode
|
||||
red_set_can_mode(CAN_MODE_NORMAL);
|
||||
|
||||
// flip CAN0 and CAN2 if we are flipped
|
||||
if (car_harness_status == HARNESS_STATUS_FLIPPED) {
|
||||
can_flip_buses(0, 2);
|
||||
}
|
||||
}
|
||||
|
||||
const harness_configuration red_harness_config = {
|
||||
.has_harness = true,
|
||||
.GPIO_SBU1 = GPIOC,
|
||||
.GPIO_SBU2 = GPIOA,
|
||||
.GPIO_relay_SBU1 = GPIOC,
|
||||
.GPIO_relay_SBU2 = GPIOC,
|
||||
.pin_SBU1 = 4,
|
||||
.pin_SBU2 = 1,
|
||||
.pin_relay_SBU1 = 10,
|
||||
.pin_relay_SBU2 = 11,
|
||||
.adc_channel_SBU1 = 4, //ADC12_INP4
|
||||
.adc_channel_SBU2 = 17 //ADC1_INP17
|
||||
};
|
||||
|
||||
const board board_red = {
|
||||
.board_type = "Red",
|
||||
.harness_config = &red_harness_config,
|
||||
.has_gps = false,
|
||||
.has_hw_gmlan = false,
|
||||
.has_obd = true,
|
||||
.has_lin = false,
|
||||
.has_rtc = false,
|
||||
.init = red_init,
|
||||
.enable_can_transceiver = red_enable_can_transceiver,
|
||||
.enable_can_transceivers = red_enable_can_transceivers,
|
||||
.set_led = red_set_led,
|
||||
.set_usb_power_mode = red_set_usb_power_mode,
|
||||
.set_gps_mode = unused_set_gps_mode,
|
||||
.set_can_mode = red_set_can_mode,
|
||||
.usb_power_mode_tick = unused_usb_power_mode_tick,
|
||||
.check_ignition = red_check_ignition,
|
||||
.read_current = unused_read_current,
|
||||
.set_fan_power = unused_set_fan_power,
|
||||
.set_ir_power = unused_set_ir_power,
|
||||
.set_phone_power = unused_set_phone_power,
|
||||
.set_clock_source_mode = unused_set_clock_source_mode,
|
||||
.set_siren = unused_set_siren
|
||||
};
|
|
@ -173,19 +173,6 @@ void uno_set_fan_power(uint8_t percentage){
|
|||
fan_set_power(percentage);
|
||||
}
|
||||
|
||||
uint32_t uno_read_current(void){
|
||||
// No current sense on Uno
|
||||
return 0U;
|
||||
}
|
||||
|
||||
void uno_set_clock_source_mode(uint8_t mode){
|
||||
UNUSED(mode);
|
||||
}
|
||||
|
||||
void uno_set_siren(bool enabled){
|
||||
UNUSED(enabled);
|
||||
}
|
||||
|
||||
void uno_init(void) {
|
||||
common_init_gpio();
|
||||
|
||||
|
@ -292,10 +279,10 @@ const board board_uno = {
|
|||
.set_can_mode = uno_set_can_mode,
|
||||
.usb_power_mode_tick = uno_usb_power_mode_tick,
|
||||
.check_ignition = uno_check_ignition,
|
||||
.read_current = uno_read_current,
|
||||
.read_current = unused_read_current,
|
||||
.set_fan_power = uno_set_fan_power,
|
||||
.set_ir_power = uno_set_ir_power,
|
||||
.set_phone_power = uno_set_phone_power,
|
||||
.set_clock_source_mode = uno_set_clock_source_mode,
|
||||
.set_siren = uno_set_siren
|
||||
.set_clock_source_mode = unused_set_clock_source_mode,
|
||||
.set_siren = unused_set_siren
|
||||
};
|
||||
|
|
|
@ -0,0 +1,31 @@
|
|||
void unused_set_gps_mode(uint8_t mode) {
|
||||
UNUSED(mode);
|
||||
}
|
||||
|
||||
void unused_usb_power_mode_tick(uint32_t uptime) {
|
||||
UNUSED(uptime);
|
||||
}
|
||||
|
||||
void unused_set_ir_power(uint8_t percentage) {
|
||||
UNUSED(percentage);
|
||||
}
|
||||
|
||||
void unused_set_fan_power(uint8_t percentage) {
|
||||
UNUSED(percentage);
|
||||
}
|
||||
|
||||
void unused_set_phone_power(bool enabled) {
|
||||
UNUSED(enabled);
|
||||
}
|
||||
|
||||
void unused_set_clock_source_mode(uint8_t mode) {
|
||||
UNUSED(mode);
|
||||
}
|
||||
|
||||
void unused_set_siren(bool enabled) {
|
||||
UNUSED(enabled);
|
||||
}
|
||||
|
||||
uint32_t unused_read_current(void) {
|
||||
return 0U;
|
||||
}
|
|
@ -151,35 +151,11 @@ uint32_t white_read_current(void){
|
|||
return adc_get(ADCCHAN_CURRENT);
|
||||
}
|
||||
|
||||
void white_usb_power_mode_tick(uint32_t uptime){
|
||||
UNUSED(uptime);
|
||||
}
|
||||
|
||||
void white_set_ir_power(uint8_t percentage){
|
||||
UNUSED(percentage);
|
||||
}
|
||||
|
||||
void white_set_fan_power(uint8_t percentage){
|
||||
UNUSED(percentage);
|
||||
}
|
||||
|
||||
bool white_check_ignition(void){
|
||||
// ignition is on PA1
|
||||
return !get_gpio_input(GPIOA, 1);
|
||||
}
|
||||
|
||||
void white_set_phone_power(bool enabled){
|
||||
UNUSED(enabled);
|
||||
}
|
||||
|
||||
void white_set_clock_source_mode(uint8_t mode){
|
||||
UNUSED(mode);
|
||||
}
|
||||
|
||||
void white_set_siren(bool enabled){
|
||||
UNUSED(enabled);
|
||||
}
|
||||
|
||||
void white_grey_common_init(void) {
|
||||
common_init_gpio();
|
||||
|
||||
|
@ -277,12 +253,12 @@ const board board_white = {
|
|||
.set_usb_power_mode = white_set_usb_power_mode,
|
||||
.set_gps_mode = white_set_gps_mode,
|
||||
.set_can_mode = white_set_can_mode,
|
||||
.usb_power_mode_tick = white_usb_power_mode_tick,
|
||||
.usb_power_mode_tick = unused_usb_power_mode_tick,
|
||||
.check_ignition = white_check_ignition,
|
||||
.read_current = white_read_current,
|
||||
.set_fan_power = white_set_fan_power,
|
||||
.set_ir_power = white_set_ir_power,
|
||||
.set_phone_power = white_set_phone_power,
|
||||
.set_clock_source_mode = white_set_clock_source_mode,
|
||||
.set_siren = white_set_siren
|
||||
.set_fan_power = unused_set_fan_power,
|
||||
.set_ir_power = unused_set_ir_power,
|
||||
.set_phone_power = unused_set_phone_power,
|
||||
.set_clock_source_mode = unused_set_clock_source_mode,
|
||||
.set_siren = unused_set_siren
|
||||
};
|
||||
|
|
|
@ -17,7 +17,7 @@
|
|||
|
||||
#include "obj/cert.h"
|
||||
#include "obj/gitversion.h"
|
||||
#include "spi_flasher.h"
|
||||
#include "flasher.h"
|
||||
|
||||
void __initialize_hardware_early(void) {
|
||||
early_initialization();
|
||||
|
|
|
@ -0,0 +1,7 @@
|
|||
#!/usr/bin/env sh
|
||||
set -e
|
||||
|
||||
scons -u
|
||||
PANDA_H7=1 scons -u
|
||||
PEDAL=1 scons -u
|
||||
PEDAL=1 PEDAL_USB=1 scons -u
|
|
@ -34,7 +34,21 @@
|
|||
|
||||
#define MAX_RESP_LEN 0x40U
|
||||
|
||||
#define GET_BUS(msg) (((msg)->RDTR >> 4) & 0xFF)
|
||||
#define GET_LEN(msg) ((msg)->RDTR & 0xF)
|
||||
#define GET_ADDR(msg) ((((msg)->RIR & 4) != 0) ? ((msg)->RIR >> 3) : ((msg)->RIR >> 21))
|
||||
#define GET_BYTE(msg, b) (((int)(b) > 3) ? (((msg)->RDHR >> (8U * ((unsigned int)(b) % 4U))) & 0xFFU) : (((msg)->RDLR >> (8U * (unsigned int)(b))) & 0xFFU))
|
||||
#define GET_BYTES_04(msg) ((msg)->RDLR)
|
||||
#define GET_BYTES_48(msg) ((msg)->RDHR)
|
||||
#define GET_FLAG(value, mask) (((__typeof__(mask))(value) & (mask)) == (mask))
|
||||
|
||||
#define CAN_INIT_TIMEOUT_MS 500U
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "stm32fx/stm32fx_config.h"
|
||||
#ifdef STM32H7
|
||||
#include "stm32h7/stm32h7_config.h"
|
||||
#else
|
||||
#include "stm32fx/stm32fx_config.h"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
@ -2,163 +2,7 @@
|
|||
// CAN2_TX, CAN2_RX0, CAN2_SCE
|
||||
// CAN3_TX, CAN3_RX0, CAN3_SCE
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t w_ptr;
|
||||
volatile uint32_t r_ptr;
|
||||
uint32_t fifo_size;
|
||||
CAN_FIFOMailBox_TypeDef *elems;
|
||||
} can_ring;
|
||||
|
||||
#define CAN_BUS_RET_FLAG 0x80U
|
||||
#define CAN_BUS_NUM_MASK 0x7FU
|
||||
|
||||
#define BUS_MAX 4U
|
||||
|
||||
uint32_t can_rx_errs = 0;
|
||||
uint32_t can_send_errs = 0;
|
||||
uint32_t can_fwd_errs = 0;
|
||||
uint32_t gmlan_send_errs = 0;
|
||||
|
||||
extern int can_live;
|
||||
extern int pending_can_live;
|
||||
|
||||
// must reinit after changing these
|
||||
extern int can_loopback;
|
||||
extern int can_silent;
|
||||
extern uint32_t can_speed[4];
|
||||
|
||||
void can_set_forwarding(int from, int to);
|
||||
|
||||
bool can_init(uint8_t can_number);
|
||||
void can_init_all(void);
|
||||
bool can_tx_check_min_slots_free(uint32_t min);
|
||||
void can_send(CAN_FIFOMailBox_TypeDef *to_push, uint8_t bus_number, bool skip_tx_hook);
|
||||
bool can_pop(can_ring *q, CAN_FIFOMailBox_TypeDef *elem);
|
||||
|
||||
// Ignition detected from CAN meessages
|
||||
bool ignition_can = false;
|
||||
bool ignition_cadillac = false;
|
||||
uint32_t ignition_can_cnt = 0U;
|
||||
|
||||
// end API
|
||||
|
||||
#define ALL_CAN_SILENT 0xFF
|
||||
#define ALL_CAN_LIVE 0
|
||||
|
||||
int can_live = 0;
|
||||
int pending_can_live = 0;
|
||||
int can_loopback = 0;
|
||||
int can_silent = ALL_CAN_SILENT;
|
||||
|
||||
// ********************* instantiate queues *********************
|
||||
#define can_buffer(x, size) \
|
||||
CAN_FIFOMailBox_TypeDef elems_##x[size]; \
|
||||
can_ring can_##x = { .w_ptr = 0, .r_ptr = 0, .fifo_size = (size), .elems = (CAN_FIFOMailBox_TypeDef *)&(elems_##x) };
|
||||
|
||||
can_buffer(rx_q, 0x1000)
|
||||
can_buffer(tx1_q, 0x100)
|
||||
can_buffer(tx2_q, 0x100)
|
||||
can_buffer(tx3_q, 0x100)
|
||||
can_buffer(txgmlan_q, 0x100)
|
||||
// FIXME:
|
||||
// cppcheck-suppress misra-c2012-9.3
|
||||
can_ring *can_queues[] = {&can_tx1_q, &can_tx2_q, &can_tx3_q, &can_txgmlan_q};
|
||||
|
||||
// global CAN stats
|
||||
int can_rx_cnt = 0;
|
||||
int can_tx_cnt = 0;
|
||||
int can_txd_cnt = 0;
|
||||
int can_err_cnt = 0;
|
||||
int can_overflow_cnt = 0;
|
||||
|
||||
// ********************* interrupt safe queue *********************
|
||||
bool can_pop(can_ring *q, CAN_FIFOMailBox_TypeDef *elem) {
|
||||
bool ret = 0;
|
||||
|
||||
ENTER_CRITICAL();
|
||||
if (q->w_ptr != q->r_ptr) {
|
||||
*elem = q->elems[q->r_ptr];
|
||||
if ((q->r_ptr + 1U) == q->fifo_size) {
|
||||
q->r_ptr = 0;
|
||||
} else {
|
||||
q->r_ptr += 1U;
|
||||
}
|
||||
ret = 1;
|
||||
}
|
||||
EXIT_CRITICAL();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool can_push(can_ring *q, CAN_FIFOMailBox_TypeDef *elem) {
|
||||
bool ret = false;
|
||||
uint32_t next_w_ptr;
|
||||
|
||||
ENTER_CRITICAL();
|
||||
if ((q->w_ptr + 1U) == q->fifo_size) {
|
||||
next_w_ptr = 0;
|
||||
} else {
|
||||
next_w_ptr = q->w_ptr + 1U;
|
||||
}
|
||||
if (next_w_ptr != q->r_ptr) {
|
||||
q->elems[q->w_ptr] = *elem;
|
||||
q->w_ptr = next_w_ptr;
|
||||
ret = true;
|
||||
}
|
||||
EXIT_CRITICAL();
|
||||
if (!ret) {
|
||||
can_overflow_cnt++;
|
||||
#ifdef DEBUG
|
||||
puts("can_push failed!\n");
|
||||
#endif
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
uint32_t can_slots_empty(can_ring *q) {
|
||||
uint32_t ret = 0;
|
||||
|
||||
ENTER_CRITICAL();
|
||||
if (q->w_ptr >= q->r_ptr) {
|
||||
ret = q->fifo_size - 1U - q->w_ptr + q->r_ptr;
|
||||
} else {
|
||||
ret = q->r_ptr - q->w_ptr - 1U;
|
||||
}
|
||||
EXIT_CRITICAL();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void can_clear(can_ring *q) {
|
||||
ENTER_CRITICAL();
|
||||
q->w_ptr = 0;
|
||||
q->r_ptr = 0;
|
||||
EXIT_CRITICAL();
|
||||
}
|
||||
|
||||
// assign CAN numbering
|
||||
// bus num: Can bus number on ODB connector. Sent to/from USB
|
||||
// Min: 0; Max: 127; Bit 7 marks message as receipt (bus 129 is receipt for but 1)
|
||||
// cans: Look up MCU can interface from bus number
|
||||
// can number: numeric lookup for MCU CAN interfaces (0 = CAN1, 1 = CAN2, etc);
|
||||
// bus_lookup: Translates from 'can number' to 'bus number'.
|
||||
// can_num_lookup: Translates from 'bus number' to 'can number'.
|
||||
// can_forwarding: Given a bus num, lookup bus num to forward to. -1 means no forward.
|
||||
|
||||
// Panda: Bus 0=CAN1 Bus 1=CAN2 Bus 2=CAN3
|
||||
CAN_TypeDef *cans[] = {CAN1, CAN2, CAN3};
|
||||
uint8_t bus_lookup[] = {0,1,2};
|
||||
uint8_t can_num_lookup[] = {0,1,2,-1};
|
||||
int8_t can_forwarding[] = {-1,-1,-1,-1};
|
||||
uint32_t can_speed[] = {5000, 5000, 5000, 333};
|
||||
#define CAN_MAX 3U
|
||||
|
||||
#define CANIF_FROM_CAN_NUM(num) (cans[num])
|
||||
#define CAN_NUM_FROM_CANIF(CAN) ((CAN)==CAN1 ? 0 : ((CAN) == CAN2 ? 1 : 2))
|
||||
#define BUS_NUM_FROM_CAN_NUM(num) (bus_lookup[num])
|
||||
#define CAN_NUM_FROM_BUS_NUM(num) (can_num_lookup[num])
|
||||
|
||||
void process_can(uint8_t can_number);
|
||||
|
||||
bool can_set_speed(uint8_t can_number) {
|
||||
bool ret = true;
|
||||
|
@ -169,22 +13,6 @@ bool can_set_speed(uint8_t can_number) {
|
|||
return ret;
|
||||
}
|
||||
|
||||
void can_init_all(void) {
|
||||
bool ret = true;
|
||||
for (uint8_t i=0U; i < CAN_MAX; i++) {
|
||||
can_clear(can_queues[i]);
|
||||
ret &= can_init(i);
|
||||
}
|
||||
UNUSED(ret);
|
||||
}
|
||||
|
||||
void can_flip_buses(uint8_t bus1, uint8_t bus2){
|
||||
bus_lookup[bus1] = bus2;
|
||||
bus_lookup[bus2] = bus1;
|
||||
can_num_lookup[bus1] = bus2;
|
||||
can_num_lookup[bus2] = bus1;
|
||||
}
|
||||
|
||||
// TODO: Cleanup with new abstraction
|
||||
void can_set_gmlan(uint8_t bus) {
|
||||
if(current_board->has_hw_gmlan){
|
||||
|
@ -323,34 +151,6 @@ void process_can(uint8_t can_number) {
|
|||
}
|
||||
}
|
||||
|
||||
void ignition_can_hook(CAN_FIFOMailBox_TypeDef *to_push) {
|
||||
int bus = GET_BUS(to_push);
|
||||
int addr = GET_ADDR(to_push);
|
||||
int len = GET_LEN(to_push);
|
||||
|
||||
ignition_can_cnt = 0U; // reset counter
|
||||
|
||||
if (bus == 0) {
|
||||
// TODO: verify on all supported GM models that we can reliably detect ignition using only this signal,
|
||||
// since the 0x1F1 signal can briefly go low immediately after ignition
|
||||
if ((addr == 0x160) && (len == 5)) {
|
||||
// this message isn't all zeros when ignition is on
|
||||
ignition_cadillac = GET_BYTES_04(to_push) != 0;
|
||||
}
|
||||
// GM exception
|
||||
if ((addr == 0x1F1) && (len == 8)) {
|
||||
// Bit 5 is ignition "on"
|
||||
bool ignition_gm = ((GET_BYTE(to_push, 0) & 0x20) != 0);
|
||||
ignition_can = ignition_gm || ignition_cadillac;
|
||||
}
|
||||
// Tesla exception
|
||||
if ((addr == 0x348) && (len == 8)) {
|
||||
// GTW_status
|
||||
ignition_can = (GET_BYTE(to_push, 0) & 0x1) != 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// CAN receive handlers
|
||||
// blink blue when we are receiving CAN messages
|
||||
void can_rx(uint8_t can_number) {
|
||||
|
@ -406,34 +206,6 @@ void CAN3_TX_IRQ_Handler(void) { process_can(2); }
|
|||
void CAN3_RX0_IRQ_Handler(void) { can_rx(2); }
|
||||
void CAN3_SCE_IRQ_Handler(void) { can_sce(CAN3); }
|
||||
|
||||
bool can_tx_check_min_slots_free(uint32_t min) {
|
||||
return
|
||||
(can_slots_empty(&can_tx1_q) >= min) &&
|
||||
(can_slots_empty(&can_tx2_q) >= min) &&
|
||||
(can_slots_empty(&can_tx3_q) >= min) &&
|
||||
(can_slots_empty(&can_txgmlan_q) >= min);
|
||||
}
|
||||
|
||||
void can_send(CAN_FIFOMailBox_TypeDef *to_push, uint8_t bus_number, bool skip_tx_hook) {
|
||||
if (skip_tx_hook || safety_tx_hook(to_push) != 0) {
|
||||
if (bus_number < BUS_MAX) {
|
||||
// add CAN packet to send queue
|
||||
// bus number isn't passed through
|
||||
to_push->RDTR &= 0xF;
|
||||
if ((bus_number == 3U) && (can_num_lookup[3] == 0xFFU)) {
|
||||
gmlan_send_errs += bitbang_gmlan(to_push) ? 0U : 1U;
|
||||
} else {
|
||||
can_fwd_errs += can_push(can_queues[bus_number], to_push) ? 0U : 1U;
|
||||
process_can(CAN_NUM_FROM_BUS_NUM(bus_number));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void can_set_forwarding(int from, int to) {
|
||||
can_forwarding[from] = to;
|
||||
}
|
||||
|
||||
bool can_init(uint8_t can_number) {
|
||||
bool ret = false;
|
||||
|
|
@ -0,0 +1,222 @@
|
|||
typedef struct {
|
||||
volatile uint32_t w_ptr;
|
||||
volatile uint32_t r_ptr;
|
||||
uint32_t fifo_size;
|
||||
CAN_FIFOMailBox_TypeDef *elems;
|
||||
} can_ring;
|
||||
|
||||
#define CAN_BUS_RET_FLAG 0x80U
|
||||
#define CAN_BUS_NUM_MASK 0x7FU
|
||||
|
||||
#define BUS_MAX 4U
|
||||
|
||||
uint32_t can_rx_errs = 0;
|
||||
uint32_t can_send_errs = 0;
|
||||
uint32_t can_fwd_errs = 0;
|
||||
uint32_t gmlan_send_errs = 0;
|
||||
|
||||
extern int can_live;
|
||||
extern int pending_can_live;
|
||||
|
||||
// must reinit after changing these
|
||||
extern int can_loopback;
|
||||
extern int can_silent;
|
||||
extern uint32_t can_speed[4];
|
||||
extern uint32_t can_data_speed[3];
|
||||
|
||||
// Ignition detected from CAN meessages
|
||||
bool ignition_can = false;
|
||||
bool ignition_cadillac = false;
|
||||
uint32_t ignition_can_cnt = 0U;
|
||||
|
||||
#define ALL_CAN_SILENT 0xFF
|
||||
#define ALL_CAN_LIVE 0
|
||||
|
||||
int can_live = 0;
|
||||
int pending_can_live = 0;
|
||||
int can_loopback = 0;
|
||||
int can_silent = ALL_CAN_SILENT;
|
||||
|
||||
// ******************* functions prototypes *********************
|
||||
bool can_init(uint8_t can_number);
|
||||
void process_can(uint8_t can_number);
|
||||
|
||||
// ********************* instantiate queues *********************
|
||||
#define can_buffer(x, size) \
|
||||
CAN_FIFOMailBox_TypeDef elems_##x[size]; \
|
||||
can_ring can_##x = { .w_ptr = 0, .r_ptr = 0, .fifo_size = (size), .elems = (CAN_FIFOMailBox_TypeDef *)&(elems_##x) };
|
||||
|
||||
can_buffer(rx_q, 0x1000)
|
||||
can_buffer(tx1_q, 0x100)
|
||||
can_buffer(tx2_q, 0x100)
|
||||
can_buffer(tx3_q, 0x100)
|
||||
can_buffer(txgmlan_q, 0x100)
|
||||
// FIXME:
|
||||
// cppcheck-suppress misra-c2012-9.3
|
||||
can_ring *can_queues[] = {&can_tx1_q, &can_tx2_q, &can_tx3_q, &can_txgmlan_q};
|
||||
|
||||
// global CAN stats
|
||||
int can_rx_cnt = 0;
|
||||
int can_tx_cnt = 0;
|
||||
int can_txd_cnt = 0;
|
||||
int can_err_cnt = 0;
|
||||
int can_overflow_cnt = 0;
|
||||
|
||||
// ********************* interrupt safe queue *********************
|
||||
bool can_pop(can_ring *q, CAN_FIFOMailBox_TypeDef *elem) {
|
||||
bool ret = 0;
|
||||
|
||||
ENTER_CRITICAL();
|
||||
if (q->w_ptr != q->r_ptr) {
|
||||
*elem = q->elems[q->r_ptr];
|
||||
if ((q->r_ptr + 1U) == q->fifo_size) {
|
||||
q->r_ptr = 0;
|
||||
} else {
|
||||
q->r_ptr += 1U;
|
||||
}
|
||||
ret = 1;
|
||||
}
|
||||
EXIT_CRITICAL();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool can_push(can_ring *q, CAN_FIFOMailBox_TypeDef *elem) {
|
||||
bool ret = false;
|
||||
uint32_t next_w_ptr;
|
||||
|
||||
ENTER_CRITICAL();
|
||||
if ((q->w_ptr + 1U) == q->fifo_size) {
|
||||
next_w_ptr = 0;
|
||||
} else {
|
||||
next_w_ptr = q->w_ptr + 1U;
|
||||
}
|
||||
if (next_w_ptr != q->r_ptr) {
|
||||
q->elems[q->w_ptr] = *elem;
|
||||
q->w_ptr = next_w_ptr;
|
||||
ret = true;
|
||||
}
|
||||
EXIT_CRITICAL();
|
||||
if (!ret) {
|
||||
can_overflow_cnt++;
|
||||
#ifdef DEBUG
|
||||
puts("can_push failed!\n");
|
||||
#endif
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
uint32_t can_slots_empty(can_ring *q) {
|
||||
uint32_t ret = 0;
|
||||
|
||||
ENTER_CRITICAL();
|
||||
if (q->w_ptr >= q->r_ptr) {
|
||||
ret = q->fifo_size - 1U - q->w_ptr + q->r_ptr;
|
||||
} else {
|
||||
ret = q->r_ptr - q->w_ptr - 1U;
|
||||
}
|
||||
EXIT_CRITICAL();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void can_clear(can_ring *q) {
|
||||
ENTER_CRITICAL();
|
||||
q->w_ptr = 0;
|
||||
q->r_ptr = 0;
|
||||
EXIT_CRITICAL();
|
||||
}
|
||||
|
||||
// assign CAN numbering
|
||||
// bus num: Can bus number on ODB connector. Sent to/from USB
|
||||
// Min: 0; Max: 127; Bit 7 marks message as receipt (bus 129 is receipt for but 1)
|
||||
// cans: Look up MCU can interface from bus number
|
||||
// can number: numeric lookup for MCU CAN interfaces (0 = CAN1, 1 = CAN2, etc);
|
||||
// bus_lookup: Translates from 'can number' to 'bus number'.
|
||||
// can_num_lookup: Translates from 'bus number' to 'can number'.
|
||||
// can_forwarding: Given a bus num, lookup bus num to forward to. -1 means no forward.
|
||||
|
||||
// Helpers
|
||||
// Panda: Bus 0=CAN1 Bus 1=CAN2 Bus 2=CAN3
|
||||
uint8_t bus_lookup[] = {0,1,2};
|
||||
uint8_t can_num_lookup[] = {0,1,2,-1};
|
||||
int8_t can_forwarding[] = {-1,-1,-1,-1};
|
||||
uint32_t can_speed[] = {5000, 5000, 5000, 333};
|
||||
uint32_t can_data_speed[] = {5000, 5000, 5000}; //For CAN FD with BRS only
|
||||
#define CAN_MAX 3U
|
||||
|
||||
#define CANIF_FROM_CAN_NUM(num) (cans[num])
|
||||
#define BUS_NUM_FROM_CAN_NUM(num) (bus_lookup[num])
|
||||
#define CAN_NUM_FROM_BUS_NUM(num) (can_num_lookup[num])
|
||||
|
||||
void can_init_all(void) {
|
||||
bool ret = true;
|
||||
for (uint8_t i=0U; i < CAN_MAX; i++) {
|
||||
can_clear(can_queues[i]);
|
||||
ret &= can_init(i);
|
||||
}
|
||||
UNUSED(ret);
|
||||
}
|
||||
|
||||
void can_flip_buses(uint8_t bus1, uint8_t bus2){
|
||||
bus_lookup[bus1] = bus2;
|
||||
bus_lookup[bus2] = bus1;
|
||||
can_num_lookup[bus1] = bus2;
|
||||
can_num_lookup[bus2] = bus1;
|
||||
}
|
||||
|
||||
void ignition_can_hook(CAN_FIFOMailBox_TypeDef *to_push) {
|
||||
int bus = GET_BUS(to_push);
|
||||
int addr = GET_ADDR(to_push);
|
||||
int len = GET_LEN(to_push);
|
||||
|
||||
ignition_can_cnt = 0U; // reset counter
|
||||
|
||||
if (bus == 0) {
|
||||
// TODO: verify on all supported GM models that we can reliably detect ignition using only this signal,
|
||||
// since the 0x1F1 signal can briefly go low immediately after ignition
|
||||
if ((addr == 0x160) && (len == 5)) {
|
||||
// this message isn't all zeros when ignition is on
|
||||
ignition_cadillac = GET_BYTES_04(to_push) != 0;
|
||||
}
|
||||
// GM exception
|
||||
if ((addr == 0x1F1) && (len == 8)) {
|
||||
// Bit 5 is ignition "on"
|
||||
bool ignition_gm = ((GET_BYTE(to_push, 0) & 0x20) != 0);
|
||||
ignition_can = ignition_gm || ignition_cadillac;
|
||||
}
|
||||
// Tesla exception
|
||||
if ((addr == 0x348) && (len == 8)) {
|
||||
// GTW_status
|
||||
ignition_can = (GET_BYTE(to_push, 0) & 0x1) != 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool can_tx_check_min_slots_free(uint32_t min) {
|
||||
return
|
||||
(can_slots_empty(&can_tx1_q) >= min) &&
|
||||
(can_slots_empty(&can_tx2_q) >= min) &&
|
||||
(can_slots_empty(&can_tx3_q) >= min) &&
|
||||
(can_slots_empty(&can_txgmlan_q) >= min);
|
||||
}
|
||||
|
||||
void can_send(CAN_FIFOMailBox_TypeDef *to_push, uint8_t bus_number, bool skip_tx_hook) {
|
||||
if (skip_tx_hook || safety_tx_hook(to_push) != 0) {
|
||||
if (bus_number < BUS_MAX) {
|
||||
// add CAN packet to send queue
|
||||
// bus number isn't passed through
|
||||
to_push->RDTR &= 0xF;
|
||||
if ((bus_number == 3U) && (can_num_lookup[3] == 0xFFU)) {
|
||||
gmlan_send_errs += bitbang_gmlan(to_push) ? 0U : 1U;
|
||||
} else {
|
||||
can_fwd_errs += can_push(can_queues[bus_number], to_push) ? 0U : 1U;
|
||||
process_can(CAN_NUM_FROM_BUS_NUM(bus_number));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void can_set_forwarding(int from, int to) {
|
||||
can_forwarding[from] = to;
|
||||
}
|
|
@ -0,0 +1,203 @@
|
|||
// IRQs: FDCAN1_IT0, FDCAN1_IT1
|
||||
// FDCAN2_IT0, FDCAN2_IT1
|
||||
// FDCAN3_IT0, FDCAN3_IT1
|
||||
|
||||
#define BUS_OFF_FAIL_LIMIT 2U
|
||||
uint8_t bus_off_err[] = {0U, 0U, 0U};
|
||||
|
||||
FDCAN_GlobalTypeDef *cans[] = {FDCAN1, FDCAN2, FDCAN3};
|
||||
|
||||
bool can_set_speed(uint8_t can_number) {
|
||||
bool ret = true;
|
||||
FDCAN_GlobalTypeDef *CANx = CANIF_FROM_CAN_NUM(can_number);
|
||||
uint8_t bus_number = BUS_NUM_FROM_CAN_NUM(can_number);
|
||||
|
||||
ret &= llcan_set_speed(CANx, can_speed[bus_number], can_data_speed[bus_number], can_loopback, (unsigned int)(can_silent) & (1U << can_number));
|
||||
return ret;
|
||||
}
|
||||
|
||||
void can_set_gmlan(uint8_t bus) {
|
||||
UNUSED(bus);
|
||||
puts("GMLAN not available on red panda\n");
|
||||
}
|
||||
|
||||
void cycle_transceiver(uint8_t can_number) {
|
||||
// FDCAN1 = trans 1, FDCAN3 = trans 3, FDCAN2 = trans 2 normal or 4 flipped harness
|
||||
uint8_t transceiver_number = can_number;
|
||||
if (can_number == 2U) {
|
||||
uint8_t flip = (car_harness_status == HARNESS_STATUS_FLIPPED) ? 2U : 0U;
|
||||
transceiver_number += flip;
|
||||
}
|
||||
current_board->enable_can_transceiver(transceiver_number, false);
|
||||
delay(20000);
|
||||
current_board->enable_can_transceiver(transceiver_number, true);
|
||||
bus_off_err[can_number] = 0U;
|
||||
puts("Cycled transceiver number: "); puth(transceiver_number); puts("\n");
|
||||
}
|
||||
|
||||
// ***************************** CAN *****************************
|
||||
void process_can(uint8_t can_number) {
|
||||
if (can_number != 0xffU) {
|
||||
ENTER_CRITICAL();
|
||||
|
||||
FDCAN_GlobalTypeDef *CANx = CANIF_FROM_CAN_NUM(can_number);
|
||||
uint8_t bus_number = BUS_NUM_FROM_CAN_NUM(can_number);
|
||||
|
||||
CANx->IR |= FDCAN_IR_TFE; // Clear Tx FIFO Empty flag
|
||||
|
||||
if ((CANx->TXFQS & FDCAN_TXFQS_TFQF) == 0) {
|
||||
CAN_FIFOMailBox_TypeDef to_send;
|
||||
if (can_pop(can_queues[bus_number], &to_send)) {
|
||||
can_tx_cnt += 1;
|
||||
uint32_t TxFIFOSA = FDCAN_START_ADDRESS + (can_number * FDCAN_OFFSET) + (FDCAN_RX_FIFO_0_EL_CNT * FDCAN_RX_FIFO_0_EL_SIZE);
|
||||
uint8_t tx_index = (CANx->TXFQS >> FDCAN_TXFQS_TFQPI_Pos) & 0x1F;
|
||||
// only send if we have received a packet
|
||||
CAN_FIFOMailBox_TypeDef *fifo;
|
||||
fifo = (CAN_FIFOMailBox_TypeDef *)(TxFIFOSA + (tx_index * FDCAN_TX_FIFO_EL_SIZE));
|
||||
|
||||
// Convert from "mailbox type"
|
||||
fifo->RIR = ((to_send.RIR & 0x6) << 28) | (to_send.RIR >> 3); // identifier format and frame type | identifier
|
||||
//REDEBUG: enable CAN FD and BRS for test purposes
|
||||
//fifo->RDTR = ((to_send.RDTR & 0xF) << 16) | ((to_send.RDTR) >> 16) | (1U << 21) | (1U << 20); // DLC (length) | timestamp | enable CAN FD | enable BRS
|
||||
fifo->RDTR = ((to_send.RDTR & 0xF) << 16) | ((to_send.RDTR) >> 16); // DLC (length) | timestamp
|
||||
fifo->RDLR = to_send.RDLR;
|
||||
fifo->RDHR = to_send.RDHR;
|
||||
|
||||
CANx->TXBAR = (1UL << tx_index);
|
||||
|
||||
// Send back to USB
|
||||
can_txd_cnt += 1;
|
||||
CAN_FIFOMailBox_TypeDef to_push;
|
||||
to_push.RIR = to_send.RIR;
|
||||
to_push.RDTR = (to_send.RDTR & 0xFFFF000FU) | ((CAN_BUS_RET_FLAG | bus_number) << 4);
|
||||
to_push.RDLR = to_send.RDLR;
|
||||
to_push.RDHR = to_send.RDHR;
|
||||
can_send_errs += can_push(&can_rx_q, &to_push) ? 0U : 1U;
|
||||
|
||||
if (can_tx_check_min_slots_free(MAX_CAN_MSGS_PER_BULK_TRANSFER)) {
|
||||
usb_outep3_resume_if_paused();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Recover after Bus-off state
|
||||
if (((CANx->PSR & FDCAN_PSR_BO) != 0) && ((CANx->CCCR & FDCAN_CCCR_INIT) != 0)) {
|
||||
bus_off_err[can_number] += 1U;
|
||||
puts("CAN is in Bus_Off state! Resetting... CAN number: "); puth(can_number); puts("\n");
|
||||
if (bus_off_err[can_number] > BUS_OFF_FAIL_LIMIT) {
|
||||
cycle_transceiver(can_number);
|
||||
}
|
||||
CANx->IR = 0xFFC60000U; // Reset all flags(Only errors!)
|
||||
CANx->CCCR &= ~(FDCAN_CCCR_INIT);
|
||||
uint32_t timeout_counter = 0U;
|
||||
while((CANx->CCCR & FDCAN_CCCR_INIT) != 0) {
|
||||
// Delay for about 1ms
|
||||
delay(10000);
|
||||
timeout_counter++;
|
||||
|
||||
if(timeout_counter >= CAN_INIT_TIMEOUT_MS){
|
||||
puts(CAN_NAME_FROM_CANIF(CANx)); puts(" Bus_Off reset timed out!\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
EXIT_CRITICAL();
|
||||
}
|
||||
}
|
||||
|
||||
// CAN receive handlers
|
||||
// blink blue when we are receiving CAN messages
|
||||
void can_rx(uint8_t can_number) {
|
||||
FDCAN_GlobalTypeDef *CANx = CANIF_FROM_CAN_NUM(can_number);
|
||||
uint8_t bus_number = BUS_NUM_FROM_CAN_NUM(can_number);
|
||||
uint8_t rx_fifo_idx;
|
||||
|
||||
// Rx FIFO 0 new message
|
||||
if((CANx->IR & FDCAN_IR_RF0N) != 0) {
|
||||
CANx->IR |= FDCAN_IR_RF0N;
|
||||
while((CANx->RXF0S & FDCAN_RXF0S_F0FL) != 0) {
|
||||
can_rx_cnt += 1;
|
||||
|
||||
// can is live
|
||||
pending_can_live = 1;
|
||||
|
||||
// getting new message index (0 to 63)
|
||||
rx_fifo_idx = (uint8_t)((CANx->RXF0S >> FDCAN_RXF0S_F0GI_Pos) & 0x3F);
|
||||
|
||||
uint32_t RxFIFO0SA = FDCAN_START_ADDRESS + (can_number * FDCAN_OFFSET);
|
||||
CAN_FIFOMailBox_TypeDef to_push;
|
||||
CAN_FIFOMailBox_TypeDef *fifo;
|
||||
|
||||
// getting address
|
||||
fifo = (CAN_FIFOMailBox_TypeDef *)(RxFIFO0SA + (rx_fifo_idx * FDCAN_RX_FIFO_0_EL_SIZE));
|
||||
|
||||
// Need to convert real CAN frame format to mailbox "type"
|
||||
to_push.RIR = ((fifo->RIR >> 28) & 0x6) | (fifo->RIR << 3); // identifier format and frame type | identifier
|
||||
to_push.RDTR = ((fifo->RDTR >> 16) & 0xF) | (fifo->RDTR << 16); // DLC (length) | timestamp
|
||||
to_push.RDLR = fifo->RDLR;
|
||||
to_push.RDHR = fifo->RDHR;
|
||||
|
||||
// modify RDTR for our API
|
||||
to_push.RDTR = (to_push.RDTR & 0xFFFF000F) | (bus_number << 4);
|
||||
|
||||
// forwarding (panda only)
|
||||
int bus_fwd_num = (can_forwarding[bus_number] != -1) ? can_forwarding[bus_number] : safety_fwd_hook(bus_number, &to_push);
|
||||
if (bus_fwd_num != -1) {
|
||||
CAN_FIFOMailBox_TypeDef to_send;
|
||||
to_send.RIR = to_push.RIR;
|
||||
to_send.RDTR = to_push.RDTR;
|
||||
to_send.RDLR = to_push.RDLR;
|
||||
to_send.RDHR = to_push.RDHR;
|
||||
can_send(&to_send, bus_fwd_num, true);
|
||||
}
|
||||
|
||||
can_rx_errs += safety_rx_hook(&to_push) ? 0U : 1U;
|
||||
ignition_can_hook(&to_push);
|
||||
|
||||
current_board->set_led(LED_BLUE, true);
|
||||
can_send_errs += can_push(&can_rx_q, &to_push) ? 0U : 1U;
|
||||
|
||||
// update read index
|
||||
CANx->RXF0A = rx_fifo_idx;
|
||||
}
|
||||
|
||||
} else if((CANx->IR & (FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_EW | FDCAN_IR_MRAF | FDCAN_IR_TOO)) != 0) {
|
||||
#ifdef DEBUG
|
||||
puts("FDCAN error, FDCAN_IR: ");puth(CANx->IR);puts("\n");
|
||||
#endif
|
||||
CANx->IR |= (FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_EW | FDCAN_IR_MRAF | FDCAN_IR_TOO); // Clean all error flags
|
||||
can_err_cnt += 1;
|
||||
} else {
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void FDCAN1_IT0_IRQ_Handler(void) { can_rx(0); }
|
||||
void FDCAN1_IT1_IRQ_Handler(void) { process_can(0); }
|
||||
|
||||
void FDCAN2_IT0_IRQ_Handler(void) { can_rx(1); }
|
||||
void FDCAN2_IT1_IRQ_Handler(void) { process_can(1); }
|
||||
|
||||
void FDCAN3_IT0_IRQ_Handler(void) { can_rx(2); }
|
||||
void FDCAN3_IT1_IRQ_Handler(void) { process_can(2); }
|
||||
|
||||
bool can_init(uint8_t can_number) {
|
||||
bool ret = false;
|
||||
|
||||
REGISTER_INTERRUPT(FDCAN1_IT0_IRQn, FDCAN1_IT0_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_1)
|
||||
REGISTER_INTERRUPT(FDCAN1_IT1_IRQn, FDCAN1_IT1_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_1)
|
||||
REGISTER_INTERRUPT(FDCAN2_IT0_IRQn, FDCAN2_IT0_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_2)
|
||||
REGISTER_INTERRUPT(FDCAN2_IT1_IRQn, FDCAN2_IT1_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_2)
|
||||
REGISTER_INTERRUPT(FDCAN3_IT0_IRQn, FDCAN3_IT0_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_3)
|
||||
REGISTER_INTERRUPT(FDCAN3_IT1_IRQn, FDCAN3_IT1_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_3)
|
||||
|
||||
if (can_number != 0xffU) {
|
||||
FDCAN_GlobalTypeDef *CANx = CANIF_FROM_CAN_NUM(can_number);
|
||||
ret &= can_set_speed(can_number);
|
||||
ret &= llcan_init(CANx);
|
||||
// in case there are queued up messages
|
||||
process_can(can_number);
|
||||
}
|
||||
return ret;
|
||||
}
|
|
@ -38,6 +38,7 @@ typedef struct uart_ring {
|
|||
// ***************************** Function prototypes *****************************
|
||||
void debug_ring_callback(uart_ring *ring);
|
||||
void uart_tx_ring(uart_ring *q);
|
||||
void uart_send_break(uart_ring *u);
|
||||
|
||||
// ******************************** UART buffers ********************************
|
||||
|
||||
|
@ -138,11 +139,6 @@ void uart_flush_sync(uart_ring *q) {
|
|||
}
|
||||
}
|
||||
|
||||
void uart_send_break(uart_ring *u) {
|
||||
while ((u->uart->CR1 & USART_CR1_SBK) != 0);
|
||||
u->uart->CR1 |= USART_CR1_SBK;
|
||||
}
|
||||
|
||||
void clear_uart_buff(uart_ring *q) {
|
||||
ENTER_CRITICAL();
|
||||
q->w_ptr_tx = 0;
|
||||
|
|
|
@ -123,7 +123,7 @@ uint8_t device_desc[] = {
|
|||
0xFF, 0xFF, 0xFF, 0x40, // Class, Subclass, Protocol, Max Packet Size
|
||||
TOUSBORDER(USB_VID), // idVendor
|
||||
TOUSBORDER(USB_PID), // idProduct
|
||||
0x00, 0x23, // bcdDevice
|
||||
0x00, 0x00, // bcdDevice
|
||||
0x01, 0x02, // Manufacturer, Product
|
||||
0x03, 0x01 // Serial Number, Num Configurations
|
||||
};
|
||||
|
@ -526,6 +526,8 @@ void usb_setup(void) {
|
|||
case USB_DESC_TYPE_DEVICE:
|
||||
//puts(" writing device descriptor\n");
|
||||
|
||||
// set bcdDevice to hardware type
|
||||
device_desc[13] = hw_type;
|
||||
// setup transfer
|
||||
USB_WritePacket(device_desc, MIN(sizeof(device_desc), setup.b.wLength.w), 0);
|
||||
USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK;
|
||||
|
|
|
@ -0,0 +1,5 @@
|
|||
#!/usr/bin/env sh
|
||||
set -e
|
||||
|
||||
PANDA_GEN3=1 scons -u
|
||||
PYTHONPATH=.. python3 -c "from python import Panda; Panda().flash('obj/panda_h7.bin.signed')"
|
|
@ -1,6 +1,6 @@
|
|||
// flasher state variables
|
||||
uint32_t *prog_ptr = NULL;
|
||||
int unlocked = 0;
|
||||
bool unlocked = false;
|
||||
|
||||
#ifdef uart_ring
|
||||
void debug_ring_callback(uart_ring *ring) {}
|
||||
|
@ -26,32 +26,27 @@ int usb_cb_control_msg(USB_Setup_TypeDef *setup, uint8_t *resp, bool hardwired)
|
|||
break;
|
||||
// **** 0xb1: unlock flash
|
||||
case 0xb1:
|
||||
if (FLASH->CR & FLASH_CR_LOCK) {
|
||||
FLASH->KEYR = 0x45670123;
|
||||
FLASH->KEYR = 0xCDEF89AB;
|
||||
if (flash_is_locked()) {
|
||||
flash_unlock();
|
||||
resp[1] = 0xff;
|
||||
}
|
||||
current_board->set_led(LED_GREEN, 1);
|
||||
unlocked = 1;
|
||||
prog_ptr = (uint32_t *)0x8004000;
|
||||
unlocked = true;
|
||||
prog_ptr = (uint32_t *)APP_START_ADDRESS;
|
||||
break;
|
||||
// **** 0xb2: erase sector
|
||||
case 0xb2:
|
||||
sec = setup->b.wValue.w;
|
||||
// don't erase the bootloader
|
||||
if (sec != 0 && sec < 12 && unlocked) {
|
||||
FLASH->CR = (sec << 3) | FLASH_CR_SER;
|
||||
FLASH->CR |= FLASH_CR_STRT;
|
||||
while (FLASH->SR & FLASH_SR_BSY);
|
||||
if (flash_erase_sector(sec, unlocked)) {
|
||||
resp[1] = 0xff;
|
||||
}
|
||||
break;
|
||||
// **** 0xd0: fetch serial number
|
||||
case 0xd0:
|
||||
#ifdef STM32F4
|
||||
#ifndef STM32F2
|
||||
// addresses are OTP
|
||||
if (setup->b.wValue.w == 1) {
|
||||
memcpy(resp, (void *)0x1fff79c0, 0x10);
|
||||
memcpy(resp, (void *)DEVICE_SERIAL_NUMBER_ADDRESS, 0x10);
|
||||
resp_len = 0x10;
|
||||
} else {
|
||||
get_provision_chunk(resp);
|
||||
|
@ -93,6 +88,7 @@ int usb_cb_control_msg(USB_Setup_TypeDef *setup, uint8_t *resp, bool hardwired)
|
|||
break;
|
||||
// **** 0xd8: reset ST
|
||||
case 0xd8:
|
||||
flush_write_buffer();
|
||||
NVIC_SystemReset();
|
||||
break;
|
||||
}
|
||||
|
@ -122,11 +118,7 @@ void usb_cb_ep2_out(void *usbdata, int len, bool hardwired) {
|
|||
UNUSED(hardwired);
|
||||
current_board->set_led(LED_RED, 0);
|
||||
for (int i = 0; i < len/4; i++) {
|
||||
// program byte 1
|
||||
FLASH->CR = FLASH_CR_PSIZE_1 | FLASH_CR_PG;
|
||||
|
||||
*prog_ptr = *(uint32_t*)(usbdata+(i*4));
|
||||
while (FLASH->SR & FLASH_SR_BSY);
|
||||
flash_write_word(prog_ptr, *(uint32_t*)(usbdata+(i*4)));
|
||||
|
||||
//*(uint64_t*)(&spi_tx_buf[0x30+(i*4)]) = *prog_ptr;
|
||||
prog_ptr++;
|
||||
|
@ -153,7 +145,7 @@ int spi_cb_rx(uint8_t *data, int len, uint8_t *data_out) {
|
|||
|
||||
#ifdef PEDAL
|
||||
|
||||
#include "stm32fx/llcan.h"
|
||||
#include "stm32fx/llbxcan.h"
|
||||
#define CAN CAN1
|
||||
|
||||
#define CAN_BL_INPUT 0x1
|
||||
|
@ -278,10 +270,7 @@ void soft_flasher_start(void) {
|
|||
|
||||
enter_bootloader_mode = 0;
|
||||
|
||||
RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN;
|
||||
RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
|
||||
RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
|
||||
RCC->APB1ENR |= RCC_APB1ENR_USART2EN;
|
||||
flasher_peripherals_init();
|
||||
|
||||
// pedal has the canloader
|
||||
#ifdef PEDAL
|
||||
|
@ -297,23 +286,8 @@ void soft_flasher_start(void) {
|
|||
llcan_init(CAN1);
|
||||
#endif
|
||||
|
||||
// A4,A5,A6,A7: setup SPI
|
||||
set_gpio_alternate(GPIOA, 4, GPIO_AF5_SPI1);
|
||||
set_gpio_alternate(GPIOA, 5, GPIO_AF5_SPI1);
|
||||
set_gpio_alternate(GPIOA, 6, GPIO_AF5_SPI1);
|
||||
set_gpio_alternate(GPIOA, 7, GPIO_AF5_SPI1);
|
||||
|
||||
// A2,A3: USART 2 for debugging
|
||||
set_gpio_alternate(GPIOA, 2, GPIO_AF7_USART2);
|
||||
set_gpio_alternate(GPIOA, 3, GPIO_AF7_USART2);
|
||||
|
||||
// A11,A12: USB
|
||||
set_gpio_alternate(GPIOA, 11, GPIO_AF10_OTG_FS);
|
||||
set_gpio_alternate(GPIOA, 12, GPIO_AF10_OTG_FS);
|
||||
GPIOA->OSPEEDR = GPIO_OSPEEDER_OSPEEDR11 | GPIO_OSPEEDER_OSPEEDR12;
|
||||
|
||||
// flasher
|
||||
//spi_init();
|
||||
gpio_usart2_init();
|
||||
gpio_usb_init();
|
||||
|
||||
// enable USB
|
||||
usb_init();
|
|
@ -12,7 +12,13 @@
|
|||
#include "power_saving.h"
|
||||
#include "safety.h"
|
||||
|
||||
#include "drivers/can.h"
|
||||
#include "drivers/can_common.h"
|
||||
|
||||
#ifdef STM32H7
|
||||
#include "drivers/fdcan.h"
|
||||
#else
|
||||
#include "drivers/bxcan.h"
|
||||
#endif
|
||||
|
||||
#include "obj/gitversion.h"
|
||||
|
||||
|
@ -464,6 +470,7 @@ int usb_cb_control_msg(USB_Setup_TypeDef *setup, uint8_t *resp, bool hardwired)
|
|||
// **** 0xde: set can bitrate
|
||||
case 0xde:
|
||||
if (setup->b.wValue.w < BUS_MAX) {
|
||||
// TODO: add sanity check, ideally check if value is correct(from array of correct values)
|
||||
can_speed[setup->b.wValue.w] = setup->b.wIndex.w;
|
||||
bool ret = can_init(CAN_NUM_FROM_BUS_NUM(setup->b.wValue.w));
|
||||
UNUSED(ret);
|
||||
|
@ -617,6 +624,15 @@ int usb_cb_control_msg(USB_Setup_TypeDef *setup, uint8_t *resp, bool hardwired)
|
|||
heartbeat_disabled = true;
|
||||
break;
|
||||
#endif
|
||||
// **** 0xde: set CAN FD data bitrate
|
||||
case 0xf9:
|
||||
if (setup->b.wValue.w < CAN_MAX) {
|
||||
// TODO: add sanity check, ideally check if value is correct(from array of correct values)
|
||||
can_data_speed[setup->b.wValue.w] = setup->b.wIndex.w;
|
||||
bool ret = can_init(CAN_NUM_FROM_BUS_NUM(setup->b.wValue.w));
|
||||
UNUSED(ret);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
puts("NO HANDLER ");
|
||||
puth(setup->b.bRequest);
|
||||
|
|
|
@ -0,0 +1,11 @@
|
|||
#!/usr/bin/env sh
|
||||
set -e
|
||||
|
||||
DFU_UTIL="dfu-util"
|
||||
|
||||
PANDA_H7=1 scons -u
|
||||
|
||||
PYTHONPATH=.. python3 -c "from python import Panda; Panda().reset(enter_bootstub=True); Panda().reset(enter_bootloader=True)" || true
|
||||
sleep 1
|
||||
$DFU_UTIL -d 0483:df11 -a 0 -s 0x08020000 -D obj/panda_h7.bin.signed
|
||||
$DFU_UTIL -d 0483:df11 -a 0 -s 0x08000000:leave -D obj/bootstub.panda_h7.bin
|
|
@ -7,8 +7,8 @@
|
|||
// brake rising edge
|
||||
// brake > 0mph
|
||||
const CanMsg HONDA_N_TX_MSGS[] = {{0xE4, 0, 5}, {0x194, 0, 4}, {0x1FA, 0, 8}, {0x200, 0, 6}, {0x30C, 0, 8}, {0x33D, 0, 5}};
|
||||
const CanMsg HONDA_BG_TX_MSGS[] = {{0xE4, 2, 5}, {0xE5, 2, 8}, {0x296, 0, 4}, {0x33D, 2, 5}}; // Bosch Giraffe
|
||||
const CanMsg HONDA_BH_TX_MSGS[] = {{0xE4, 0, 5}, {0xE5, 0, 8}, {0x296, 1, 4}, {0x33D, 0, 5}}; // Bosch Harness
|
||||
const CanMsg HONDA_BG_TX_MSGS[] = {{0xE4, 2, 5}, {0xE5, 2, 8}, {0x296, 0, 4}, {0x33D, 2, 5}, {0x33DA, 2, 5}, {0x33DB, 2, 8}}; // Bosch Giraffe
|
||||
const CanMsg HONDA_BH_TX_MSGS[] = {{0xE4, 0, 5}, {0xE5, 0, 8}, {0x296, 1, 4}, {0x33D, 0, 5}, {0x33DA, 0, 5}, {0x33DB, 0, 8}}; // Bosch Harness
|
||||
const CanMsg HONDA_BG_LONG_TX_MSGS[] = {{0xE4, 0, 5}, {0x1DF, 0, 8}, {0x1EF, 0, 8}, {0x1FA, 0, 8}, {0x30C, 0, 8}, {0x33D, 0, 5}, {0x39F, 0, 8}, {0x18DAB0F1, 0, 8}}; // Bosch Giraffe w/ gas and brakes
|
||||
const CanMsg HONDA_BH_LONG_TX_MSGS[] = {{0xE4, 1, 5}, {0x1DF, 1, 8}, {0x1EF, 1, 8}, {0x1FA, 1, 8}, {0x30C, 1, 8}, {0x33D, 1, 5}, {0x39F, 1, 8}, {0x18DAB0F1, 1, 8}}; // Bosch Harness w/ gas and brakes
|
||||
|
||||
|
@ -376,7 +376,7 @@ static int honda_bosch_fwd_hook(int bus_num, CAN_FIFOMailBox_TypeDef *to_fwd) {
|
|||
}
|
||||
if (bus_num == bus_rdr_cam) {
|
||||
int addr = GET_ADDR(to_fwd);
|
||||
int is_lkas_msg = (addr == 0xE4) || (addr == 0xE5) || (addr == 0x33D);
|
||||
int is_lkas_msg = (addr == 0xE4) || (addr == 0xE5) || (addr == 0x33D) || (addr == 0x33DA) || (addr == 0x33DB);
|
||||
if (!is_lkas_msg) {
|
||||
bus_fwd = bus_rdr_car;
|
||||
}
|
||||
|
|
|
@ -2,6 +2,7 @@
|
|||
// Hardware abstraction layer for all different supported boards //
|
||||
// ///////////////////////////////////////////////////////////// //
|
||||
#include "boards/board_declarations.h"
|
||||
#include "boards/unused_funcs.h"
|
||||
|
||||
// ///// Board definition and detection ///// //
|
||||
#include "drivers/harness.h"
|
||||
|
|
|
@ -10,8 +10,8 @@
|
|||
* is using in the C source code, usually in main.c. This file contains:
|
||||
* - Configuration section that allows to select:
|
||||
* - The STM32F2xx device used in the target application
|
||||
* - To use or not the peripheral’s drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral’s registers
|
||||
* - To use or not the peripheral’s drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral’s registers
|
||||
* rather than drivers API), this option is controlled by
|
||||
* "#define USE_HAL_DRIVER"
|
||||
*
|
||||
|
@ -74,7 +74,7 @@
|
|||
/* Uncomment the line below according to the target STM32 device used in your
|
||||
application
|
||||
*/
|
||||
#if !defined (STM32F205xx) && !defined (STM32F215xx) && !defined (STM32F207xx) && !defined (STM32F217xx)
|
||||
/* #if !defined (STM32F205xx) && !defined (STM32F215xx) && !defined (STM32F207xx) && !defined (STM32F217xx) */
|
||||
|
||||
/* #define STM32F205xx */ /*!< STM32F205RG, STM32F205VG, STM32F205ZG, STM32F205RF, STM32F205VF, STM32F205ZF,
|
||||
STM32F205RE, STM32F205VE, STM32F205ZE, STM32F205RC, STM32F205VC, STM32F205ZC,
|
||||
|
@ -84,7 +84,7 @@
|
|||
STM32F207VE, STM32F207ZE, STM32F207IE, STM32F207VC, STM32F207ZC and STM32F207IC Devices */
|
||||
/* #define STM32F217xx */ /*!< STM32F217VG, STM32F217ZG, STM32F217IG, STM32F217VE, STM32F217ZE and STM32F217IE Devices */
|
||||
|
||||
#endif
|
||||
//#endif
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
devices, you can define the device in your toolchain compiler preprocessor.
|
||||
|
@ -118,14 +118,14 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F205xx)
|
||||
#include "stm32f205xx.h"
|
||||
#elif defined(STM32F215xx)
|
||||
#if defined(STM32F215xx)
|
||||
#include "stm32f215xx.h"
|
||||
#elif defined(STM32F207xx)
|
||||
#include "stm32f207xx.h"
|
||||
#elif defined(STM32F217xx)
|
||||
#include "stm32f217xx.h"
|
||||
#elif defined(STM32F205xx)
|
||||
#include "stm32f205xx.h"
|
||||
// #elif defined(STM32F207xx)
|
||||
// #include "stm32f207xx.h"
|
||||
// #elif defined(STM32F217xx)
|
||||
// #include "stm32f217xx.h"
|
||||
#else
|
||||
#error "Please select first the target STM32F2xx device used in your application (in stm32f2xx.h file)"
|
||||
#endif
|
||||
|
|
|
@ -10,8 +10,8 @@
|
|||
* is using in the C source code, usually in main.c. This file contains:
|
||||
* - Configuration section that allows to select:
|
||||
* - The STM32F4xx device used in the target application
|
||||
* - To use or not the peripheral’s drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral’s registers
|
||||
* - To use or not the peripheral’s drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral’s registers
|
||||
* rather than drivers API), this option is controlled by
|
||||
* "#define USE_HAL_DRIVER"
|
||||
*
|
||||
|
@ -74,12 +74,12 @@
|
|||
/* Uncomment the line below according to the target STM32 device used in your
|
||||
application
|
||||
*/
|
||||
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
|
||||
/* #if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
|
||||
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
|
||||
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
|
||||
!defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
|
||||
!defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
|
||||
!defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
|
||||
!defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx) */
|
||||
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
|
||||
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
|
||||
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
|
||||
|
@ -109,7 +109,7 @@
|
|||
/* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
|
||||
STM32F413RG, STM32F413VG and STM32F413ZG Devices */
|
||||
/* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
|
||||
#endif
|
||||
//#endif
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
devices, you can define the device in your toolchain compiler preprocessor.
|
||||
|
@ -143,51 +143,51 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F405xx)
|
||||
#include "stm32f405xx.h"
|
||||
#elif defined(STM32F415xx)
|
||||
#include "stm32f415xx.h"
|
||||
#elif defined(STM32F407xx)
|
||||
#include "stm32f407xx.h"
|
||||
#elif defined(STM32F417xx)
|
||||
#include "stm32f417xx.h"
|
||||
#elif defined(STM32F427xx)
|
||||
#include "stm32f427xx.h"
|
||||
#elif defined(STM32F437xx)
|
||||
#include "stm32f437xx.h"
|
||||
#elif defined(STM32F429xx)
|
||||
#include "stm32f429xx.h"
|
||||
#elif defined(STM32F439xx)
|
||||
#include "stm32f439xx.h"
|
||||
#elif defined(STM32F401xC)
|
||||
#include "stm32f401xc.h"
|
||||
#elif defined(STM32F401xE)
|
||||
#include "stm32f401xe.h"
|
||||
#elif defined(STM32F410Tx)
|
||||
#include "stm32f410tx.h"
|
||||
#elif defined(STM32F410Cx)
|
||||
#include "stm32f410cx.h"
|
||||
#elif defined(STM32F410Rx)
|
||||
#include "stm32f410rx.h"
|
||||
#elif defined(STM32F411xE)
|
||||
#include "stm32f411xe.h"
|
||||
#elif defined(STM32F446xx)
|
||||
#include "stm32f446xx.h"
|
||||
#elif defined(STM32F469xx)
|
||||
#include "stm32f469xx.h"
|
||||
#elif defined(STM32F479xx)
|
||||
#include "stm32f479xx.h"
|
||||
#elif defined(STM32F412Cx)
|
||||
#include "stm32f412cx.h"
|
||||
#elif defined(STM32F412Zx)
|
||||
#include "stm32f412zx.h"
|
||||
#elif defined(STM32F412Rx)
|
||||
#include "stm32f412rx.h"
|
||||
#elif defined(STM32F412Vx)
|
||||
#include "stm32f412vx.h"
|
||||
#elif defined(STM32F413xx)
|
||||
// #if defined(STM32F405xx)
|
||||
// #include "stm32f405xx.h"
|
||||
// #elif defined(STM32F415xx)
|
||||
// #include "stm32f415xx.h"
|
||||
// #elif defined(STM32F407xx)
|
||||
// #include "stm32f407xx.h"
|
||||
// #elif defined(STM32F417xx)
|
||||
// #include "stm32f417xx.h"
|
||||
// #elif defined(STM32F427xx)
|
||||
// #include "stm32f427xx.h"
|
||||
// #elif defined(STM32F437xx)
|
||||
// #include "stm32f437xx.h"
|
||||
// #elif defined(STM32F429xx)
|
||||
// #include "stm32f429xx.h"
|
||||
// #elif defined(STM32F439xx)
|
||||
// #include "stm32f439xx.h"
|
||||
// #elif defined(STM32F401xC)
|
||||
// #include "stm32f401xc.h"
|
||||
// #elif defined(STM32F401xE)
|
||||
// #include "stm32f401xe.h"
|
||||
// #elif defined(STM32F410Tx)
|
||||
// #include "stm32f410tx.h"
|
||||
// #elif defined(STM32F410Cx)
|
||||
// #include "stm32f410cx.h"
|
||||
// #elif defined(STM32F410Rx)
|
||||
// #include "stm32f410rx.h"
|
||||
// #elif defined(STM32F411xE)
|
||||
// #include "stm32f411xe.h"
|
||||
// #elif defined(STM32F446xx)
|
||||
// #include "stm32f446xx.h"
|
||||
// #elif defined(STM32F469xx)
|
||||
// #include "stm32f469xx.h"
|
||||
// #elif defined(STM32F479xx)
|
||||
// #include "stm32f479xx.h"
|
||||
// #elif defined(STM32F412Cx)
|
||||
// #include "stm32f412cx.h"
|
||||
// #elif defined(STM32F412Zx)
|
||||
// #include "stm32f412zx.h"
|
||||
// #elif defined(STM32F412Rx)
|
||||
// #include "stm32f412rx.h"
|
||||
// #elif defined(STM32F412Vx)
|
||||
// #include "stm32f412vx.h"
|
||||
#if defined(STM32F413xx)
|
||||
#include "stm32f413xx.h"
|
||||
#elif defined(STM32F423xx)
|
||||
#elif defined(STM32F423xx)
|
||||
#include "stm32f423xx.h"
|
||||
#else
|
||||
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
|
||||
|
|
|
@ -8,15 +8,6 @@
|
|||
// 5000 = 500 kbps
|
||||
#define can_speed_to_prescaler(x) (CAN_PCLK / CAN_QUANTA * 10U / (x))
|
||||
|
||||
#define GET_BUS(msg) (((msg)->RDTR >> 4) & 0xFF)
|
||||
#define GET_LEN(msg) ((msg)->RDTR & 0xF)
|
||||
#define GET_ADDR(msg) ((((msg)->RIR & 4) != 0) ? ((msg)->RIR >> 3) : ((msg)->RIR >> 21))
|
||||
#define GET_BYTE(msg, b) (((int)(b) > 3) ? (((msg)->RDHR >> (8U * ((unsigned int)(b) % 4U))) & 0xFFU) : (((msg)->RDLR >> (8U * (unsigned int)(b))) & 0xFFU))
|
||||
#define GET_BYTES_04(msg) ((msg)->RDLR)
|
||||
#define GET_BYTES_48(msg) ((msg)->RDHR)
|
||||
#define GET_FLAG(value, mask) (((__typeof__(mask))(value) & (mask)) == (mask))
|
||||
|
||||
#define CAN_INIT_TIMEOUT_MS 500U
|
||||
#define CAN_NAME_FROM_CANIF(CAN_DEV) (((CAN_DEV)==CAN1) ? "CAN1" : (((CAN_DEV) == CAN2) ? "CAN2" : "CAN3"))
|
||||
|
||||
void puts(const char *a);
|
|
@ -0,0 +1,28 @@
|
|||
bool flash_is_locked(void) {
|
||||
return (FLASH->CR & FLASH_CR_LOCK);
|
||||
}
|
||||
|
||||
void flash_unlock(void) {
|
||||
FLASH->KEYR = 0x45670123;
|
||||
FLASH->KEYR = 0xCDEF89AB;
|
||||
}
|
||||
|
||||
bool flash_erase_sector(uint8_t sector, bool unlocked) {
|
||||
// don't erase the bootloader(sector 0)
|
||||
if (sector != 0 && sector < 12 && unlocked) {
|
||||
FLASH->CR = (sector << 3) | FLASH_CR_SER;
|
||||
FLASH->CR |= FLASH_CR_STRT;
|
||||
while (FLASH->SR & FLASH_SR_BSY);
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
void flash_write_word(void *prog_ptr, uint32_t data) {
|
||||
uint32_t *pp = prog_ptr;
|
||||
FLASH->CR = FLASH_CR_PSIZE_1 | FLASH_CR_PG;
|
||||
*pp = data;
|
||||
while (FLASH->SR & FLASH_SR_BSY);
|
||||
}
|
||||
|
||||
void flush_write_buffer(void) { }
|
|
@ -42,6 +42,11 @@ void uart_rx_ring(uart_ring *q){
|
|||
}
|
||||
}
|
||||
|
||||
void uart_send_break(uart_ring *u) {
|
||||
while ((u->uart->CR1 & USART_CR1_SBK) != 0);
|
||||
u->uart->CR1 |= USART_CR1_SBK;
|
||||
}
|
||||
|
||||
// This function should be called on:
|
||||
// * Half-transfer DMA interrupt
|
||||
// * Full-transfer DMA interrupt
|
||||
|
|
|
@ -1,5 +1,18 @@
|
|||
void gpio_usb_init(void) {
|
||||
// A11,A12: USB
|
||||
set_gpio_alternate(GPIOA, 11, GPIO_AF10_OTG_FS);
|
||||
set_gpio_alternate(GPIOA, 12, GPIO_AF10_OTG_FS);
|
||||
GPIOA->OSPEEDR = GPIO_OSPEEDER_OSPEEDR11 | GPIO_OSPEEDER_OSPEEDR12;
|
||||
}
|
||||
|
||||
void gpio_usart2_init(void) {
|
||||
// A2,A3: USART 2 for debugging
|
||||
set_gpio_alternate(GPIOA, 2, GPIO_AF7_USART2);
|
||||
set_gpio_alternate(GPIOA, 3, GPIO_AF7_USART2);
|
||||
}
|
||||
|
||||
// Common GPIO initialization
|
||||
void common_init_gpio(void){
|
||||
void common_init_gpio(void) {
|
||||
// TODO: Is this block actually doing something???
|
||||
// pull low to hold ESP in reset??
|
||||
// enable OTG out tied to ground
|
||||
|
@ -12,10 +25,7 @@ void common_init_gpio(void){
|
|||
// C2: Voltage sense line
|
||||
set_gpio_mode(GPIOC, 2, MODE_ANALOG);
|
||||
|
||||
// A11,A12: USB
|
||||
set_gpio_alternate(GPIOA, 11, GPIO_AF10_OTG_FS);
|
||||
set_gpio_alternate(GPIOA, 12, GPIO_AF10_OTG_FS);
|
||||
GPIOA->OSPEEDR = GPIO_OSPEEDER_OSPEEDR11 | GPIO_OSPEEDER_OSPEEDR12;
|
||||
gpio_usb_init();
|
||||
|
||||
// A9,A10: USART 1 for talking to the GPS
|
||||
set_gpio_alternate(GPIOA, 9, GPIO_AF7_USART1);
|
||||
|
@ -31,8 +41,15 @@ void common_init_gpio(void){
|
|||
#endif
|
||||
}
|
||||
|
||||
void flasher_peripherals_init(void) {
|
||||
RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN;
|
||||
RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
|
||||
RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
|
||||
RCC->APB1ENR |= RCC_APB1ENR_USART2EN;
|
||||
}
|
||||
|
||||
// Peripheral initialization
|
||||
void peripherals_init(void){
|
||||
void peripherals_init(void) {
|
||||
// enable GPIOB, UART2, CAN, USB clock
|
||||
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
|
||||
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN;
|
||||
|
|
|
@ -67,8 +67,10 @@
|
|||
#include "stm32fx/lluart.h"
|
||||
#endif
|
||||
|
||||
#ifndef BOOTSTUB
|
||||
#include "stm32fx/llcan.h"
|
||||
#ifdef BOOTSTUB
|
||||
#include "stm32fx/llflash.h"
|
||||
#else
|
||||
#include "stm32fx/llbxcan.h"
|
||||
#endif
|
||||
|
||||
#if defined(PANDA) || defined(BOOTSTUB) || defined(PEDAL_USB)
|
||||
|
|
|
@ -35,7 +35,7 @@ ENTRY(Reset_Handler)
|
|||
/* Highest address of the user mode stack */
|
||||
enter_bootloader_mode = 0x2001FFFC;
|
||||
_estack = 0x2001FFFC; /* end of 128K RAM on AHB bus*/
|
||||
_app_start = 0x08004000; /* Reserve 16K for bootloader */
|
||||
_app_start = 0x08004000; /* Reserve Sector 0(16K) for bootloader */
|
||||
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0; /* required amount of heap */
|
||||
|
|
|
@ -0,0 +1,36 @@
|
|||
// ///////////////////////////////////////////////////////////// //
|
||||
// Hardware abstraction layer for all different supported boards //
|
||||
// ///////////////////////////////////////////////////////////// //
|
||||
#include "boards/board_declarations.h"
|
||||
#include "boards/unused_funcs.h"
|
||||
|
||||
// ///// Board definition and detection ///// //
|
||||
#include "drivers/harness.h"
|
||||
#include "drivers/fan.h"
|
||||
#include "stm32h7/llfan.h"
|
||||
#include "stm32h7/llrtc.h"
|
||||
#include "drivers/rtc.h"
|
||||
#include "boards/red.h"
|
||||
|
||||
uint8_t board_id(void) {
|
||||
return detect_with_pull(GPIOF, 7, PULL_UP) |
|
||||
(detect_with_pull(GPIOF, 8, PULL_UP) << 1U) |
|
||||
(detect_with_pull(GPIOF, 9, PULL_UP) << 2U) |
|
||||
(detect_with_pull(GPIOF, 10, PULL_UP) << 3U);
|
||||
}
|
||||
|
||||
void detect_board_type(void) {
|
||||
if(board_id() == 0U){
|
||||
hw_type = HW_TYPE_RED_PANDA;
|
||||
current_board = &board_red;
|
||||
} else {
|
||||
hw_type = HW_TYPE_UNKNOWN;
|
||||
puts("Hardware type is UNKNOWN!\n");
|
||||
}
|
||||
}
|
||||
|
||||
bool has_external_debug_serial = 0;
|
||||
void detect_external_debug_serial(void) {
|
||||
// detect if external serial debugging is present
|
||||
has_external_debug_serial = detect_with_pull(GPIOA, 3, PULL_DOWN);
|
||||
}
|
|
@ -0,0 +1,54 @@
|
|||
void clock_init(void) {
|
||||
//Set power mode to direct SMPS power supply(depends on the board layout)
|
||||
register_set(&(PWR->CR3), PWR_CR3_SMPSEN, 0xFU); // powered only by SMPS
|
||||
//Set VOS level to VOS0. (VOS3 to 170Mhz, VOS2 to 300Mhz, VOS1 to 400Mhz, VOS0 to 550Mhz)
|
||||
register_set(&(PWR->D3CR), PWR_D3CR_VOS_1, 0xC000U); //VOS2
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0);
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOS) != (PWR->D3CR & PWR_D3CR_VOS)); // check that VOS level was actually set
|
||||
// Configure Flash ACR register LATENCY and WRHIGHFREQ (VOS0 range!)
|
||||
register_set(&(FLASH->ACR), FLASH_ACR_LATENCY_2WS | 0x20U, 0x3FU); // VOS2, AXI 100MHz-150MHz
|
||||
// enable external oscillator HSE
|
||||
register_set_bits(&(RCC->CR), RCC_CR_HSEON);
|
||||
while ((RCC->CR & RCC_CR_HSERDY) == 0);
|
||||
// Specify the frequency source for PLL1, divider for DIVM1, divider for DIVM2 : HSE, 5, 5
|
||||
register_set(&(RCC->PLLCKSELR), RCC_PLLCKSELR_PLLSRC_HSE | RCC_PLLCKSELR_DIVM1_0 | RCC_PLLCKSELR_DIVM1_2 | RCC_PLLCKSELR_DIVM2_0 | RCC_PLLCKSELR_DIVM2_2, 0x3F3F3U);
|
||||
|
||||
// *** PLL1 start ***
|
||||
// Specify multiplier N and dividers P, Q, R for PLL1 : 48, 1, 5, 2
|
||||
register_set(&(RCC->PLL1DIVR), 0x104002FU, 0x7F7FFFFFU);
|
||||
// Specify the input and output frequency ranges, enable dividers for PLL1
|
||||
register_set(&(RCC->PLLCFGR), RCC_PLLCFGR_PLL1RGE_2 | RCC_PLLCFGR_DIVP1EN | RCC_PLLCFGR_DIVQ1EN | RCC_PLLCFGR_DIVR1EN, 0x7000CU);
|
||||
// Enable PLL1
|
||||
register_set_bits(&(RCC->CR), RCC_CR_PLL1ON);
|
||||
while((RCC->CR & RCC_CR_PLL1RDY) == 0);
|
||||
// *** PLL1 end ***
|
||||
|
||||
//////////////OTHER CLOCKS////////////////////
|
||||
// RCC HCLK Clock Source / RCC APB3 Clock Source / RCC SYS Clock Source
|
||||
register_set(&(RCC->D1CFGR), RCC_D1CFGR_HPRE_DIV2 | RCC_D1CFGR_D1PPRE_DIV2 | RCC_D1CFGR_D1CPRE_DIV1, 0xF7FU);
|
||||
// RCC APB1 Clock Source / RCC APB2 Clock Source
|
||||
register_set(&(RCC->D2CFGR), RCC_D2CFGR_D2PPRE1_DIV2 | RCC_D2CFGR_D2PPRE2_DIV2, 0x770U);
|
||||
// RCC APB4 Clock Source
|
||||
register_set(&(RCC->D3CFGR), RCC_D3CFGR_D3PPRE_DIV2, 0x70U);
|
||||
// PLL2P for ADC
|
||||
register_clear_bits(&(RCC->D3CFGR), RCC_D3CCIPR_ADCSEL);
|
||||
|
||||
// Set SysClock source to PLL
|
||||
register_set(&(RCC->CFGR), RCC_CFGR_SW_PLL1, 0x7U);
|
||||
while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL1);
|
||||
|
||||
// SYSCFG peripheral clock enable
|
||||
register_set_bits(&(RCC->AHB4ENR), RCC_APB4ENR_SYSCFGEN);
|
||||
//////////////END OTHER CLOCKS////////////////////
|
||||
|
||||
// Configure clock source for USB
|
||||
register_set(&(RCC->D2CCIP2R), RCC_D2CCIP2R_USBSEL_0, RCC_D2CCIP2R_USBSEL); //PLL1Q
|
||||
// Configure clock source for FDCAN
|
||||
register_set(&(RCC->D2CCIP1R), RCC_D2CCIP1R_FDCANSEL_0, RCC_D2CCIP1R_FDCANSEL); //PLL1Q
|
||||
// Configure clock source for ADC1,2,3
|
||||
register_set(&(RCC->D3CCIPR), RCC_D3CCIPR_ADCSEL_1, RCC_D3CCIPR_ADCSEL); //per_ck(currently HSE)
|
||||
//Enable the Clock Security System
|
||||
register_set_bits(&(RCC->CR), RCC_CR_CSSHSEON);
|
||||
//Enable Vdd33usb supply level detector
|
||||
register_set_bits(&(PWR->CR3), PWR_CR3_USB33DEN);
|
||||
}
|
|
@ -0,0 +1,284 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.1.0
|
||||
* @date 09. October 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6.6 LTM (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||
#include "cmsis_armclang_ltm.h"
|
||||
|
||||
/*
|
||||
* Arm Compiler above 6.10.1 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,40 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.3
|
||||
* @date 24. June 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,346 @@
|
|||
/******************************************************************************
|
||||
* @file mpu_armv8.h
|
||||
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
|
||||
* @version V5.1.0
|
||||
* @date 08. March 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */
|
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||
|
||||
/** \brief Attribute for normal memory (outer and inner)
|
||||
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||
*/
|
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes
|
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||
*/
|
||||
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
|
||||
|
||||
/** \brief Normal memory non-shareable */
|
||||
#define ARM_MPU_SH_NON (0U)
|
||||
|
||||
/** \brief Normal memory outer shareable */
|
||||
#define ARM_MPU_SH_OUTER (2U)
|
||||
|
||||
/** \brief Normal memory inner shareable */
|
||||
#define ARM_MPU_SH_INNER (3U)
|
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||
*/
|
||||
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
|
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||
* \param SH Defines the Shareability domain for this memory region.
|
||||
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||
((BASE & MPU_RBAR_BASE_Msk) | \
|
||||
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#if defined(MPU_RLAR_PXN_Pos)
|
||||
|
||||
/** \brief Region Limit Address Register with PXN value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
|
||||
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||
((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
|
||||
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||
{
|
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||
{
|
||||
const uint8_t reg = idx / 4U;
|
||||
const uint32_t pos = ((idx % 4U) * 8U);
|
||||
const uint32_t mask = 0xFFU << pos;
|
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||
return; // invalid index
|
||||
}
|
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||
}
|
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RLAR = 0U;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RBAR = rbar;
|
||||
mpu->RLAR = rlar;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
if (cnt == 1U) {
|
||||
mpu->RNR = rnr;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
} else {
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||
table += c;
|
||||
cnt -= c;
|
||||
rnrOffset = 0U;
|
||||
rnrBase += MPU_TYPE_RALIASES;
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,243 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS STM32H7xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
* is using in the C source code, usually in main.c. This file contains:
|
||||
* - Configuration section that allows to select:
|
||||
* - The STM32H7xx device used in the target application
|
||||
* - To use or not the peripheral’s drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral’s registers
|
||||
* rather than drivers API), this option is controlled by
|
||||
* "#define USE_HAL_DRIVER"
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32h7xx
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef STM32H7xx_H
|
||||
#define STM32H7xx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @addtogroup Library_configuration_section
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32 Family
|
||||
*/
|
||||
#if !defined (STM32H7)
|
||||
#define STM32H7
|
||||
#endif /* STM32H7 */
|
||||
|
||||
|
||||
/* Uncomment the line below according to the target STM32H7 device used in your
|
||||
application
|
||||
*/
|
||||
|
||||
/* #if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \
|
||||
!defined (STM32H745xx) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H757xx) && \
|
||||
!defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx) && !defined (STM32H7B0xxQ) && \
|
||||
!defined (STM32H735xx) && !defined (STM32H733xx) && !defined (STM32H730xx) && !defined (STM32H730xxQ) && !defined (STM32H725xx) && !defined (STM32H723xx) */
|
||||
/* #define STM32H742xx */ /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
|
||||
/* #define STM32H743xx */ /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */
|
||||
/* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
|
||||
/* #define STM32H750xx */ /*!< STM32H750V, STM32H750I, STM32H750X Devices */
|
||||
/* #define STM32H747xx */ /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */
|
||||
/* #define STM32H757xx */ /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */
|
||||
/* #define STM32H745xx */ /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices */
|
||||
/* #define STM32H755xx */ /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices */
|
||||
/* #define STM32H7B0xx */ /*!< STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ */
|
||||
/* #define STM32H7A3xx */ /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */
|
||||
/* #define STM32H7A3xxQ */ /*!< STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q */
|
||||
/* #define STM32H7B3xx */ /*!< STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6 */
|
||||
/* #define STM32H7B3xxQ */ /*!< STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q */
|
||||
/* #define STM32H735xx */ /*!< STM32H735AGI6, STM32H735IGK6, STM32H735RGV6, STM32H735VGT6, STM32H735VGY6, STM32H735ZGT6 Devices */
|
||||
/* #define STM32H733xx */ /*!< STM32H733VGH6, STM32H733VGT6, STM32H733ZGI6, STM32H733ZGT6, Devices */
|
||||
/* #define STM32H730xx */ /*!< STM32H730VBH6, STM32H730VBT6, STM32H730ZBT6, STM32H730ZBI6 Devices */
|
||||
/* #define STM32H730xxQ */ /*!< STM32H730IBT6Q, STM32H730ABI6Q, STM32H730IBK6Q Devices */
|
||||
/* #define STM32H725xx */ /*!< STM32H725AGI6, STM32H725IGK6, STM32H725IGT6, STM32H725RGV6, STM32H725VGT6, STM32H725VGY6, STM32H725ZGT6, STM32H725REV6, SM32H725VET6, STM32H725ZET6, STM32H725AEI6, STM32H725IET6, STM32H725IEK6 Devices */
|
||||
/* #define STM32H723xx */ /*!< STM32H723VGH6, STM32H723VGT6, STM32H723ZGI6, STM32H723ZGT6, STM32H723VET6, STM32H723VEH6, STM32H723ZET6, STM32H723ZEI6 Devices */
|
||||
/* #endif */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
devices, you can define the device in your toolchain compiler preprocessor.
|
||||
*/
|
||||
|
||||
#if defined(DUAL_CORE) && !defined(CORE_CM4) && !defined(CORE_CM7)
|
||||
#error "Dual core device, please select CORE_CM4 or CORE_CM7"
|
||||
#endif
|
||||
|
||||
#if !defined (USE_HAL_DRIVER)
|
||||
/**
|
||||
* @brief Comment the line below if you will not use the peripherals drivers.
|
||||
In this case, these drivers will not be included and the application code will
|
||||
be based on direct access to peripherals registers
|
||||
*/
|
||||
/*#define USE_HAL_DRIVER */
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V1.10.0
|
||||
*/
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x0A) /*!< [23:16] sub1 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
|
||||
|(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\
|
||||
|(__STM32H7xx_CMSIS_DEVICE_VERSION_RC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Device_Included
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32H743xx)
|
||||
#include "stm32h743xx.h"
|
||||
// #elif defined(STM32H753xx)
|
||||
// #include "stm32h753xx.h"
|
||||
// #elif defined(STM32H750xx)
|
||||
// #include "stm32h750xx.h"
|
||||
// #elif defined(STM32H742xx)
|
||||
// #include "stm32h742xx.h"
|
||||
// #elif defined(STM32H745xx)
|
||||
// #include "stm32h745xx.h"
|
||||
// #elif defined(STM32H755xx)
|
||||
// #include "stm32h755xx.h"
|
||||
// #elif defined(STM32H747xx)
|
||||
// #include "stm32h747xx.h"
|
||||
// #elif defined(STM32H757xx)
|
||||
// #include "stm32h757xx.h"
|
||||
// #elif defined(STM32H7B0xx)
|
||||
// #include "stm32h7b0xx.h"
|
||||
// #elif defined(STM32H7B0xxQ)
|
||||
// #include "stm32h7b0xxq.h"
|
||||
// #elif defined(STM32H7A3xx)
|
||||
// #include "stm32h7a3xx.h"
|
||||
// #elif defined(STM32H7B3xx)
|
||||
// #include "stm32h7b3xx.h"
|
||||
// #elif defined(STM32H7A3xxQ)
|
||||
// #include "stm32h7a3xxq.h"
|
||||
// #elif defined(STM32H7B3xxQ)
|
||||
// #include "stm32h7b3xxq.h"
|
||||
#elif defined(STM32H735xx)
|
||||
#include "stm32h735xx.h"
|
||||
// #elif defined(STM32H733xx)
|
||||
// #include "stm32h733xx.h"
|
||||
// #elif defined(STM32H730xx)
|
||||
// #include "stm32h730xx.h"
|
||||
// #elif defined(STM32H730xxQ)
|
||||
// #include "stm32h730xxq.h"
|
||||
#elif defined(STM32H725xx)
|
||||
#include "stm32h725xx.h"
|
||||
// #elif defined(STM32H723xx)
|
||||
// #include "stm32h723xx.h"
|
||||
#else
|
||||
#error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Exported_types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RESET = 0,
|
||||
SET = !RESET
|
||||
} FlagStatus, ITStatus;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DISABLE = 0,
|
||||
ENABLE = !DISABLE
|
||||
} FunctionalState;
|
||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
||||
|
||||
typedef enum
|
||||
{
|
||||
SUCCESS = 0,
|
||||
ERROR = !SUCCESS
|
||||
} ErrorStatus;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Exported_macros
|
||||
* @{
|
||||
*/
|
||||
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
||||
|
||||
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
||||
|
||||
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
||||
|
||||
#define CLEAR_REG(REG) ((REG) = (0x0))
|
||||
|
||||
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||
|
||||
#define READ_REG(REG) ((REG))
|
||||
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||
|
||||
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (USE_HAL_DRIVER)
|
||||
#include "stm32h7xx_hal.h"
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* STM32H7xx_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
@ -0,0 +1,221 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_def.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains HAL common defines, enumeration, macros and
|
||||
* structures definitions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_DEF
|
||||
#define STM32H7xx_HAL_DEF
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx.h"
|
||||
//#include "Legacy/stm32_hal_legacy.h"
|
||||
//#include <stddef.h>
|
||||
//#include <math.h>
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL Status structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_OK = 0x00,
|
||||
HAL_ERROR = 0x01,
|
||||
HAL_BUSY = 0x02,
|
||||
HAL_TIMEOUT = 0x03
|
||||
} HAL_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Lock structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_UNLOCKED = 0x00,
|
||||
HAL_LOCKED = 0x01
|
||||
} HAL_LockTypeDef;
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
|
||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
|
||||
|
||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
|
||||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
#define UNUSED(x) ((void)(x))
|
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__: specifies the Peripheral Handle.
|
||||
* @note This macro can be used for the following purpose:
|
||||
* - When the Handle is declared as local variable; before passing it as parameter
|
||||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
|
||||
* to set to 0 the Handle's "State" field.
|
||||
* Otherwise, "State" field may have any random value and the first time the function
|
||||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
|
||||
* (i.e. HAL_PPP_MspInit() will not be executed).
|
||||
* - When there is a need to reconfigure the low level hardware: instead of calling
|
||||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
|
||||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
|
||||
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
|
||||
|
||||
#if (USE_RTOS == 1)
|
||||
#error " USE_RTOS should be 0 in the current HAL release "
|
||||
#else
|
||||
#define __HAL_LOCK(__HANDLE__) \
|
||||
do{ \
|
||||
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
||||
{ \
|
||||
return HAL_BUSY; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Lock = HAL_LOCKED; \
|
||||
} \
|
||||
}while (0)
|
||||
|
||||
#define __HAL_UNLOCK(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
||||
}while (0)
|
||||
#endif /* USE_RTOS */
|
||||
|
||||
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((packed))
|
||||
#endif
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif /* __weak */
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((__packed__))
|
||||
#endif /* __packed */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#else
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#if defined (__CC_ARM) /* ARM Compiler V5 */
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __CC_ARM */
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */
|
||||
#if defined (__GNUC__) /* GNU Compiler */
|
||||
#define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32)))
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf
|
||||
#elif defined (__CC_ARM) /* ARM Compiler */
|
||||
#define ALIGN_32BYTES(buf) __align(32) buf
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief __RAM_FUNC definition
|
||||
*/
|
||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
||||
/* ARM Compiler V4/V5 and V6
|
||||
--------------------------
|
||||
RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module.
|
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
area of a module to a memory space in physical RAM.
|
||||
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
|
||||
dialog.
|
||||
*/
|
||||
#define __RAM_FUNC
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
RAM functions are defined using a specific toolchain keyword "__ramfunc".
|
||||
*/
|
||||
#define __RAM_FUNC __ramfunc
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
/* GNU Compiler
|
||||
------------
|
||||
RAM functions are defined using a specific toolchain attribute
|
||||
"__attribute__((section(".RamFunc")))".
|
||||
*/
|
||||
#define __RAM_FUNC __attribute__((section(".RamFunc")))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief __NOINLINE definition
|
||||
*/
|
||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
|
||||
/* ARM V4/V5 and V6 & GNU Compiler
|
||||
-------------------------------
|
||||
*/
|
||||
#define __NOINLINE __attribute__ ( (noinline) )
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
*/
|
||||
#define __NOINLINE _Pragma("optimize = no_inline")
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_DEF */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
@ -0,0 +1,489 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_gpio_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_GPIO_EX_H
|
||||
#define STM32H7xx_HAL_GPIO_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIOEx GPIOEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
#if defined (PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */
|
||||
#define GPIO_AF0_C1DSLEEP ((uint8_t)0x00) /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
#define GPIO_AF0_C1SLEEP ((uint8_t)0x00) /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
#define GPIO_AF0_D1PWREN ((uint8_t)0x00) /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
#define GPIO_AF0_D2PWREN ((uint8_t)0x00) /* Domain 2 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
#if defined(DUAL_CORE)
|
||||
#define GPIO_AF0_C2DSLEEP ((uint8_t)0x00) /* Cortex-M4 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
#define GPIO_AF0_C2SLEEP ((uint8_t)0x00) /* Cortex-M4 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
#endif /* DUAL_CORE */
|
||||
#endif /* PWR_CPUCR_PDDS_D2 */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
|
||||
#if defined(HRTIM1)
|
||||
#define GPIO_AF1_HRTIM1 ((uint8_t)0x01) /* HRTIM1 Alternate Function mapping */
|
||||
#endif /* HRTIM1 */
|
||||
#if defined(SAI4)
|
||||
#define GPIO_AF1_SAI4 ((uint8_t)0x01) /* SAI4 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */
|
||||
#endif /* SAI4 */
|
||||
#define GPIO_AF1_FMC ((uint8_t)0x01) /* FMC Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */
|
||||
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */
|
||||
#if defined(HRTIM1)
|
||||
#define GPIO_AF2_HRTIM1 ((uint8_t)0x02) /* HRTIM1 Alternate Function mapping */
|
||||
#endif /* HRTIM1 */
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */
|
||||
#if defined(FDCAN3)
|
||||
#define GPIO_AF2_FDCAN3 ((uint8_t)0x02) /* FDCAN3 Alternate Function mapping */
|
||||
#endif /*FDCAN3*/
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */
|
||||
#define GPIO_AF3_DFSDM1 ((uint8_t)0x03) /* DFSDM Alternate Function mapping */
|
||||
#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */
|
||||
#define GPIO_AF3_LPTIM4 ((uint8_t)0x03) /* LPTIM4 Alternate Function mapping */
|
||||
#define GPIO_AF3_LPTIM5 ((uint8_t)0x03) /* LPTIM5 Alternate Function mapping */
|
||||
#define GPIO_AF3_LPUART ((uint8_t)0x03) /* LPUART Alternate Function mapping */
|
||||
#if defined(OCTOSPIM)
|
||||
#define GPIO_AF3_OCTOSPIM_P1 ((uint8_t)0x03) /* OCTOSPI Manager Port 1 Alternate Function mapping */
|
||||
#define GPIO_AF3_OCTOSPIM_P2 ((uint8_t)0x03) /* OCTOSPI Manager Port 2 Alternate Function mapping */
|
||||
#endif /* OCTOSPIM */
|
||||
#if defined(HRTIM1)
|
||||
#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM1 Alternate Function mapping */
|
||||
#endif /* HRTIM1 */
|
||||
#define GPIO_AF3_LTDC ((uint8_t)0x03) /* LTDC Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
|
||||
#if defined(I2C5)
|
||||
#define GPIO_AF4_I2C5 ((uint8_t)0x04) /* I2C5 Alternate Function mapping */
|
||||
#endif /* I2C5*/
|
||||
#define GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
|
||||
#define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
|
||||
#if defined(USART10)
|
||||
#define GPIO_AF4_USART10 ((uint8_t)0x04) /* USART10 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */
|
||||
#endif /*USART10*/
|
||||
#define GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM Alternate Function mapping */
|
||||
#if defined(DFSDM2_BASE)
|
||||
#define GPIO_AF4_DFSDM2 ((uint8_t)0x04) /* DFSDM2 Alternate Function mapping */
|
||||
#endif /* DFSDM2_BASE */
|
||||
#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */
|
||||
#if defined(PSSI)
|
||||
#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */
|
||||
#endif /* PSSI */
|
||||
#if defined(OCTOSPIM)
|
||||
#define GPIO_AF4_OCTOSPIM_P1 ((uint8_t)0x04) /* OCTOSPI Manager Port 1 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */
|
||||
#endif /* OCTOSPIM */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
|
||||
#define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */
|
||||
#if defined(FDCAN3)
|
||||
#define GPIO_AF5_FDCAN3 ((uint8_t)0x05) /* FDCAN3 Alternate Function mapping */
|
||||
#endif /*FDCAN3*/
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
|
||||
#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
|
||||
#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */
|
||||
#if defined(I2C5)
|
||||
#define GPIO_AF6_I2C5 ((uint8_t)0x06) /* I2C5 Alternate Function mapping */
|
||||
#endif /* I2C5*/
|
||||
#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */
|
||||
#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */
|
||||
#if defined(DFSDM2_BASE)
|
||||
#define GPIO_AF6_DFSDM2 ((uint8_t)0x06) /* DFSDM2 Alternate Function mapping */
|
||||
#endif /* DFSDM2_BASE */
|
||||
#if defined(SAI3)
|
||||
#define GPIO_AF6_SAI3 ((uint8_t)0x06) /* SAI3 Alternate Function mapping */
|
||||
#endif /* SAI3 */
|
||||
#if defined(OCTOSPIM)
|
||||
#define GPIO_AF6_OCTOSPIM_P1 ((uint8_t)0x06) /* OCTOSPI Manager Port 1 Alternate Function mapping */
|
||||
#endif /* OCTOSPIM */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */
|
||||
#define GPIO_AF7_SPI6 ((uint8_t)0x07) /* SPI6 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */
|
||||
#define GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */
|
||||
#define GPIO_AF7_SDMMC1 ((uint8_t)0x07) /* SDMMC1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */
|
||||
#if defined(SAI2)
|
||||
#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
|
||||
#endif /*SAI2*/
|
||||
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
|
||||
#define GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */
|
||||
#define GPIO_AF8_LPUART ((uint8_t)0x08) /* LPUART Alternate Function mapping */
|
||||
#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */
|
||||
#if defined(SAI4)
|
||||
#define GPIO_AF8_SAI4 ((uint8_t)0x08) /* SAI4 Alternate Function mapping */
|
||||
#endif /* SAI4 */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
|
||||
#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF9_SDMMC2 ((uint8_t)0x09) /* SDMMC2 Alternate Function mapping */
|
||||
#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */
|
||||
#define GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */
|
||||
#define GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */
|
||||
#if defined(QUADSPI)
|
||||
#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */
|
||||
#endif /* QUADSPI */
|
||||
#if defined(SAI4)
|
||||
#define GPIO_AF9_SAI4 ((uint8_t)0x09) /* SAI4 Alternate Function mapping */
|
||||
#endif /* SAI4 */
|
||||
#if defined(OCTOSPIM)
|
||||
#define GPIO_AF9_OCTOSPIM_P1 ((uint8_t)0x09) /* OCTOSPI Manager Port 1 Alternate Function mapping */
|
||||
#define GPIO_AF9_OCTOSPIM_P2 ((uint8_t)0x09) /* OCTOSPI Manager Port 2 Alternate Function mapping */
|
||||
#endif /* OCTOSPIM */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#if defined(SAI2)
|
||||
#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */
|
||||
#endif /*SAI2*/
|
||||
#define GPIO_AF10_SDMMC2 ((uint8_t)0x0A) /* SDMMC2 Alternate Function mapping */
|
||||
#if defined(USB2_OTG_FS)
|
||||
#define GPIO_AF10_OTG2_FS ((uint8_t)0x0A) /* OTG2_FS Alternate Function mapping */
|
||||
#endif /*USB2_OTG_FS*/
|
||||
#define GPIO_AF10_COMP1 ((uint8_t)0x0A) /* COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF10_COMP2 ((uint8_t)0x0A) /* COMP2 Alternate Function mapping */
|
||||
#if defined(LTDC)
|
||||
#define GPIO_AF10_LTDC ((uint8_t)0x0A) /* LTDC Alternate Function mapping */
|
||||
#endif /*LTDC*/
|
||||
#define GPIO_AF10_CRS_SYNC ((uint8_t)0x0A) /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
#if defined(QUADSPI)
|
||||
#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */
|
||||
#endif /* QUADSPI */
|
||||
#if defined(SAI4)
|
||||
#define GPIO_AF10_SAI4 ((uint8_t)0x0A) /* SAI4 Alternate Function mapping */
|
||||
#endif /* SAI4 */
|
||||
#if !defined(USB2_OTG_FS)
|
||||
#define GPIO_AF10_OTG1_FS ((uint8_t)0x0A) /* OTG1_FS Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */
|
||||
#endif /* !USB2_OTG_FS */
|
||||
#define GPIO_AF10_OTG1_HS ((uint8_t)0x0A) /* OTG1_HS Alternate Function mapping */
|
||||
#if defined(OCTOSPIM)
|
||||
#define GPIO_AF10_OCTOSPIM_P1 ((uint8_t)0x0A) /* OCTOSPI Manager Port 1 Alternate Function mapping */
|
||||
#endif /* OCTOSPIM */
|
||||
#define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF10_FMC ((uint8_t)0x0A) /* FMC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_SWP ((uint8_t)0x0B) /* SWP Alternate Function mapping */
|
||||
#define GPIO_AF11_MDIOS ((uint8_t)0x0B) /* MDIOS Alternate Function mapping */
|
||||
#define GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */
|
||||
#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */
|
||||
#define GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM1 Alternate Function mapping */
|
||||
#define GPIO_AF11_COMP1 ((uint8_t)0x0B) /* COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF11_COMP2 ((uint8_t)0x0B) /* COMP2 Alternate Function mapping */
|
||||
#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF11_I2C4 ((uint8_t)0x0B) /* I2C4 Alternate Function mapping */
|
||||
#if defined(DFSDM2_BASE)
|
||||
#define GPIO_AF11_DFSDM2 ((uint8_t)0x0B) /* DFSDM2 Alternate Function mapping */
|
||||
#endif /* DFSDM2_BASE */
|
||||
#if defined(USART10)
|
||||
#define GPIO_AF11_USART10 ((uint8_t)0x0B) /* USART10 Alternate Function mapping */
|
||||
#endif /* USART10 */
|
||||
#if defined(UART9)
|
||||
#define GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */
|
||||
#endif /* UART9 */
|
||||
#if defined(ETH)
|
||||
#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */
|
||||
#endif /* ETH */
|
||||
#if defined(LTDC)
|
||||
#define GPIO_AF11_LTDC ((uint8_t)0x0B) /* LTDC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */
|
||||
#endif /*LTDC*/
|
||||
#if defined(OCTOSPIM)
|
||||
#define GPIO_AF11_OCTOSPIM_P1 ((uint8_t)0x0B) /* OCTOSPI Manager Port 1 Alternate Function mapping */
|
||||
#endif /* OCTOSPIM */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
|
||||
#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
|
||||
#define GPIO_AF12_MDIOS ((uint8_t)0x0C) /* MDIOS Alternate Function mapping */
|
||||
#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */
|
||||
#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF12_TIM8 ((uint8_t)0x0C) /* TIM8 Alternate Function mapping */
|
||||
#if defined(LTDC)
|
||||
#define GPIO_AF12_LTDC ((uint8_t)0x0C) /* LTDC Alternate Function mapping */
|
||||
#endif /*LTDC*/
|
||||
#if defined(USB2_OTG_FS)
|
||||
#define GPIO_AF12_OTG1_FS ((uint8_t)0x0C) /* OTG1_FS Alternate Function mapping */
|
||||
#endif /* USB2_OTG_FS */
|
||||
#if defined(OCTOSPIM)
|
||||
#define GPIO_AF12_OCTOSPIM_P1 ((uint8_t)0x0C) /* OCTOSPI Manager Port 1 Alternate Function mapping */
|
||||
#endif /* OCTOSPIM */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
|
||||
#define GPIO_AF13_COMP1 ((uint8_t)0x0D) /* COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF13_COMP2 ((uint8_t)0x0D) /* COMP2 Alternate Function mapping */
|
||||
#if defined(LTDC)
|
||||
#define GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */
|
||||
#endif /*LTDC*/
|
||||
#if defined(DSI)
|
||||
#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */
|
||||
#endif /* DSI */
|
||||
#if defined(PSSI)
|
||||
#define GPIO_AF13_PSSI ((uint8_t)0x0D) /* PSSI Alternate Function mapping */
|
||||
#endif /* PSSI */
|
||||
#define GPIO_AF13_TIM1 ((uint8_t)0x0D) /* TIM1 Alternate Function mapping */
|
||||
#if defined(TIM23)
|
||||
#define GPIO_AF13_TIM23 ((uint8_t)0x0D) /* TIM23 Alternate Function mapping */
|
||||
#endif /*TIM23*/
|
||||
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */
|
||||
#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */
|
||||
#if defined(TIM24)
|
||||
#define GPIO_AF14_TIM24 ((uint8_t)0x0E) /* TIM24 Alternate Function mapping */
|
||||
#endif /*TIM24*/
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief GPIO pin available on the platform
|
||||
*/
|
||||
/* Defines the available pins per GPIOs */
|
||||
#define GPIOA_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOB_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOC_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOD_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOE_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOF_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOG_PIN_AVAILABLE GPIO_PIN_All
|
||||
#if defined(GPIOI)
|
||||
#define GPIOI_PIN_AVAILABLE GPIO_PIN_All
|
||||
#endif /*GPIOI*/
|
||||
#if defined(GPIOI)
|
||||
#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All
|
||||
#else
|
||||
#define GPIOJ_PIN_AVAILABLE (GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 )
|
||||
#endif /* GPIOI */
|
||||
#define GPIOH_PIN_AVAILABLE GPIO_PIN_All
|
||||
#if defined(GPIOI)
|
||||
#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \
|
||||
GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
|
||||
#else
|
||||
#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 )
|
||||
#endif /* GPIOI */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
|
||||
* @{
|
||||
*/
|
||||
#if defined(GPIOI)
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\
|
||||
((__GPIOx__) == (GPIOB))? 1UL :\
|
||||
((__GPIOx__) == (GPIOC))? 2UL :\
|
||||
((__GPIOx__) == (GPIOD))? 3UL :\
|
||||
((__GPIOx__) == (GPIOE))? 4UL :\
|
||||
((__GPIOx__) == (GPIOF))? 5UL :\
|
||||
((__GPIOx__) == (GPIOG))? 6UL :\
|
||||
((__GPIOx__) == (GPIOH))? 7UL :\
|
||||
((__GPIOx__) == (GPIOI))? 8UL :\
|
||||
((__GPIOx__) == (GPIOJ))? 9UL : 10UL)
|
||||
#else
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\
|
||||
((__GPIOx__) == (GPIOB))? 1UL :\
|
||||
((__GPIOx__) == (GPIOC))? 2UL :\
|
||||
((__GPIOx__) == (GPIOD))? 3UL :\
|
||||
((__GPIOx__) == (GPIOE))? 4UL :\
|
||||
((__GPIOx__) == (GPIOF))? 5UL :\
|
||||
((__GPIOx__) == (GPIOG))? 6UL :\
|
||||
((__GPIOx__) == (GPIOH))? 7UL :\
|
||||
((__GPIOx__) == (GPIOJ))? 9UL : 10UL)
|
||||
#endif /* GPIOI */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_GPIO_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
@ -0,0 +1,105 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32h7xx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32h7xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define to prevent recursive inclusion
|
||||
*/
|
||||
#ifndef SYSTEM_STM32H7XX_H
|
||||
#define SYSTEM_STM32H7XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Exported_types
|
||||
* @{
|
||||
*/
|
||||
/* This variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock; /*!< System Domain1 Clock Frequency */
|
||||
extern uint32_t SystemD2Clock; /*!< System Domain2 Clock Frequency */
|
||||
extern const uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers table values */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_STM32H7XX_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
@ -0,0 +1,74 @@
|
|||
// ********************* Bare interrupt handlers *********************
|
||||
// Interrupts for STM32H7x5
|
||||
|
||||
void WWDG_IRQHandler(void) {handle_interrupt(WWDG_IRQn);}
|
||||
void PVD_AVD_IRQHandler(void) {handle_interrupt(PVD_AVD_IRQn);}
|
||||
void TAMP_STAMP_IRQHandler(void) {handle_interrupt(TAMP_STAMP_IRQn);}
|
||||
void RTC_WKUP_IRQHandler(void) {handle_interrupt(RTC_WKUP_IRQn);}
|
||||
void FLASH_IRQHandler(void) {handle_interrupt(FLASH_IRQn);}
|
||||
void RCC_IRQHandler(void) {handle_interrupt(RCC_IRQn);}
|
||||
void EXTI0_IRQHandler(void) {handle_interrupt(EXTI0_IRQn);}
|
||||
void EXTI1_IRQHandler(void) {handle_interrupt(EXTI1_IRQn);}
|
||||
void EXTI2_IRQHandler(void) {handle_interrupt(EXTI2_IRQn);}
|
||||
void EXTI3_IRQHandler(void) {handle_interrupt(EXTI3_IRQn);}
|
||||
void EXTI4_IRQHandler(void) {handle_interrupt(EXTI4_IRQn);}
|
||||
void DMA1_Stream0_IRQHandler(void) {handle_interrupt(DMA1_Stream0_IRQn);}
|
||||
void DMA1_Stream1_IRQHandler(void) {handle_interrupt(DMA1_Stream1_IRQn);}
|
||||
void DMA1_Stream2_IRQHandler(void) {handle_interrupt(DMA1_Stream2_IRQn);}
|
||||
void DMA1_Stream3_IRQHandler(void) {handle_interrupt(DMA1_Stream3_IRQn);}
|
||||
void DMA1_Stream4_IRQHandler(void) {handle_interrupt(DMA1_Stream4_IRQn);}
|
||||
void DMA1_Stream5_IRQHandler(void) {handle_interrupt(DMA1_Stream5_IRQn);}
|
||||
void DMA1_Stream6_IRQHandler(void) {handle_interrupt(DMA1_Stream6_IRQn);}
|
||||
void ADC_IRQHandler(void) {handle_interrupt(ADC_IRQn);}
|
||||
void EXTI9_5_IRQHandler(void) {handle_interrupt(EXTI9_5_IRQn);}
|
||||
void TIM1_BRK_IRQHandler(void) {handle_interrupt(TIM1_BRK_IRQn);}
|
||||
void TIM1_UP_TIM10_IRQHandler(void) {handle_interrupt(TIM1_UP_TIM10_IRQn);}
|
||||
void TIM1_TRG_COM_IRQHandler(void) {handle_interrupt(TIM1_TRG_COM_IRQn);}
|
||||
void TIM1_CC_IRQHandler(void) {handle_interrupt(TIM1_CC_IRQn);}
|
||||
void TIM2_IRQHandler(void) {handle_interrupt(TIM2_IRQn);}
|
||||
void TIM3_IRQHandler(void) {handle_interrupt(TIM3_IRQn);}
|
||||
void TIM4_IRQHandler(void) {handle_interrupt(TIM4_IRQn);}
|
||||
void I2C1_EV_IRQHandler(void) {handle_interrupt(I2C1_EV_IRQn);}
|
||||
void I2C1_ER_IRQHandler(void) {handle_interrupt(I2C1_ER_IRQn);}
|
||||
void I2C2_EV_IRQHandler(void) {handle_interrupt(I2C2_EV_IRQn);}
|
||||
void I2C2_ER_IRQHandler(void) {handle_interrupt(I2C2_ER_IRQn);}
|
||||
void SPI1_IRQHandler(void) {handle_interrupt(SPI1_IRQn);}
|
||||
void SPI2_IRQHandler(void) {handle_interrupt(SPI2_IRQn);}
|
||||
void USART1_IRQHandler(void) {handle_interrupt(USART1_IRQn);}
|
||||
void USART2_IRQHandler(void) {handle_interrupt(USART2_IRQn);}
|
||||
void USART3_IRQHandler(void) {handle_interrupt(USART3_IRQn);}
|
||||
void EXTI15_10_IRQHandler(void) {handle_interrupt(EXTI15_10_IRQn);}
|
||||
void RTC_Alarm_IRQHandler(void) {handle_interrupt(RTC_Alarm_IRQn);}
|
||||
void TIM8_BRK_TIM12_IRQHandler(void) {handle_interrupt(TIM8_BRK_TIM12_IRQn);}
|
||||
void TIM8_UP_TIM13_IRQHandler(void) {handle_interrupt(TIM8_UP_TIM13_IRQn);}
|
||||
void TIM8_TRG_COM_TIM14_IRQHandler(void) {handle_interrupt(TIM8_TRG_COM_TIM14_IRQn);}
|
||||
void TIM8_CC_IRQHandler(void) {handle_interrupt(TIM8_CC_IRQn);}
|
||||
void DMA1_Stream7_IRQHandler(void) {handle_interrupt(DMA1_Stream7_IRQn);}
|
||||
void TIM5_IRQHandler(void) {handle_interrupt(TIM5_IRQn);}
|
||||
void SPI3_IRQHandler(void) {handle_interrupt(SPI3_IRQn);}
|
||||
void UART4_IRQHandler(void) {handle_interrupt(UART4_IRQn);}
|
||||
void UART5_IRQHandler(void) {handle_interrupt(UART5_IRQn);}
|
||||
void TIM6_DAC_IRQHandler(void) {handle_interrupt(TIM6_DAC_IRQn);}
|
||||
void TIM7_IRQHandler(void) {handle_interrupt(TIM7_IRQn);}
|
||||
void DMA2_Stream0_IRQHandler(void) {handle_interrupt(DMA2_Stream0_IRQn);}
|
||||
void DMA2_Stream1_IRQHandler(void) {handle_interrupt(DMA2_Stream1_IRQn);}
|
||||
void DMA2_Stream2_IRQHandler(void) {handle_interrupt(DMA2_Stream2_IRQn);}
|
||||
void DMA2_Stream3_IRQHandler(void) {handle_interrupt(DMA2_Stream3_IRQn);}
|
||||
void DMA2_Stream4_IRQHandler(void) {handle_interrupt(DMA2_Stream4_IRQn);}
|
||||
void DMA2_Stream5_IRQHandler(void) {handle_interrupt(DMA2_Stream5_IRQn);}
|
||||
void DMA2_Stream6_IRQHandler(void) {handle_interrupt(DMA2_Stream6_IRQn);}
|
||||
void DMA2_Stream7_IRQHandler(void) {handle_interrupt(DMA2_Stream7_IRQn);}
|
||||
void USART6_IRQHandler(void) {handle_interrupt(USART6_IRQn);}
|
||||
void I2C3_EV_IRQHandler(void) {handle_interrupt(I2C3_EV_IRQn);}
|
||||
void I2C3_ER_IRQHandler(void) {handle_interrupt(I2C3_ER_IRQn);}
|
||||
void FDCAN1_IT0_IRQHandler(void) {handle_interrupt(FDCAN1_IT0_IRQn);}
|
||||
void FDCAN1_IT1_IRQHandler(void) {handle_interrupt(FDCAN1_IT1_IRQn);}
|
||||
void FDCAN2_IT0_IRQHandler(void) {handle_interrupt(FDCAN2_IT0_IRQn);}
|
||||
void FDCAN2_IT1_IRQHandler(void) {handle_interrupt(FDCAN2_IT1_IRQn);}
|
||||
void FDCAN3_IT0_IRQHandler(void) {handle_interrupt(FDCAN3_IT0_IRQn);}
|
||||
void FDCAN3_IT1_IRQHandler(void) {handle_interrupt(FDCAN3_IT1_IRQn);}
|
||||
void FDCAN_CAL_IRQHandler(void) {handle_interrupt(FDCAN_CAL_IRQn);}
|
||||
void OTG_HS_EP1_OUT_IRQHandler(void) {handle_interrupt(OTG_HS_EP1_OUT_IRQn);}
|
||||
void OTG_HS_EP1_IN_IRQHandler(void) {handle_interrupt(OTG_HS_EP1_IN_IRQn);}
|
||||
void OTG_HS_WKUP_IRQHandler(void) {handle_interrupt(OTG_HS_WKUP_IRQn);}
|
||||
void OTG_HS_IRQHandler(void) {handle_interrupt(OTG_HS_IRQn);}
|
|
@ -0,0 +1,48 @@
|
|||
// 5VOUT_S = ADC12_INP5
|
||||
// VOLT_S = ADC1_INP2
|
||||
#define ADCCHAN_VOLTAGE 2
|
||||
|
||||
void adc_init(void) {
|
||||
ADC1->CR &= ~(ADC_CR_DEEPPWD); //Reset deep-power-down mode
|
||||
ADC1->CR |= ADC_CR_ADVREGEN; // Enable ADC regulator
|
||||
while(!(ADC1->ISR & ADC_ISR_LDORDY));
|
||||
|
||||
ADC1->CR &= ~(ADC_CR_ADCALDIF); // Choose single-ended calibration
|
||||
ADC1->CR |= ADC_CR_ADCALLIN; // Lineriality calibration
|
||||
ADC1->CR |= ADC_CR_ADCAL; // Start calibrtation
|
||||
while((ADC1->CR & ADC_CR_ADCAL) != 0);
|
||||
|
||||
ADC1->ISR |= ADC_ISR_ADRDY;
|
||||
ADC1->CR |= ADC_CR_ADEN;
|
||||
while(!(ADC1->ISR & ADC_ISR_ADRDY));
|
||||
}
|
||||
|
||||
uint32_t adc_get(unsigned int channel) {
|
||||
|
||||
ADC1->SQR1 &= ~(ADC_SQR1_L);
|
||||
ADC1->SQR1 = (channel << 6U);
|
||||
|
||||
ADC1->SMPR1 = (0x7U << (channel * 3U) );
|
||||
ADC1->PCSEL_RES0 = (0x1U << channel);
|
||||
|
||||
ADC1->CR |= ADC_CR_ADSTART;
|
||||
while (!(ADC1->ISR & ADC_ISR_EOC));
|
||||
|
||||
uint16_t res = ADC1->DR;
|
||||
|
||||
while (!(ADC1->ISR & ADC_ISR_EOS));
|
||||
ADC1->ISR |= ADC_ISR_EOS;
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
uint32_t adc_get_voltage(void) {
|
||||
// REVC has a 10, 1 (1/11) voltage divider
|
||||
// Here is the calculation for the scale (s)
|
||||
// ADCV = VIN_S * (1/11) * (65535/3.3)
|
||||
// RETVAL = ADCV * s = VIN_S*1000
|
||||
// s = 1000/((65535/3.3)*(1/11)) = 0.553902494
|
||||
|
||||
// Avoid needing floating point math, so output in mV
|
||||
return (adc_get(ADCCHAN_VOLTAGE) * 5539U) / 10000U;
|
||||
}
|
|
@ -0,0 +1,2 @@
|
|||
void EXTI2_IRQ_Handler(void) { }
|
||||
void fan_init(void){ }
|
|
@ -0,0 +1,210 @@
|
|||
#define FDCAN_MESSAGE_RAM_SIZE 0x2800UL
|
||||
#define FDCAN_START_ADDRESS 0x4000AC00UL
|
||||
#define FDCAN_OFFSET 3412UL // bytes for each FDCAN module
|
||||
#define FDCAN_OFFSET_W 853UL // words for each FDCAN module
|
||||
#define FDCAN_END_ADDRESS 0x4000D3FCUL // Message RAM has a width of 4 Bytes
|
||||
|
||||
// With this settings we can go up to 6Mbit/s
|
||||
#define CAN_SYNC_JW 1U // 1 to 4
|
||||
#define CAN_PHASE_SEG1 6U // =(PROP_SEG + PHASE_SEG1) , 1 to 16
|
||||
#define CAN_PHASE_SEG2 1U // 1 to 8
|
||||
#define CAN_PCLK 48000U // Sourced from PLL1Q
|
||||
#define CAN_QUANTA (1U + CAN_PHASE_SEG1 + CAN_PHASE_SEG2)
|
||||
// Valid speeds in kbps and their prescalers:
|
||||
// 10=600, 20=300, 50=120, 83.333=72, 100=60, 125=48, 250=24, 500=12, 1000=6, 2000=3, 3000=2, 6000=1
|
||||
#define can_speed_to_prescaler(x) (CAN_PCLK / CAN_QUANTA * 10U / (x))
|
||||
|
||||
// RX FIFO 0
|
||||
#define FDCAN_RX_FIFO_0_EL_CNT 32UL
|
||||
#define FDCAN_RX_FIFO_0_HEAD_SIZE 8UL // bytes
|
||||
#define FDCAN_RX_FIFO_0_DATA_SIZE 8UL // bytes
|
||||
#define FDCAN_RX_FIFO_0_EL_SIZE (FDCAN_RX_FIFO_0_HEAD_SIZE + FDCAN_RX_FIFO_0_DATA_SIZE)
|
||||
#define FDCAN_RX_FIFO_0_EL_W_SIZE (FDCAN_RX_FIFO_0_EL_SIZE / 4UL)
|
||||
#define FDCAN_RX_FIFO_0_OFFSET 0UL
|
||||
|
||||
// TX FIFO
|
||||
#define FDCAN_TX_FIFO_EL_CNT 32UL
|
||||
#define FDCAN_TX_FIFO_HEAD_SIZE 8UL // bytes
|
||||
#define FDCAN_TX_FIFO_DATA_SIZE 8UL // bytes
|
||||
#define FDCAN_TX_FIFO_EL_SIZE (FDCAN_TX_FIFO_HEAD_SIZE + FDCAN_TX_FIFO_DATA_SIZE)
|
||||
#define FDCAN_TX_FIFO_EL_W_SIZE (FDCAN_TX_FIFO_EL_SIZE / 4UL)
|
||||
#define FDCAN_TX_FIFO_OFFSET (FDCAN_RX_FIFO_0_OFFSET + (FDCAN_RX_FIFO_0_EL_CNT * FDCAN_RX_FIFO_0_EL_W_SIZE))
|
||||
|
||||
#define CAN_NAME_FROM_CANIF(CAN_DEV) (((CAN_DEV)==FDCAN1) ? "FDCAN1" : (((CAN_DEV) == FDCAN2) ? "FDCAN2" : "FDCAN3"))
|
||||
#define CAN_NUM_FROM_CANIF(CAN_DEV) (((CAN_DEV)==FDCAN1) ? 0UL : (((CAN_DEV) == FDCAN2) ? 1UL : 2UL))
|
||||
|
||||
// For backwards compatibility with safety code
|
||||
typedef struct {
|
||||
__IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
|
||||
__IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
|
||||
__IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
|
||||
__IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
|
||||
} CAN_FIFOMailBox_TypeDef;
|
||||
|
||||
void puts(const char *a);
|
||||
|
||||
bool fdcan_request_init(FDCAN_GlobalTypeDef *CANx) {
|
||||
bool ret = true;
|
||||
// Exit from sleep mode
|
||||
CANx->CCCR &= ~(FDCAN_CCCR_CSR);
|
||||
while ((CANx->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA);
|
||||
|
||||
// Request init
|
||||
uint32_t timeout_counter = 0U;
|
||||
CANx->CCCR |= FDCAN_CCCR_INIT;
|
||||
while ((CANx->CCCR & FDCAN_CCCR_INIT) == 0) {
|
||||
// Delay for about 1ms
|
||||
delay(10000);
|
||||
timeout_counter++;
|
||||
|
||||
if (timeout_counter >= CAN_INIT_TIMEOUT_MS){
|
||||
ret = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool fdcan_exit_init(FDCAN_GlobalTypeDef *CANx) {
|
||||
bool ret = true;
|
||||
|
||||
CANx->CCCR &= ~(FDCAN_CCCR_INIT);
|
||||
uint32_t timeout_counter = 0U;
|
||||
while ((CANx->CCCR & FDCAN_CCCR_INIT) != 0) {
|
||||
// Delay for about 1ms
|
||||
delay(10000);
|
||||
timeout_counter++;
|
||||
|
||||
if (timeout_counter >= CAN_INIT_TIMEOUT_MS) {
|
||||
ret = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool llcan_set_speed(FDCAN_GlobalTypeDef *CANx, uint32_t speed, uint32_t data_speed, bool loopback, bool silent) {
|
||||
bool ret = fdcan_request_init(CANx);
|
||||
|
||||
if (ret) {
|
||||
// Enable config change
|
||||
CANx->CCCR |= FDCAN_CCCR_CCE;
|
||||
|
||||
//Reset operation mode to Normal
|
||||
CANx->CCCR &= ~(FDCAN_CCCR_TEST);
|
||||
CANx->TEST &= ~(FDCAN_TEST_LBCK);
|
||||
CANx->CCCR &= ~(FDCAN_CCCR_MON);
|
||||
CANx->CCCR &= ~(FDCAN_CCCR_ASM);
|
||||
|
||||
// Set the nominal bit timing register
|
||||
CANx->NBTP = ((CAN_SYNC_JW-1U)<<FDCAN_NBTP_NSJW_Pos) | ((CAN_PHASE_SEG1-1U)<<FDCAN_NBTP_NTSEG1_Pos) | ((CAN_PHASE_SEG2-1U)<<FDCAN_NBTP_NTSEG2_Pos) | ((can_speed_to_prescaler(speed)-1U)<<FDCAN_NBTP_NBRP_Pos);
|
||||
// Set the data bit timing register
|
||||
CANx->DBTP = ((CAN_SYNC_JW-1U)<<FDCAN_DBTP_DSJW_Pos) | ((CAN_PHASE_SEG1-1U)<<FDCAN_DBTP_DTSEG1_Pos) | ((CAN_PHASE_SEG2-1U)<<FDCAN_DBTP_DTSEG2_Pos) | ((can_speed_to_prescaler(data_speed)-1U)<<FDCAN_DBTP_DBRP_Pos);
|
||||
// Silent loopback is known as internal loopback in the docs
|
||||
if (loopback) {
|
||||
CANx->CCCR |= FDCAN_CCCR_TEST;
|
||||
CANx->TEST |= FDCAN_TEST_LBCK;
|
||||
CANx->CCCR |= FDCAN_CCCR_MON;
|
||||
}
|
||||
// Silent is known as bus monitoring in the docs
|
||||
if (silent) {
|
||||
CANx->CCCR |= FDCAN_CCCR_MON;
|
||||
}
|
||||
ret = fdcan_exit_init(CANx);
|
||||
if (!ret) {
|
||||
puts(CAN_NAME_FROM_CANIF(CANx)); puts(" set_speed timed out! (2)\n");
|
||||
}
|
||||
} else {
|
||||
puts(CAN_NAME_FROM_CANIF(CANx)); puts(" set_speed timed out! (1)\n");
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool llcan_init(FDCAN_GlobalTypeDef *CANx) {
|
||||
uint32_t can_number = CAN_NUM_FROM_CANIF(CANx);
|
||||
bool ret = fdcan_request_init(CANx);
|
||||
|
||||
if (ret) {
|
||||
// Enable config change
|
||||
CANx->CCCR |= FDCAN_CCCR_CCE;
|
||||
// Enable automatic retransmission
|
||||
CANx->CCCR &= ~(FDCAN_CCCR_DAR);
|
||||
// Enable transmission pause feature
|
||||
CANx->CCCR |= FDCAN_CCCR_TXP;
|
||||
// Disable protocol exception handling
|
||||
CANx->CCCR |= FDCAN_CCCR_PXHD;
|
||||
// FD with BRS
|
||||
CANx->CCCR |= (FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE);
|
||||
|
||||
// Set TX mode to FIFO
|
||||
CANx->TXBC &= ~(FDCAN_TXBC_TFQM);
|
||||
// Configure TX element size (for now 8 bytes, no need to change)
|
||||
//CANx->TXESC |= 0x000U;
|
||||
//Configure RX FIFO0, FIFO1, RX buffer element sizes (no need for now, using classic 8 bytes)
|
||||
register_set(&(CANx->RXESC), 0x0U, (FDCAN_RXESC_F0DS | FDCAN_RXESC_F1DS | FDCAN_RXESC_RBDS));
|
||||
// Disable filtering, accept all valid frames received
|
||||
CANx->XIDFC &= ~(FDCAN_XIDFC_LSE); // No extended filters
|
||||
CANx->SIDFC &= ~(FDCAN_SIDFC_LSS); // No standard filters
|
||||
CANx->GFC &= ~(FDCAN_GFC_RRFE); // Accept extended remote frames
|
||||
CANx->GFC &= ~(FDCAN_GFC_RRFS); // Accept standard remote frames
|
||||
CANx->GFC &= ~(FDCAN_GFC_ANFE); // Accept extended frames to FIFO 0
|
||||
CANx->GFC &= ~(FDCAN_GFC_ANFS); // Accept standard frames to FIFO 0
|
||||
|
||||
uint32_t RxFIFO0SA = FDCAN_START_ADDRESS + (can_number * FDCAN_OFFSET);
|
||||
uint32_t TxFIFOSA = RxFIFO0SA + (FDCAN_RX_FIFO_0_EL_CNT * FDCAN_RX_FIFO_0_EL_SIZE);
|
||||
|
||||
// RX FIFO 0
|
||||
CANx->RXF0C = (FDCAN_RX_FIFO_0_OFFSET + (can_number * FDCAN_OFFSET_W)) << FDCAN_RXF0C_F0SA_Pos;
|
||||
CANx->RXF0C |= FDCAN_RX_FIFO_0_EL_CNT << FDCAN_RXF0C_F0S_Pos;
|
||||
// RX FIFO 0 switch to non-blocking (overwrite) mode
|
||||
CANx->RXF0C |= FDCAN_RXF0C_F0OM;
|
||||
|
||||
// TX FIFO (mode set earlier)
|
||||
CANx->TXBC = (FDCAN_TX_FIFO_OFFSET + (can_number * FDCAN_OFFSET_W)) << FDCAN_TXBC_TBSA_Pos;
|
||||
CANx->TXBC |= FDCAN_TX_FIFO_EL_CNT << FDCAN_TXBC_TFQS_Pos;
|
||||
|
||||
// Flush allocated RAM
|
||||
uint32_t EndAddress = TxFIFOSA + (FDCAN_TX_FIFO_EL_CNT * FDCAN_TX_FIFO_EL_SIZE);
|
||||
for (uint32_t RAMcounter = RxFIFO0SA; RAMcounter < EndAddress; RAMcounter += 4U) {
|
||||
*(uint32_t *)(RAMcounter) = 0x00000000;
|
||||
}
|
||||
|
||||
// Enable both interrupts for each module
|
||||
CANx->ILE = (FDCAN_ILE_EINT0 | FDCAN_ILE_EINT1);
|
||||
|
||||
CANx->IE &= 0x0U; // Reset all interrupts
|
||||
// Messages for INT0
|
||||
CANx->IE |= FDCAN_IE_RF0NE; // Rx FIFO 0 new message
|
||||
|
||||
// Messages for INT1 (Only TFE works??)
|
||||
CANx->ILS |= FDCAN_ILS_TFEL;
|
||||
CANx->IE |= FDCAN_IE_TFEE; // Tx FIFO empty
|
||||
|
||||
ret = fdcan_exit_init(CANx);
|
||||
if(!ret) {
|
||||
puts(CAN_NAME_FROM_CANIF(CANx)); puts(" llcan_init timed out (2)!\n");
|
||||
}
|
||||
|
||||
if (CANx == FDCAN1) {
|
||||
NVIC_EnableIRQ(FDCAN1_IT0_IRQn);
|
||||
NVIC_EnableIRQ(FDCAN1_IT1_IRQn);
|
||||
} else if (CANx == FDCAN2) {
|
||||
NVIC_EnableIRQ(FDCAN2_IT0_IRQn);
|
||||
NVIC_EnableIRQ(FDCAN2_IT1_IRQn);
|
||||
} else if (CANx == FDCAN3) {
|
||||
NVIC_EnableIRQ(FDCAN3_IT0_IRQn);
|
||||
NVIC_EnableIRQ(FDCAN3_IT1_IRQn);
|
||||
} else {
|
||||
puts("Invalid CAN: initialization failed\n");
|
||||
}
|
||||
|
||||
} else {
|
||||
puts(CAN_NAME_FROM_CANIF(CANx)); puts(" llcan_init timed out (1)!\n");
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
void llcan_clear_send(FDCAN_GlobalTypeDef *CANx) {
|
||||
// From H7 datasheet: Transmit cancellation is not intended for Tx FIFO operation.
|
||||
UNUSED(CANx);
|
||||
}
|
|
@ -0,0 +1,33 @@
|
|||
bool flash_is_locked(void) {
|
||||
return (FLASH->CR1 & FLASH_CR_LOCK);
|
||||
}
|
||||
|
||||
void flash_unlock(void) {
|
||||
FLASH->KEYR1 = 0x45670123;
|
||||
FLASH->KEYR1 = 0xCDEF89AB;
|
||||
}
|
||||
|
||||
bool flash_erase_sector(uint8_t sector, bool unlocked) {
|
||||
// don't erase the bootloader(sector 0)
|
||||
if (sector != 0 && sector < 8 && unlocked) {
|
||||
FLASH->CR1 = (sector << 8) | FLASH_CR_SER;
|
||||
FLASH->CR1 |= FLASH_CR_START;
|
||||
while (FLASH->SR1 & FLASH_SR_QW);
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
void flash_write_word(void *prog_ptr, uint32_t data) {
|
||||
uint32_t *pp = prog_ptr;
|
||||
FLASH->CR1 |= FLASH_CR_PG;
|
||||
*pp = data;
|
||||
while (FLASH->SR1 & FLASH_SR_QW);
|
||||
}
|
||||
|
||||
void flush_write_buffer(void) {
|
||||
if (FLASH->SR1 & FLASH_SR_WBNE) {
|
||||
FLASH->CR1 |= FLASH_CR_FW;
|
||||
while (FLASH->SR1 & FLASH_CR_FW);
|
||||
}
|
||||
}
|
|
@ -0,0 +1,9 @@
|
|||
#define RCC_BDCR_MASK (RCC_BDCR_RTCEN | RCC_BDCR_RTCSEL | RCC_BDCR_LSEDRV | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)
|
||||
|
||||
void enable_bdomain_protection(void) {
|
||||
register_clear_bits(&(PWR->CR1), PWR_CR1_DBP);
|
||||
}
|
||||
|
||||
void disable_bdomain_protection(void) {
|
||||
register_set_bits(&(PWR->CR1), PWR_CR1_DBP);
|
||||
}
|
|
@ -0,0 +1,5 @@
|
|||
void uart_init(uart_ring *q, int baud) { UNUSED(q); UNUSED(baud); }
|
||||
void uart_set_baud(USART_TypeDef *u, unsigned int baud) { UNUSED(u); UNUSED(baud); }
|
||||
void dma_pointer_handler(uart_ring *q, uint32_t dma_ndtr) { UNUSED(q); UNUSED(dma_ndtr); }
|
||||
void uart_rx_ring(uart_ring *q) { UNUSED(q); }
|
||||
void uart_tx_ring(uart_ring *q) { UNUSED(q); }
|
|
@ -0,0 +1,98 @@
|
|||
typedef struct
|
||||
{
|
||||
__IO uint32_t HPRT;
|
||||
}
|
||||
USB_OTG_HostPortTypeDef;
|
||||
|
||||
USB_OTG_GlobalTypeDef *USBx = USB_OTG_HS;
|
||||
|
||||
#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t)USBx + USB_OTG_HOST_BASE))
|
||||
#define USBx_HOST_PORT ((USB_OTG_HostPortTypeDef *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE))
|
||||
#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)((uint32_t)USBx + USB_OTG_DEVICE_BASE))
|
||||
#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
|
||||
#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
|
||||
#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
|
||||
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
|
||||
|
||||
#define USBD_FS_TRDT_VALUE 6U
|
||||
#define USB_OTG_SPEED_FULL 3U
|
||||
#define DCFG_FRAME_INTERVAL_80 0U
|
||||
|
||||
|
||||
void usb_irqhandler(void);
|
||||
|
||||
void OTG_HS_IRQ_Handler(void) {
|
||||
NVIC_DisableIRQ(OTG_HS_IRQn);
|
||||
usb_irqhandler();
|
||||
NVIC_EnableIRQ(OTG_HS_IRQn);
|
||||
}
|
||||
|
||||
void usb_init(void) {
|
||||
REGISTER_INTERRUPT(OTG_HS_IRQn, OTG_HS_IRQ_Handler, 1500000U, FAULT_INTERRUPT_RATE_USB) // TODO: Find out a better rate limit for USB. Now it's the 1.5MB/s rate
|
||||
|
||||
// Disable global interrupt
|
||||
USBx->GAHBCFG &= ~(USB_OTG_GAHBCFG_GINT);
|
||||
// Select FS Embedded PHY
|
||||
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
|
||||
// Force device mode
|
||||
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
|
||||
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
|
||||
delay(250000); // Wait for about 25ms (explicitly stated in H7 ref manual)
|
||||
// Wait for AHB master IDLE state.
|
||||
while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0);
|
||||
// Core Soft Reset
|
||||
USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
|
||||
while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
|
||||
// Activate the USB Transceiver
|
||||
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
|
||||
|
||||
for (uint8_t i = 0U; i < 15U; i++) {
|
||||
USBx->DIEPTXF[i] = 0U;
|
||||
}
|
||||
|
||||
// VBUS Sensing setup
|
||||
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
|
||||
// Deactivate VBUS Sensing B
|
||||
USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN);
|
||||
// B-peripheral session valid override enable
|
||||
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
|
||||
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
|
||||
// Restart the Phy Clock
|
||||
USBx_PCGCCTL = 0U;
|
||||
// Device mode configuration
|
||||
USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
|
||||
USBx_DEVICE->DCFG |= USB_OTG_SPEED_FULL | USB_OTG_DCFG_NZLSOHSK;
|
||||
|
||||
// Flush FIFOs
|
||||
USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (0x10U << 6));
|
||||
while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
|
||||
|
||||
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
|
||||
while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
|
||||
|
||||
// Clear all pending Device Interrupts
|
||||
USBx_DEVICE->DIEPMSK = 0U;
|
||||
USBx_DEVICE->DOEPMSK = 0U;
|
||||
USBx_DEVICE->DAINTMSK = 0U;
|
||||
USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
|
||||
|
||||
// Disable all interrupts.
|
||||
USBx->GINTMSK = 0U;
|
||||
// Clear any pending interrupts
|
||||
USBx->GINTSTS = 0xBFFFFFFFU;
|
||||
// Enable interrupts matching to the Device mode ONLY
|
||||
USBx->GINTMSK = USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_OTGINT |
|
||||
USB_OTG_GINTMSK_RXFLVLM | USB_OTG_GINTMSK_GONAKEFFM | USB_OTG_GINTMSK_GINAKEFFM |
|
||||
USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT | USB_OTG_GINTMSK_USBSUSPM |
|
||||
USB_OTG_GINTMSK_CIDSCHGM | USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_MMISM | USB_OTG_GINTMSK_EOPFM;
|
||||
|
||||
// Set USB Turnaround time
|
||||
USBx->GUSBCFG |= ((USBD_FS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);
|
||||
// Enables the controller's Global Int in the AHB Config reg
|
||||
USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
|
||||
// Soft disconnect disable:
|
||||
USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_SDIS);
|
||||
|
||||
// enable the IRQ
|
||||
NVIC_EnableIRQ(OTG_HS_IRQn);
|
||||
}
|
|
@ -0,0 +1,123 @@
|
|||
void gpio_usb_init(void) {
|
||||
// A11,A12: USB:
|
||||
set_gpio_alternate(GPIOA, 11, GPIO_AF10_OTG1_FS);
|
||||
set_gpio_alternate(GPIOA, 12, GPIO_AF10_OTG1_FS);
|
||||
GPIOA->OSPEEDR = GPIO_OSPEEDR_OSPEED11 | GPIO_OSPEEDR_OSPEED12;
|
||||
}
|
||||
|
||||
void gpio_usart2_init(void) {
|
||||
// A2,A3: USART 2 for debugging
|
||||
set_gpio_alternate(GPIOA, 2, GPIO_AF7_USART2);
|
||||
set_gpio_alternate(GPIOA, 3, GPIO_AF7_USART2);
|
||||
}
|
||||
|
||||
// Common GPIO initialization
|
||||
void common_init_gpio(void) {
|
||||
/// E2,E3,E4: RGB LED
|
||||
set_gpio_pullup(GPIOE, 2, PULL_NONE);
|
||||
set_gpio_mode(GPIOE, 2, MODE_OUTPUT);
|
||||
|
||||
set_gpio_pullup(GPIOE, 3, PULL_NONE);
|
||||
set_gpio_mode(GPIOE, 3, MODE_OUTPUT);
|
||||
|
||||
set_gpio_pullup(GPIOE, 4, PULL_NONE);
|
||||
set_gpio_mode(GPIOE, 4, MODE_OUTPUT);
|
||||
|
||||
// F7,F8,F9,F10: BOARD ID
|
||||
set_gpio_pullup(GPIOF, 7, PULL_NONE);
|
||||
set_gpio_mode(GPIOF, 7, MODE_INPUT);
|
||||
|
||||
set_gpio_pullup(GPIOF, 8, PULL_NONE);
|
||||
set_gpio_mode(GPIOF, 8, MODE_INPUT);
|
||||
|
||||
set_gpio_pullup(GPIOF, 9, PULL_NONE);
|
||||
set_gpio_mode(GPIOF, 9, MODE_INPUT);
|
||||
|
||||
set_gpio_pullup(GPIOF, 10, PULL_NONE);
|
||||
set_gpio_mode(GPIOF, 10, MODE_INPUT);
|
||||
|
||||
// G11,B3,D7,B4: transceiver enable
|
||||
set_gpio_pullup(GPIOG, 11, PULL_NONE);
|
||||
set_gpio_mode(GPIOG, 11, MODE_OUTPUT);
|
||||
|
||||
// Speed was set to high by default after reset, changing to low
|
||||
GPIOB->OSPEEDR = GPIO_OSPEEDR_OSPEED3;
|
||||
set_gpio_pullup(GPIOB, 3, PULL_NONE);
|
||||
set_gpio_mode(GPIOB, 3, MODE_OUTPUT);
|
||||
|
||||
set_gpio_pullup(GPIOD, 7, PULL_NONE);
|
||||
set_gpio_mode(GPIOD, 7, MODE_OUTPUT);
|
||||
|
||||
set_gpio_pullup(GPIOB, 4, PULL_NONE);
|
||||
set_gpio_mode(GPIOB, 4, MODE_OUTPUT);
|
||||
|
||||
// B14: usb load switch
|
||||
set_gpio_pullup(GPIOB, 14, PULL_NONE);
|
||||
set_gpio_mode(GPIOB, 14, MODE_OUTPUT);
|
||||
|
||||
//B1,F11 5VOUT_S, VOLT_S
|
||||
set_gpio_pullup(GPIOB, 1, PULL_NONE);
|
||||
set_gpio_mode(GPIOB, 1, MODE_ANALOG);
|
||||
|
||||
set_gpio_pullup(GPIOF, 11, PULL_NONE);
|
||||
set_gpio_mode(GPIOF, 11, MODE_ANALOG);
|
||||
|
||||
gpio_usb_init();
|
||||
|
||||
// B8,B9: FDCAN1
|
||||
set_gpio_pullup(GPIOB, 8, PULL_NONE);
|
||||
set_gpio_alternate(GPIOB, 8, GPIO_AF9_FDCAN1);
|
||||
|
||||
set_gpio_pullup(GPIOB, 9, PULL_NONE);
|
||||
set_gpio_alternate(GPIOB, 9, GPIO_AF9_FDCAN1);
|
||||
|
||||
// B5,B6 (mplex to B12,B13): FDCAN2
|
||||
set_gpio_pullup(GPIOB, 12, PULL_NONE);
|
||||
set_gpio_pullup(GPIOB, 13, PULL_NONE);
|
||||
|
||||
set_gpio_pullup(GPIOB, 5, PULL_NONE);
|
||||
set_gpio_alternate(GPIOB, 5, GPIO_AF9_FDCAN2);
|
||||
|
||||
set_gpio_pullup(GPIOB, 6, PULL_NONE);
|
||||
set_gpio_alternate(GPIOB, 6, GPIO_AF9_FDCAN2);
|
||||
|
||||
// G9,G10: FDCAN3
|
||||
set_gpio_pullup(GPIOG, 9, PULL_NONE);
|
||||
set_gpio_alternate(GPIOG, 9, GPIO_AF2_FDCAN3);
|
||||
|
||||
set_gpio_pullup(GPIOG, 10, PULL_NONE);
|
||||
set_gpio_alternate(GPIOG, 10, GPIO_AF2_FDCAN3);
|
||||
}
|
||||
|
||||
void flasher_peripherals_init(void) {
|
||||
RCC->AHB1ENR |= RCC_AHB1ENR_USB1OTGHSEN;
|
||||
}
|
||||
|
||||
// Peripheral initialization
|
||||
void peripherals_init(void) {
|
||||
// enable GPIO(A,B,C,D,E,F,G,H)
|
||||
RCC->AHB4ENR |= RCC_AHB4ENR_GPIOAEN;
|
||||
RCC->AHB4ENR |= RCC_AHB4ENR_GPIOBEN;
|
||||
RCC->AHB4ENR |= RCC_AHB4ENR_GPIOCEN;
|
||||
RCC->AHB4ENR |= RCC_AHB4ENR_GPIODEN;
|
||||
RCC->AHB4ENR |= RCC_AHB4ENR_GPIOEEN;
|
||||
RCC->AHB4ENR |= RCC_AHB4ENR_GPIOFEN;
|
||||
RCC->AHB4ENR |= RCC_AHB4ENR_GPIOGEN;
|
||||
|
||||
RCC->APB1LENR |= RCC_APB1LENR_TIM2EN; // main counter
|
||||
RCC->APB1LENR |= RCC_APB1LENR_TIM6EN; // interrupt timer
|
||||
RCC->APB2ENR |= RCC_APB2ENR_TIM8EN; // clock source timer
|
||||
RCC->APB1LENR |= RCC_APB1LENR_TIM12EN; // slow loop
|
||||
|
||||
RCC->APB1HENR |= RCC_APB1HENR_FDCANEN; // FDCAN core enable
|
||||
RCC->AHB1ENR |= RCC_AHB1ENR_ADC12EN; // Enable ADC clocks
|
||||
|
||||
// HS USB enable, also LP is needed for CSleep state(__WFI())
|
||||
RCC->AHB1ENR |= RCC_AHB1ENR_USB1OTGHSEN;
|
||||
RCC->AHB1LPENR |= RCC_AHB1LPENR_USB1OTGHSLPEN;
|
||||
RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_USB1OTGHSULPILPEN);
|
||||
}
|
||||
|
||||
void enable_interrupt_timer(void) {
|
||||
register_set_bits(&(RCC->APB1LENR), RCC_APB1LENR_TIM6EN); // Enable interrupt timer peripheral
|
||||
}
|
|
@ -0,0 +1,767 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32h735xx.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32H735xx Devices vector table for GCC based toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m7
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
bl __initialize_hardware_early
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
ldr r2, =_sidata
|
||||
movs r3, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
movs r3, #0
|
||||
b LoopFillZerobss
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
/* bl SystemInit */
|
||||
/* Call static constructors */
|
||||
/* bl __libc_init_array */
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.word WWDG_IRQHandler /* Window WatchDog */
|
||||
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
|
||||
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||
.word FLASH_IRQHandler /* FLASH */
|
||||
.word RCC_IRQHandler /* RCC */
|
||||
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
|
||||
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
|
||||
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
|
||||
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
|
||||
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
|
||||
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
|
||||
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
|
||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.word TIM2_IRQHandler /* TIM2 */
|
||||
.word TIM3_IRQHandler /* TIM3 */
|
||||
.word TIM4_IRQHandler /* TIM4 */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word SPI2_IRQHandler /* SPI2 */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||
.word 0 /* Reserved */
|
||||
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
|
||||
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
|
||||
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
|
||||
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||
.word FMC_IRQHandler /* FMC */
|
||||
.word SDMMC1_IRQHandler /* SDMMC1 */
|
||||
.word TIM5_IRQHandler /* TIM5 */
|
||||
.word SPI3_IRQHandler /* SPI3 */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
.word UART5_IRQHandler /* UART5 */
|
||||
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
|
||||
.word TIM7_IRQHandler /* TIM7 */
|
||||
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||
.word ETH_IRQHandler /* Ethernet */
|
||||
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
|
||||
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||
.word USART6_IRQHandler /* USART6 */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
|
||||
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
|
||||
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
||||
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||
.word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
|
||||
.word CRYP_IRQHandler /* CRYP */
|
||||
.word HASH_RNG_IRQHandler /* Hash and Rng */
|
||||
.word FPU_IRQHandler /* FPU */
|
||||
.word UART7_IRQHandler /* UART7 */
|
||||
.word UART8_IRQHandler /* UART8 */
|
||||
.word SPI4_IRQHandler /* SPI4 */
|
||||
.word SPI5_IRQHandler /* SPI5 */
|
||||
.word SPI6_IRQHandler /* SPI6 */
|
||||
.word SAI1_IRQHandler /* SAI1 */
|
||||
.word LTDC_IRQHandler /* LTDC */
|
||||
.word LTDC_ER_IRQHandler /* LTDC error */
|
||||
.word DMA2D_IRQHandler /* DMA2D */
|
||||
.word 0 /* Reserved */
|
||||
.word OCTOSPI1_IRQHandler /* OCTOSPI1 */
|
||||
.word LPTIM1_IRQHandler /* LPTIM1 */
|
||||
.word CEC_IRQHandler /* HDMI_CEC */
|
||||
.word I2C4_EV_IRQHandler /* I2C4 Event */
|
||||
.word I2C4_ER_IRQHandler /* I2C4 Error */
|
||||
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
|
||||
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
|
||||
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
|
||||
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
|
||||
.word 0 /* Reserved */
|
||||
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
|
||||
.word TIM15_IRQHandler /* TIM15 global Interrupt */
|
||||
.word TIM16_IRQHandler /* TIM16 global Interrupt */
|
||||
.word TIM17_IRQHandler /* TIM17 global Interrupt */
|
||||
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
|
||||
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
|
||||
.word 0 /* Reserved */
|
||||
.word MDMA_IRQHandler /* MDMA global Interrupt */
|
||||
.word 0 /* Reserved */
|
||||
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
|
||||
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
|
||||
.word 0 /* Reserved */
|
||||
.word ADC3_IRQHandler /* ADC3 global Interrupt */
|
||||
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
|
||||
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
|
||||
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
|
||||
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
|
||||
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
|
||||
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
|
||||
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
|
||||
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
|
||||
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
|
||||
.word COMP1_IRQHandler /* COMP1 global Interrupt */
|
||||
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
|
||||
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
|
||||
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
|
||||
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
|
||||
.word LPUART1_IRQHandler /* LP UART1 interrupt */
|
||||
.word 0 /* Reserved */
|
||||
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
|
||||
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
|
||||
.word SAI4_IRQHandler /* SAI4 global interrupt */
|
||||
.word DTS_IRQHandler /* Digital Temperature Sensor interrupt */
|
||||
.word 0 /* Reserved */
|
||||
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||
.word OCTOSPI2_IRQHandler /* OCTOSPI2 Interrupt */
|
||||
.word OTFDEC1_IRQHandler /* OTFDEC1 Interrupt */
|
||||
.word OTFDEC2_IRQHandler /* OTFDEC2 Interrupt */
|
||||
.word FMAC_IRQHandler /* FMAC Interrupt */
|
||||
.word CORDIC_IRQHandler /* CORDIC Interrupt */
|
||||
.word UART9_IRQHandler /* UART9 Interrupt */
|
||||
.word USART10_IRQHandler /* UART10 Interrupt */
|
||||
.word I2C5_EV_IRQHandler /* I2C5 Event Interrupt */
|
||||
.word I2C5_ER_IRQHandler /* I2C5 Error Interrupt */
|
||||
.word FDCAN3_IT0_IRQHandler /* FDCAN3 interrupt line 0 */
|
||||
.word FDCAN3_IT1_IRQHandler /* FDCAN3 interrupt line 1 */
|
||||
.word TIM23_IRQHandler /* TIM23 global interrupt */
|
||||
.word TIM24_IRQHandler /* TIM24 global interrupt */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_AVD_IRQHandler
|
||||
.thumb_set PVD_AVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_IRQHandler
|
||||
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream0_IRQHandler
|
||||
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream1_IRQHandler
|
||||
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream2_IRQHandler
|
||||
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream3_IRQHandler
|
||||
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream4_IRQHandler
|
||||
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream5_IRQHandler
|
||||
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream6_IRQHandler
|
||||
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT0_IRQHandler
|
||||
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT0_IRQHandler
|
||||
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT1_IRQHandler
|
||||
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT1_IRQHandler
|
||||
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_TIM12_IRQHandler
|
||||
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_TIM13_IRQHandler
|
||||
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream7_IRQHandler
|
||||
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC1_IRQHandler
|
||||
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_DAC_IRQHandler
|
||||
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream0_IRQHandler
|
||||
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream1_IRQHandler
|
||||
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream2_IRQHandler
|
||||
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream3_IRQHandler
|
||||
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_WKUP_IRQHandler
|
||||
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN_CAL_IRQHandler
|
||||
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream5_IRQHandler
|
||||
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream6_IRQHandler
|
||||
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream7_IRQHandler
|
||||
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART6_IRQHandler
|
||||
.thumb_set USART6_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_OUT_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_IN_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_WKUP_IRQHandler
|
||||
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_IRQHandler
|
||||
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCMI_PSSI_IRQHandler
|
||||
.thumb_set DCMI_PSSI_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRYP_IRQHandler
|
||||
.thumb_set CRYP_IRQHandler,Default_Handler
|
||||
|
||||
.weak HASH_RNG_IRQHandler
|
||||
.thumb_set HASH_RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART8_IRQHandler
|
||||
.thumb_set UART8_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI5_IRQHandler
|
||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI6_IRQHandler
|
||||
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_IRQHandler
|
||||
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LTDC_IRQHandler
|
||||
.thumb_set LTDC_IRQHandler,Default_Handler
|
||||
|
||||
.weak LTDC_ER_IRQHandler
|
||||
.thumb_set LTDC_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2D_IRQHandler
|
||||
.thumb_set DMA2D_IRQHandler,Default_Handler
|
||||
|
||||
.weak OCTOSPI1_IRQHandler
|
||||
.thumb_set OCTOSPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CEC_IRQHandler
|
||||
.thumb_set CEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_EV_IRQHandler
|
||||
.thumb_set I2C4_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_ER_IRQHandler
|
||||
.thumb_set I2C4_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPDIF_RX_IRQHandler
|
||||
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX1_OVR_IRQHandler
|
||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT0_IRQHandler
|
||||
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT1_IRQHandler
|
||||
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT2_IRQHandler
|
||||
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT3_IRQHandler
|
||||
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SWPMI1_IRQHandler
|
||||
.thumb_set SWPMI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM15_IRQHandler
|
||||
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM16_IRQHandler
|
||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM17_IRQHandler
|
||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDIOS_WKUP_IRQHandler
|
||||
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDIOS_IRQHandler
|
||||
.thumb_set MDIOS_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDMA_IRQHandler
|
||||
.thumb_set MDMA_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC2_IRQHandler
|
||||
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM1_IRQHandler
|
||||
.thumb_set HSEM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC3_IRQHandler
|
||||
.thumb_set ADC3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX2_OVR_IRQHandler
|
||||
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel0_IRQHandler
|
||||
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel1_IRQHandler
|
||||
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel2_IRQHandler
|
||||
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel3_IRQHandler
|
||||
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel4_IRQHandler
|
||||
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel5_IRQHandler
|
||||
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel6_IRQHandler
|
||||
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel7_IRQHandler
|
||||
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak COMP1_IRQHandler
|
||||
.thumb_set COMP1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM3_IRQHandler
|
||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM4_IRQHandler
|
||||
.thumb_set LPTIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM5_IRQHandler
|
||||
.thumb_set LPTIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRS_IRQHandler
|
||||
.thumb_set CRS_IRQHandler,Default_Handler
|
||||
|
||||
.weak ECC_IRQHandler
|
||||
.thumb_set ECC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI4_IRQHandler
|
||||
.thumb_set SAI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DTS_IRQHandler
|
||||
.thumb_set DTS_IRQHandler,Default_Handler
|
||||
|
||||
.weak WAKEUP_PIN_IRQHandler
|
||||
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||
|
||||
.weak OCTOSPI2_IRQHandler
|
||||
.thumb_set OCTOSPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTFDEC1_IRQHandler
|
||||
.thumb_set OTFDEC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTFDEC2_IRQHandler
|
||||
.thumb_set OTFDEC2_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMAC_IRQHandler
|
||||
.thumb_set FMAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak CORDIC_IRQHandler
|
||||
.thumb_set CORDIC_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART9_IRQHandler
|
||||
.thumb_set UART9_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART10_IRQHandler
|
||||
.thumb_set USART10_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C5_EV_IRQHandler
|
||||
.thumb_set I2C5_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C5_ER_IRQHandler
|
||||
.thumb_set I2C5_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN3_IT0_IRQHandler
|
||||
.thumb_set FDCAN3_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN3_IT1_IRQHandler
|
||||
.thumb_set FDCAN3_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM23_IRQHandler
|
||||
.thumb_set TIM23_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM24_IRQHandler
|
||||
.thumb_set TIM24_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
#include "stm32h7/inc/stm32h7xx.h"
|
||||
#include "stm32h7/inc/stm32h7xx_hal_gpio_ex.h"
|
||||
#define MCU_IDCODE 0x483U
|
||||
|
||||
// from the linker script
|
||||
#define APP_START_ADDRESS 0x8020000U
|
||||
|
||||
#define CORE_FREQ 240U // in Mhz
|
||||
//APB1 - 120Mhz, APB2 - 120Mhz
|
||||
#define APB1_FREQ CORE_FREQ/2U
|
||||
#define APB2_FREQ CORE_FREQ/2U
|
||||
|
||||
#define BOOTLOADER_ADDRESS 0x1FF09804U
|
||||
|
||||
// Around (1Mbps / 8 bits/byte / 12 bytes per message)
|
||||
#define CAN_INTERRUPT_RATE 12000U // FIXME: should raise to 16000 ?
|
||||
|
||||
#define MAX_LED_FADE 10240U
|
||||
|
||||
// Threshold voltage (mV) for either of the SBUs to be below before deciding harness is connected
|
||||
#define HARNESS_CONNECTED_THRESHOLD 40000U
|
||||
|
||||
// There are 163 external interrupt sources (see stm32f735xx.h)
|
||||
#define NUM_INTERRUPTS 163U
|
||||
|
||||
#define TICK_TIMER_IRQ TIM8_BRK_TIM12_IRQn
|
||||
#define TICK_TIMER TIM12
|
||||
|
||||
#define MICROSECOND_TIMER TIM2
|
||||
|
||||
#define INTERRUPT_TIMER_IRQ TIM6_DAC_IRQn
|
||||
#define INTERRUPT_TIMER TIM6
|
||||
|
||||
#define PROVISION_CHUNK_ADDRESS 0x080FFFE0U
|
||||
#define DEVICE_SERIAL_NUMBER_ADDRESS 0x080FFFC0U
|
||||
|
||||
#ifndef BOOTSTUB
|
||||
#include "main_declarations.h"
|
||||
#else
|
||||
#include "bootstub_declarations.h"
|
||||
#endif
|
||||
|
||||
#include "libc.h"
|
||||
#include "critical.h"
|
||||
#include "faults.h"
|
||||
|
||||
#include "drivers/registers.h"
|
||||
#include "drivers/interrupts.h"
|
||||
#include "drivers/gpio.h"
|
||||
#include "stm32h7/peripherals.h"
|
||||
#include "stm32h7/interrupt_handlers.h"
|
||||
#include "drivers/timers.h"
|
||||
#include "stm32h7/lladc.h"
|
||||
#include "stm32h7/board.h"
|
||||
#include "stm32h7/clock.h"
|
||||
|
||||
#if !defined (BOOTSTUB) && defined(PANDA)
|
||||
#include "drivers/uart.h"
|
||||
#include "stm32h7/lluart.h"
|
||||
#endif
|
||||
|
||||
#ifdef BOOTSTUB
|
||||
#include "stm32h7/llflash.h"
|
||||
#else
|
||||
#include "stm32h7/llfdcan.h"
|
||||
#endif
|
||||
|
||||
#include "stm32h7/llusb.h"
|
||||
|
||||
void early_gpio_float(void) {
|
||||
RCC->AHB4ENR = RCC_AHB4ENR_GPIOAEN | RCC_AHB4ENR_GPIOBEN | RCC_AHB4ENR_GPIOCEN | RCC_AHB4ENR_GPIODEN | RCC_AHB4ENR_GPIOEEN | RCC_AHB4ENR_GPIOFEN | RCC_AHB4ENR_GPIOGEN | RCC_AHB4ENR_GPIOHEN;
|
||||
GPIOA->MODER = 0; GPIOB->MODER = 0; GPIOC->MODER = 0; GPIOD->MODER = 0; GPIOE->MODER = 0; GPIOF->MODER = 0; GPIOG->MODER = 0; GPIOH->MODER = 0;
|
||||
GPIOA->ODR = 0; GPIOB->ODR = 0; GPIOC->ODR = 0; GPIOD->ODR = 0; GPIOE->ODR = 0; GPIOF->ODR = 0; GPIOG->ODR = 0; GPIOH->ODR = 0;
|
||||
GPIOA->PUPDR = 0; GPIOB->PUPDR = 0; GPIOC->PUPDR = 0; GPIOD->PUPDR = 0; GPIOE->PUPDR = 0; GPIOF->PUPDR = 0; GPIOG->PUPDR = 0; GPIOH->PUPDR = 0;
|
||||
}
|
|
@ -0,0 +1,186 @@
|
|||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
|
||||
** File : LinkerScript.ld
|
||||
**
|
||||
** Author : Auto-generated by System Workbench for STM32
|
||||
**
|
||||
** Abstract : Linker script for STM32H735ZGTx series
|
||||
** 1024Kbytes FLASH and 560Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed “as is,” without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
** 1. Redistributions of source code must retain the above copyright notice,
|
||||
** this list of conditions and the following disclaimer.
|
||||
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
** this list of conditions and the following disclaimer in the documentation
|
||||
** and/or other materials provided with the distribution.
|
||||
** 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
** may be used to endorse or promote products derived from this software
|
||||
** without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
enter_bootloader_mode = 0x38001FFC;
|
||||
_estack = 0x20020000; /* end of RAM */
|
||||
_app_start = 0x08020000; /* Reserve Sector 0(128K) for bootloader */
|
||||
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||
RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 320K
|
||||
RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 32K
|
||||
RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 16K
|
||||
ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
|
||||
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >DTCMRAM AT> FLASH
|
||||
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >DTCMRAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >DTCMRAM
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
||||
|
|
@ -8,17 +8,16 @@ import os
|
|||
import time
|
||||
import traceback
|
||||
import sys
|
||||
from .dfu import PandaDFU # pylint: disable=import-error
|
||||
from .dfu import PandaDFU, MCU_TYPE_F2, MCU_TYPE_F4, MCU_TYPE_H7 # pylint: disable=import-error
|
||||
from .flash_release import flash_release # noqa pylint: disable=import-error
|
||||
from .update import ensure_st_up_to_date # noqa pylint: disable=import-error
|
||||
from .serial import PandaSerial # noqa pylint: disable=import-error
|
||||
from .isotp import isotp_send, isotp_recv # pylint: disable=import-error
|
||||
|
||||
from .config import DEFAULT_FW_FN, DEFAULT_H7_FW_FN # noqa pylint: disable=import-error
|
||||
|
||||
__version__ = '0.0.9'
|
||||
|
||||
BASEDIR = os.path.join(os.path.dirname(os.path.realpath(__file__)), "../")
|
||||
DEFAULT_FW_FN = os.path.join(BASEDIR, "board", "obj", "panda.bin.signed")
|
||||
|
||||
DEBUG = os.getenv("PANDADEBUG") is not None
|
||||
|
||||
|
@ -139,6 +138,11 @@ class Panda(object):
|
|||
HW_TYPE_PEDAL = b'\x04'
|
||||
HW_TYPE_UNO = b'\x05'
|
||||
HW_TYPE_DOS = b'\x06'
|
||||
HW_TYPE_RED_PANDA = b'\x07'
|
||||
|
||||
F2_DEVICES = [HW_TYPE_PEDAL]
|
||||
F4_DEVICES = [HW_TYPE_WHITE_PANDA, HW_TYPE_GREY_PANDA, HW_TYPE_BLACK_PANDA, HW_TYPE_UNO, HW_TYPE_DOS]
|
||||
H7_DEVICES = [HW_TYPE_RED_PANDA]
|
||||
|
||||
CLOCK_SOURCE_MODE_DISABLED = 0
|
||||
CLOCK_SOURCE_MODE_FREE_RUNNING = 1
|
||||
|
@ -151,6 +155,7 @@ class Panda(object):
|
|||
self._serial = serial
|
||||
self._handle = None
|
||||
self.connect(claim)
|
||||
self._mcu_type = self.get_mcu_type()
|
||||
|
||||
def close(self):
|
||||
self._handle.close()
|
||||
|
@ -225,7 +230,7 @@ class Panda(object):
|
|||
except Exception:
|
||||
print("reconnecting is taking %d seconds..." % (i + 1))
|
||||
try:
|
||||
dfu = PandaDFU(PandaDFU.st_serial_to_dfu_serial(self._serial))
|
||||
dfu = PandaDFU(PandaDFU.st_serial_to_dfu_serial(self._serial, self._mcu_type))
|
||||
dfu.recover()
|
||||
except Exception:
|
||||
pass
|
||||
|
@ -262,6 +267,8 @@ class Panda(object):
|
|||
pass
|
||||
|
||||
def flash(self, fn=DEFAULT_FW_FN, code=None, reconnect=True):
|
||||
if self._mcu_type == MCU_TYPE_H7 and fn == DEFAULT_FW_FN:
|
||||
fn = DEFAULT_H7_FW_FN
|
||||
print("flash: main version is " + self.get_version())
|
||||
if not self.bootstub:
|
||||
self.reset(enter_bootstub=True)
|
||||
|
@ -291,7 +298,7 @@ class Panda(object):
|
|||
if timeout is not None and (time.time() - t_start) > timeout:
|
||||
return False
|
||||
|
||||
dfu = PandaDFU(PandaDFU.st_serial_to_dfu_serial(self._serial))
|
||||
dfu = PandaDFU(PandaDFU.st_serial_to_dfu_serial(self._serial, self._mcu_type))
|
||||
dfu.recover()
|
||||
|
||||
# reflash after recover
|
||||
|
@ -402,8 +409,24 @@ class Panda(object):
|
|||
def is_dos(self):
|
||||
return self.get_type() == Panda.HW_TYPE_DOS
|
||||
|
||||
def is_red(self):
|
||||
return self.get_type() == Panda.HW_TYPE_RED_PANDA
|
||||
|
||||
def get_mcu_type(self):
|
||||
hw_type = self.get_type()
|
||||
if hw_type in Panda.F2_DEVICES:
|
||||
return MCU_TYPE_F2
|
||||
elif hw_type in Panda.F4_DEVICES:
|
||||
return MCU_TYPE_F4
|
||||
elif hw_type in Panda.H7_DEVICES:
|
||||
return MCU_TYPE_H7
|
||||
return None
|
||||
|
||||
def has_obd(self):
|
||||
return (self.is_uno() or self.is_dos() or self.is_black())
|
||||
return (self.is_uno() or self.is_dos() or self.is_black() or self.is_red())
|
||||
|
||||
def has_canfd(self):
|
||||
return self._mcu_type in Panda.H7_DEVICES
|
||||
|
||||
def get_serial(self):
|
||||
dat = self._handle.controlRead(Panda.REQUEST_IN, 0xd0, 0, 0, 0x20)
|
||||
|
@ -460,6 +483,9 @@ class Panda(object):
|
|||
def set_can_speed_kbps(self, bus, speed):
|
||||
self._handle.controlWrite(Panda.REQUEST_OUT, 0xde, bus, int(speed * 10), b'')
|
||||
|
||||
def set_can_data_speed_kbps(self, bus, speed):
|
||||
self._handle.controlWrite(Panda.REQUEST_OUT, 0xf9, bus, int(speed * 10), b'')
|
||||
|
||||
def set_uart_baud(self, uart, rate):
|
||||
self._handle.controlWrite(Panda.REQUEST_OUT, 0xe4, uart, int(rate / 300), b'')
|
||||
|
||||
|
|
|
@ -0,0 +1,18 @@
|
|||
import os
|
||||
|
||||
|
||||
BASEDIR = os.path.join(os.path.dirname(os.path.realpath(__file__)), "../")
|
||||
|
||||
BOOTSTUB_ADDRESS = 0x8000000
|
||||
|
||||
BLOCK_SIZE_FX = 0x800
|
||||
APP_ADDRESS_FX = 0x8004000
|
||||
DEVICE_SERIAL_NUMBER_ADDR_FX = 0x1FFF79C0
|
||||
DEFAULT_FW_FN = os.path.join(BASEDIR, "board", "obj", "panda.bin.signed")
|
||||
DEFAULT_BOOTSTUB_FN = os.path.join(BASEDIR, "board", "obj", "bootstub.panda.bin")
|
||||
|
||||
BLOCK_SIZE_H7 = 0x400
|
||||
APP_ADDRESS_H7 = 0x8020000
|
||||
DEVICE_SERIAL_NUMBER_ADDR_H7 = 0x080FFFC0
|
||||
DEFAULT_H7_FW_FN = os.path.join(BASEDIR, "board", "obj", "panda_h7.bin.signed")
|
||||
DEFAULT_H7_BOOTSTUB_FN = os.path.join(BASEDIR, "board", "obj", "bootstub.panda_h7.bin")
|
|
@ -1,10 +1,14 @@
|
|||
import os
|
||||
import usb1
|
||||
import struct
|
||||
import binascii
|
||||
from .config import BOOTSTUB_ADDRESS, APP_ADDRESS_H7, APP_ADDRESS_FX, BLOCK_SIZE_H7, BLOCK_SIZE_FX, DEFAULT_H7_BOOTSTUB_FN, DEFAULT_BOOTSTUB_FN
|
||||
|
||||
|
||||
MCU_TYPE_F2 = 0
|
||||
MCU_TYPE_F4 = 1
|
||||
MCU_TYPE_H7 = 2
|
||||
|
||||
# *** DFU mode ***
|
||||
|
||||
DFU_DNLOAD = 1
|
||||
DFU_UPLOAD = 2
|
||||
DFU_GETSTATUS = 3
|
||||
|
@ -21,6 +25,7 @@ class PandaDFU(object):
|
|||
except Exception:
|
||||
continue
|
||||
if this_dfu_serial == dfu_serial or dfu_serial is None:
|
||||
self._mcu_type = self.get_mcu_type(device)
|
||||
self._handle = device.open()
|
||||
return
|
||||
raise Exception("failed to open " + dfu_serial if dfu_serial is not None else "DFU device")
|
||||
|
@ -41,12 +46,19 @@ class PandaDFU(object):
|
|||
return dfu_serials
|
||||
|
||||
@staticmethod
|
||||
def st_serial_to_dfu_serial(st):
|
||||
def st_serial_to_dfu_serial(st, mcu_type=MCU_TYPE_F4):
|
||||
if st is None or st == "none":
|
||||
return None
|
||||
uid_base = struct.unpack("H" * 6, bytes.fromhex(st))
|
||||
if mcu_type == MCU_TYPE_H7:
|
||||
return binascii.hexlify(struct.pack("!HHH", uid_base[1] + uid_base[5], uid_base[0] + uid_base[4], uid_base[3])).upper().decode("utf-8")
|
||||
else:
|
||||
return binascii.hexlify(struct.pack("!HHH", uid_base[1] + uid_base[5], uid_base[0] + uid_base[4] + 0xA, uid_base[3])).upper().decode("utf-8")
|
||||
|
||||
# TODO: Find a way to detect F4 vs F2
|
||||
def get_mcu_type(self, dev):
|
||||
return MCU_TYPE_H7 if dev.getbcdDevice() == 512 else MCU_TYPE_F4
|
||||
|
||||
def status(self):
|
||||
while 1:
|
||||
dat = self._handle.controlRead(0x21, DFU_GETSTATUS, 0, 0, 6)
|
||||
|
@ -85,14 +97,17 @@ class PandaDFU(object):
|
|||
|
||||
def program_bootstub(self, code_bootstub):
|
||||
self.clear_status()
|
||||
self.erase(0x8004000)
|
||||
self.erase(0x8000000)
|
||||
self.program(0x8000000, code_bootstub, 0x800)
|
||||
self.erase(BOOTSTUB_ADDRESS)
|
||||
if self._mcu_type == MCU_TYPE_H7:
|
||||
self.erase(APP_ADDRESS_H7)
|
||||
self.program(BOOTSTUB_ADDRESS, code_bootstub, BLOCK_SIZE_H7)
|
||||
else:
|
||||
self.erase(APP_ADDRESS_FX)
|
||||
self.program(BOOTSTUB_ADDRESS, code_bootstub, BLOCK_SIZE_FX)
|
||||
self.reset()
|
||||
|
||||
def recover(self):
|
||||
from panda import BASEDIR
|
||||
fn = os.path.join(BASEDIR, "board", "obj", "bootstub.panda.bin")
|
||||
fn = DEFAULT_H7_BOOTSTUB_FN if self._mcu_type == MCU_TYPE_H7 else DEFAULT_BOOTSTUB_FN
|
||||
|
||||
with open(fn, "rb") as f:
|
||||
code = f.read()
|
||||
|
@ -101,7 +116,7 @@ class PandaDFU(object):
|
|||
|
||||
def reset(self):
|
||||
# **** Reset ****
|
||||
self._handle.controlWrite(0x21, DFU_DNLOAD, 0, 0, b"\x21" + struct.pack("I", 0x8000000))
|
||||
self._handle.controlWrite(0x21, DFU_DNLOAD, 0, 0, b"\x21" + struct.pack("I", BOOTSTUB_ADDRESS))
|
||||
self.status()
|
||||
try:
|
||||
self._handle.controlWrite(0x21, DFU_DNLOAD, 2, 0, b"")
|
||||
|
|
|
@ -275,6 +275,7 @@ selfdrive/hardware/hw.h
|
|||
selfdrive/hardware/eon/__init__.py
|
||||
selfdrive/hardware/eon/hardware.h
|
||||
selfdrive/hardware/eon/hardware.py
|
||||
selfdrive/hardware/eon/androidd.py
|
||||
selfdrive/hardware/tici/__init__.py
|
||||
selfdrive/hardware/tici/hardware.py
|
||||
selfdrive/hardware/tici/amplifier.py
|
||||
|
@ -310,7 +311,9 @@ selfdrive/logcatd/logcatd_android.cc
|
|||
selfdrive/logcatd/logcatd_systemd.cc
|
||||
|
||||
selfdrive/proclogd/SConscript
|
||||
selfdrive/proclogd/proclogd.cc
|
||||
selfdrive/proclogd/main.cc
|
||||
selfdrive/proclogd/proclog.cc
|
||||
selfdrive/proclogd/proclog.h
|
||||
|
||||
selfdrive/loggerd/SConscript
|
||||
selfdrive/loggerd/encoder.h
|
||||
|
@ -502,6 +505,7 @@ cereal/log.capnp
|
|||
cereal/services.py
|
||||
cereal/SConscript
|
||||
cereal/include/**
|
||||
cereal/logger/logger.h
|
||||
cereal/messaging/.gitignore
|
||||
cereal/messaging/__init__.py
|
||||
cereal/messaging/bridge.cc
|
||||
|
@ -525,7 +529,6 @@ cereal/visionipc/*.pxd
|
|||
|
||||
panda/.gitignore
|
||||
panda/__init__.py
|
||||
panda/VERSION
|
||||
panda/board/**
|
||||
panda/certs/**
|
||||
panda/crypto/**
|
||||
|
|
|
@ -1,5 +1,3 @@
|
|||
installer/continue_openpilot.sh
|
||||
|
||||
phonelibs/mapbox-gl-native-qt/include/*
|
||||
|
||||
selfdrive/timezoned.py
|
||||
|
|
|
@ -22,6 +22,7 @@ from websocket import ABNF, WebSocketTimeoutException, WebSocketException, creat
|
|||
import cereal.messaging as messaging
|
||||
from cereal.services import service_list
|
||||
from common.api import Api
|
||||
from common.file_helpers import CallbackReader
|
||||
from common.basedir import PERSIST
|
||||
from common.params import Params
|
||||
from common.realtime import sec_since_boot
|
||||
|
@ -41,6 +42,7 @@ RECONNECT_TIMEOUT_S = 70
|
|||
|
||||
RETRY_DELAY = 10 # seconds
|
||||
MAX_RETRY_COUNT = 30 # Try for at most 5 minutes if upload fails immediately
|
||||
WS_FRAME_SIZE = 4096
|
||||
|
||||
dispatcher["echo"] = lambda s: s
|
||||
recv_queue: Any = queue.Queue()
|
||||
|
@ -49,7 +51,9 @@ upload_queue: Any = queue.Queue()
|
|||
log_send_queue: Any = queue.Queue()
|
||||
log_recv_queue: Any = queue.Queue()
|
||||
cancelled_uploads: Any = set()
|
||||
UploadItem = namedtuple('UploadItem', ['path', 'url', 'headers', 'created_at', 'id', 'retry_count'], defaults=(0,))
|
||||
UploadItem = namedtuple('UploadItem', ['path', 'url', 'headers', 'created_at', 'id', 'retry_count', 'current', 'progress'], defaults=(0, False, 0))
|
||||
|
||||
cur_upload_items = {}
|
||||
|
||||
|
||||
def handle_long_poll(ws):
|
||||
|
@ -100,35 +104,53 @@ def jsonrpc_handler(end_event):
|
|||
|
||||
|
||||
def upload_handler(end_event):
|
||||
tid = threading.get_ident()
|
||||
|
||||
while not end_event.is_set():
|
||||
cur_upload_items[tid] = None
|
||||
|
||||
try:
|
||||
item = upload_queue.get(timeout=1)
|
||||
if item.id in cancelled_uploads:
|
||||
cancelled_uploads.remove(item.id)
|
||||
cur_upload_items[tid] = upload_queue.get(timeout=1)._replace(current=True)
|
||||
if cur_upload_items[tid].id in cancelled_uploads:
|
||||
cancelled_uploads.remove(cur_upload_items[tid].id)
|
||||
continue
|
||||
|
||||
try:
|
||||
_do_upload(item)
|
||||
except (requests.exceptions.Timeout, requests.exceptions.ConnectionError, requests.exceptions.SSLError) as e:
|
||||
cloudlog.warning(f"athena.upload_handler.retry {e} {item}")
|
||||
def cb(sz, cur):
|
||||
cur_upload_items[tid] = cur_upload_items[tid]._replace(progress=cur / sz if sz else 1)
|
||||
|
||||
if item.retry_count < MAX_RETRY_COUNT:
|
||||
item = item._replace(retry_count=item.retry_count + 1)
|
||||
_do_upload(cur_upload_items[tid], cb)
|
||||
except (requests.exceptions.Timeout, requests.exceptions.ConnectionError, requests.exceptions.SSLError) as e:
|
||||
cloudlog.warning(f"athena.upload_handler.retry {e} {cur_upload_items[tid]}")
|
||||
|
||||
if cur_upload_items[tid].retry_count < MAX_RETRY_COUNT:
|
||||
item = cur_upload_items[tid]
|
||||
item = item._replace(
|
||||
retry_count=item.retry_count + 1,
|
||||
progress=0,
|
||||
current=False
|
||||
)
|
||||
upload_queue.put_nowait(item)
|
||||
cur_upload_items[tid] = None
|
||||
|
||||
for _ in range(RETRY_DELAY):
|
||||
time.sleep(1)
|
||||
if end_event.is_set():
|
||||
break
|
||||
|
||||
except queue.Empty:
|
||||
pass
|
||||
except Exception:
|
||||
cloudlog.exception("athena.upload_handler.exception")
|
||||
|
||||
|
||||
def _do_upload(upload_item):
|
||||
def _do_upload(upload_item, callback=None):
|
||||
with open(upload_item.path, "rb") as f:
|
||||
size = os.fstat(f.fileno()).st_size
|
||||
|
||||
if callback:
|
||||
f = CallbackReader(f, callback, size)
|
||||
|
||||
return requests.put(upload_item.url,
|
||||
data=f,
|
||||
headers={**upload_item.headers, 'Content-Length': str(size)},
|
||||
|
@ -171,11 +193,29 @@ def setNavDestination(latitude=0, longitude=0):
|
|||
return {"success": 1}
|
||||
|
||||
|
||||
@dispatcher.add_method
|
||||
def listDataDirectory():
|
||||
files = [os.path.relpath(os.path.join(dp, f), ROOT) for dp, dn, fn in os.walk(ROOT) for f in fn]
|
||||
def scan_dir(path, prefix):
|
||||
files = list()
|
||||
# only walk directories that match the prefix
|
||||
# (glob and friends traverse entire dir tree)
|
||||
with os.scandir(path) as i:
|
||||
for e in i:
|
||||
rel_path = os.path.relpath(e.path, ROOT)
|
||||
if e.is_dir(follow_symlinks=False):
|
||||
# add trailing slash
|
||||
rel_path = os.path.join(rel_path, '')
|
||||
# if prefix is a partial dir name, current dir will start with prefix
|
||||
# if prefix is a partial file name, prefix with start with dir name
|
||||
if rel_path.startswith(prefix) or prefix.startswith(rel_path):
|
||||
files.extend(scan_dir(e.path, prefix))
|
||||
else:
|
||||
if rel_path.startswith(prefix):
|
||||
files.append(rel_path)
|
||||
return files
|
||||
|
||||
@dispatcher.add_method
|
||||
def listDataDirectory(prefix=''):
|
||||
return scan_dir(ROOT, prefix)
|
||||
|
||||
|
||||
@dispatcher.add_method
|
||||
def reboot():
|
||||
|
@ -212,7 +252,8 @@ def uploadFileToUrl(fn, url, headers):
|
|||
|
||||
@dispatcher.add_method
|
||||
def listUploadQueue():
|
||||
return [item._asdict() for item in list(upload_queue.queue)]
|
||||
items = list(upload_queue.queue) + list(cur_upload_items.values())
|
||||
return [i._asdict() for i in items if i is not None]
|
||||
|
||||
|
||||
@dispatcher.add_method
|
||||
|
@ -466,7 +507,11 @@ def ws_send(ws, end_event):
|
|||
data = send_queue.get_nowait()
|
||||
except queue.Empty:
|
||||
data = log_send_queue.get(timeout=1)
|
||||
ws.send(data)
|
||||
for i in range(0, len(data), WS_FRAME_SIZE):
|
||||
frame = data[i:i+WS_FRAME_SIZE]
|
||||
last = i + WS_FRAME_SIZE >= len(data)
|
||||
opcode = ABNF.OPCODE_TEXT if i == 0 else ABNF.OPCODE_CONT
|
||||
ws.send_frame(ABNF.create_frame(frame, opcode, last))
|
||||
except queue.Empty:
|
||||
pass
|
||||
except Exception:
|
||||
|
@ -514,6 +559,8 @@ def main():
|
|||
manage_tokens(api)
|
||||
|
||||
conn_retries = 0
|
||||
cur_upload_items.clear()
|
||||
|
||||
handle_long_poll(ws)
|
||||
except (KeyboardInterrupt, SystemExit):
|
||||
break
|
||||
|
|
|
@ -445,9 +445,10 @@ void hardware_control_thread() {
|
|||
if (sm.updated("driverCameraState")) {
|
||||
auto event = sm["driverCameraState"];
|
||||
int cur_integ_lines = event.getDriverCameraState().getIntegLines();
|
||||
float cur_gain = event.getDriverCameraState().getGain();
|
||||
|
||||
if (Hardware::TICI()) {
|
||||
cur_integ_lines = integ_lines_filter.update(cur_integ_lines);
|
||||
cur_integ_lines = integ_lines_filter.update(cur_integ_lines * cur_gain);
|
||||
}
|
||||
last_front_frame_t = event.getLogMonoTime();
|
||||
|
||||
|
|
|
@ -11,8 +11,10 @@
|
|||
#include "selfdrive/common/swaglog.h"
|
||||
#include "selfdrive/common/util.h"
|
||||
|
||||
Panda::Panda() {
|
||||
Panda::Panda(std::string serial) {
|
||||
// init libusb
|
||||
ssize_t num_devices;
|
||||
libusb_device **dev_list = NULL;
|
||||
int err = libusb_init(&ctx);
|
||||
if (err != 0) { goto fail; }
|
||||
|
||||
|
@ -22,9 +24,29 @@ Panda::Panda() {
|
|||
libusb_set_debug(ctx, 3);
|
||||
#endif
|
||||
|
||||
dev_handle = libusb_open_device_with_vid_pid(ctx, 0xbbaa, 0xddcc);
|
||||
// connect by serial
|
||||
num_devices = libusb_get_device_list(ctx, &dev_list);
|
||||
if (num_devices < 0) { goto fail; }
|
||||
for (size_t i = 0; i < num_devices; ++i) {
|
||||
libusb_device_descriptor desc;
|
||||
libusb_get_device_descriptor(dev_list[i], &desc);
|
||||
if (desc.idVendor == 0xbbaa && desc.idProduct == 0xddcc) {
|
||||
libusb_open(dev_list[i], &dev_handle);
|
||||
if (dev_handle == NULL) { goto fail; }
|
||||
|
||||
unsigned char desc_serial[25];
|
||||
int ret = libusb_get_string_descriptor_ascii(dev_handle, desc.iSerialNumber, desc_serial, sizeof(desc_serial));
|
||||
if (ret < 0) { goto fail; }
|
||||
|
||||
if (serial.empty() || serial.compare(reinterpret_cast<const char*>(desc_serial)) == 0) {
|
||||
break;
|
||||
}
|
||||
libusb_close(dev_handle);
|
||||
dev_handle = NULL;
|
||||
}
|
||||
}
|
||||
libusb_free_device_list(dev_list, 1);
|
||||
|
||||
if (libusb_kernel_driver_active(dev_handle, 0) == 1) {
|
||||
libusb_detach_kernel_driver(dev_handle, 0);
|
||||
}
|
||||
|
@ -47,6 +69,9 @@ Panda::Panda() {
|
|||
|
||||
fail:
|
||||
cleanup();
|
||||
if (dev_list != NULL) {
|
||||
libusb_free_device_list(dev_list, 1);
|
||||
}
|
||||
throw std::runtime_error("Error connecting to panda");
|
||||
}
|
||||
|
||||
|
|
|
@ -49,7 +49,7 @@ class Panda {
|
|||
void cleanup();
|
||||
|
||||
public:
|
||||
Panda();
|
||||
Panda(std::string serial="");
|
||||
~Panda();
|
||||
|
||||
std::atomic<bool> connected = true;
|
||||
|
|
|
@ -127,8 +127,6 @@ bool CameraBuf::acquire() {
|
|||
const size_t globalWorkSize[] = {size_t(camera_state->ci.frame_width), size_t(camera_state->ci.frame_height)};
|
||||
const size_t localWorkSize[] = {DEBAYER_LOCAL_WORKSIZE, DEBAYER_LOCAL_WORKSIZE};
|
||||
CL_CHECK(clSetKernelArg(krnl_debayer, 2, localMemSize, 0));
|
||||
int ggain = camera_state->analog_gain + 4*camera_state->dc_gain_enabled;
|
||||
CL_CHECK(clSetKernelArg(krnl_debayer, 3, sizeof(int), &ggain));
|
||||
CL_CHECK(clEnqueueNDRangeKernel(q, krnl_debayer, 2, NULL, globalWorkSize, localWorkSize,
|
||||
0, 0, &debayer_event));
|
||||
#else
|
||||
|
@ -193,11 +191,11 @@ void fill_frame_data(cereal::FrameData::Builder &framed, const FrameMetadata &fr
|
|||
}
|
||||
|
||||
kj::Array<uint8_t> get_frame_image(const CameraBuf *b) {
|
||||
static const int x_min = getenv("XMIN") ? atoi(getenv("XMIN")) : 0;
|
||||
static const int y_min = getenv("YMIN") ? atoi(getenv("YMIN")) : 0;
|
||||
static const int env_xmax = getenv("XMAX") ? atoi(getenv("XMAX")) : -1;
|
||||
static const int env_ymax = getenv("YMAX") ? atoi(getenv("YMAX")) : -1;
|
||||
static const int scale = getenv("SCALE") ? atoi(getenv("SCALE")) : 1;
|
||||
static const int x_min = util::getenv("XMIN", 0);
|
||||
static const int y_min = util::getenv("YMIN", 0);
|
||||
static const int env_xmax = util::getenv("XMAX", -1);
|
||||
static const int env_ymax = util::getenv("YMAX", -1);
|
||||
static const int scale = util::getenv("SCALE", 1);
|
||||
|
||||
assert(b->cur_rgb_buf);
|
||||
|
||||
|
@ -280,39 +278,30 @@ static void publish_thumbnail(PubMaster *pm, const CameraBuf *b) {
|
|||
free(thumbnail_buffer);
|
||||
}
|
||||
|
||||
float set_exposure_target(const CameraBuf *b, int x_start, int x_end, int x_skip, int y_start, int y_end, int y_skip, int analog_gain, bool hist_ceil, bool hl_weighted) {
|
||||
const uint8_t *pix_ptr = b->cur_yuv_buf->y;
|
||||
float set_exposure_target(const CameraBuf *b, int x_start, int x_end, int x_skip, int y_start, int y_end, int y_skip) {
|
||||
int lum_med;
|
||||
uint32_t lum_binning[256] = {0};
|
||||
const uint8_t *pix_ptr = b->cur_yuv_buf->y;
|
||||
|
||||
unsigned int lum_total = 0;
|
||||
for (int y = y_start; y < y_end; y += y_skip) {
|
||||
for (int x = x_start; x < x_end; x += x_skip) {
|
||||
uint8_t lum = pix_ptr[(y * b->rgb_width) + x];
|
||||
if (hist_ceil && lum < 80 && lum_binning[lum] > HISTO_CEIL_K * (y_end - y_start) * (x_end - x_start) / x_skip / y_skip / 256) {
|
||||
continue;
|
||||
}
|
||||
lum_binning[lum]++;
|
||||
lum_total += 1;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// Find mean lumimance value
|
||||
unsigned int lum_cur = 0;
|
||||
int lum_med = 0;
|
||||
int lum_med_alt = 0;
|
||||
for (lum_med=255; lum_med>=0; lum_med--) {
|
||||
for (lum_med = 255; lum_med >= 0; lum_med--) {
|
||||
lum_cur += lum_binning[lum_med];
|
||||
if (hl_weighted) {
|
||||
int lum_med_tmp = 0;
|
||||
int hb = HLC_THRESH + (10 - analog_gain);
|
||||
if (lum_cur > 0 && lum_med > hb) {
|
||||
lum_med_tmp = (lum_med - hb) + 100;
|
||||
}
|
||||
lum_med_alt = lum_med_alt>lum_med_tmp?lum_med_alt:lum_med_tmp;
|
||||
}
|
||||
|
||||
if (lum_cur >= lum_total / 2) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
lum_med = lum_med_alt>0 ? lum_med + lum_med/32*lum_cur*abs(lum_med_alt - lum_med)/lum_total:lum_med;
|
||||
|
||||
return lum_med / 256.0;
|
||||
}
|
||||
|
@ -355,18 +344,12 @@ static void driver_cam_auto_exposure(CameraState *c, SubMaster &sm) {
|
|||
struct ExpRect {int x1, x2, x_skip, y1, y2, y_skip;};
|
||||
const CameraBuf *b = &c->buf;
|
||||
|
||||
bool hist_ceil = false, hl_weighted = false;
|
||||
int x_offset = 0, y_offset = 0;
|
||||
int frame_width = b->rgb_width, frame_height = b->rgb_height;
|
||||
#ifndef QCOM2
|
||||
int analog_gain = -1;
|
||||
#else
|
||||
int analog_gain = c->analog_gain;
|
||||
#endif
|
||||
|
||||
|
||||
ExpRect def_rect;
|
||||
if (Hardware::TICI()) {
|
||||
hist_ceil = hl_weighted = true;
|
||||
x_offset = 630, y_offset = 156;
|
||||
frame_width = 668, frame_height = frame_width / 1.33;
|
||||
def_rect = {96, 1832, 2, 242, 1148, 4};
|
||||
|
@ -377,7 +360,7 @@ static void driver_cam_auto_exposure(CameraState *c, SubMaster &sm) {
|
|||
|
||||
static ExpRect rect = def_rect;
|
||||
// use driver face crop for AE
|
||||
if (sm.updated("driverState")) {
|
||||
if (Hardware::EON() && sm.updated("driverState")) {
|
||||
if (auto state = sm["driverState"].getDriverState(); state.getFaceProb() > 0.4) {
|
||||
auto face_position = state.getFacePosition();
|
||||
int x = is_rhd ? 0 : frame_width - (0.5 * frame_height);
|
||||
|
@ -385,16 +368,15 @@ static void driver_cam_auto_exposure(CameraState *c, SubMaster &sm) {
|
|||
int y = (face_position[1] + 0.5) * frame_height + y_offset;
|
||||
rect = {std::max(0, x - 72), std::min(b->rgb_width - 1, x + 72), 2,
|
||||
std::max(0, y - 72), std::min(b->rgb_height - 1, y + 72), 1};
|
||||
} else {
|
||||
rect = def_rect;
|
||||
}
|
||||
}
|
||||
|
||||
camera_autoexposure(c, set_exposure_target(b, rect.x1, rect.x2, rect.x_skip, rect.y1, rect.y2, rect.y_skip, analog_gain, hist_ceil, hl_weighted));
|
||||
camera_autoexposure(c, set_exposure_target(b, rect.x1, rect.x2, rect.x_skip, rect.y1, rect.y2, rect.y_skip));
|
||||
}
|
||||
|
||||
void common_process_driver_camera(SubMaster *sm, PubMaster *pm, CameraState *c, int cnt) {
|
||||
if (cnt % 3 == 0) {
|
||||
int j = Hardware::TICI() ? 1 : 3;
|
||||
if (cnt % j == 0) {
|
||||
sm->update(0);
|
||||
driver_cam_auto_exposure(c, *sm);
|
||||
}
|
||||
|
|
|
@ -27,16 +27,13 @@
|
|||
#define CAMERA_ID_MAX 9
|
||||
|
||||
#define UI_BUF_COUNT 4
|
||||
|
||||
#define LOG_CAMERA_ID_FCAMERA 0
|
||||
#define LOG_CAMERA_ID_DCAMERA 1
|
||||
#define LOG_CAMERA_ID_ECAMERA 2
|
||||
#define LOG_CAMERA_ID_QCAMERA 3
|
||||
#define LOG_CAMERA_ID_MAX 4
|
||||
|
||||
#define HLC_THRESH 222
|
||||
#define HLC_A 80
|
||||
#define HISTO_CEIL_K 5
|
||||
|
||||
const bool env_send_driver = getenv("SEND_DRIVER") != NULL;
|
||||
const bool env_send_road = getenv("SEND_ROAD") != NULL;
|
||||
const bool env_send_wide_road = getenv("SEND_WIDE_ROAD") != NULL;
|
||||
|
@ -62,6 +59,7 @@ typedef struct LogCameraInfo {
|
|||
bool is_h265;
|
||||
bool downscale;
|
||||
bool has_qcamera;
|
||||
bool trigger_rotate;
|
||||
} LogCameraInfo;
|
||||
|
||||
typedef struct FrameMetadata {
|
||||
|
@ -134,7 +132,7 @@ typedef void (*process_thread_cb)(MultiCameraState *s, CameraState *c, int cnt);
|
|||
|
||||
void fill_frame_data(cereal::FrameData::Builder &framed, const FrameMetadata &frame_data);
|
||||
kj::Array<uint8_t> get_frame_image(const CameraBuf *b);
|
||||
float set_exposure_target(const CameraBuf *b, int x_start, int x_end, int x_skip, int y_start, int y_end, int y_skip, int analog_gain, bool hist_ceil, bool hl_weighted);
|
||||
float set_exposure_target(const CameraBuf *b, int x_start, int x_end, int x_skip, int y_start, int y_end, int y_skip);
|
||||
std::thread start_process_thread(MultiCameraState *cameras, CameraState *cs, process_thread_cb callback);
|
||||
void common_process_driver_camera(SubMaster *sm, PubMaster *pm, CameraState *c, int cnt);
|
||||
|
||||
|
|
|
@ -1113,7 +1113,7 @@ void process_road_camera(MultiCameraState *s, CameraState *c, int cnt) {
|
|||
if (cnt % 3 == 0) {
|
||||
const int x = 290, y = 322, width = 560, height = 314;
|
||||
const int skip = 1;
|
||||
camera_autoexposure(c, set_exposure_target(b, x, x + width, skip, y, y + height, skip, -1, false, false));
|
||||
camera_autoexposure(c, set_exposure_target(b, x, x + width, skip, y, y + height, skip));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue