Agis Zisimatos
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62e9a7579b
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Add SERDES bank and connect supply voltaged to GND
* Add a fpga-power sheet
* Add auto updated kicad files
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-08 11:28:44 +03:00 |
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Agis Zisimatos
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791fa839b6
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Remove unused test points
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2022-04-07 17:52:45 +00:00 |
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Ilias Daradimos
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d9640c0ea0
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Add RBF/Kill ports
Add can footprint
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-04-06 23:27:16 +03:00 |
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Agis Zisimatos
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5754075d13
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Add changes of auto updated KiCad files
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-06 18:50:03 +03:00 |
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Ilias Daradimos
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80eade29ba
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Change battery footprint
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-04-05 16:00:20 +03:00 |
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Agis Zisimatos
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be0d0789f9
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Add FPGA_INIT to MCU, fixes #13
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-05 11:27:50 +03:00 |
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Papadeas Pierros
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929c19d30a
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Fix PWR flag
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
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2022-03-30 16:37:00 +03:00 |
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Agis Zisimatos
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f524588635
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Fix footprints that changed by previous commit
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-03-30 11:38:37 +03:00 |
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Agis Zisimatos
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95c29a28e7
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Add current limit resistor value
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-03-29 19:05:22 +03:00 |
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Papadeas Pierros
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8fbf9d13b1
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Assign footprints for power and mcu.
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
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2022-03-29 16:55:13 +03:00 |
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Ilias Daradimos
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055c01d8fa
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Move GND power flag to top sheet
Update symbols
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-03-22 13:23:56 +02:00 |
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Ilias Daradimos
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b8ad60e557
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Reanotate sheets
Update symbol and port direction
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-03-22 12:29:50 +02:00 |
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Papadeas Pierros
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046229765a
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Add interfaces between modules (closes #1)
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
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2022-03-16 20:03:26 +02:00 |