Agis Zisimatos
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be0d0789f9
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Add FPGA_INIT to MCU, fixes #13
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-05 11:27:50 +03:00 |
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Agis Zisimatos
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c3122ab59c
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Add oscillator in FPGA
Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-05 11:06:18 +03:00 |
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Agis Zisimatos
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fb9e050bc9
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Add test points for GPIOs
Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-05 11:06:18 +03:00 |
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Agis Zisimatos
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8b5c631826
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Add MSPI as default boot mode and NOR flash
Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-05 11:06:18 +03:00 |
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Agis Zisimatos
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0e86bb6f49
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Add LED indicators for DONE and INITN
Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-05 11:06:18 +03:00 |
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Agis Zisimatos
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84e1cc8608
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Implement FPGA JTAG
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-05 11:01:35 +03:00 |
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Agis Zisimatos
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e749327cc2
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Place I/Q and SPI of FPGA
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-05 11:01:35 +03:00 |
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Agis Zisimatos
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fef6cc6ec3
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Add pull-down resistor in load switch ON pin
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-03-29 19:48:29 +03:00 |
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Agis Zisimatos
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95c29a28e7
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Add current limit resistor value
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-03-29 19:05:22 +03:00 |
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Agis Zisimatos
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74dad42969
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Fixes in FPGA power schematic
- Add ferrite bead part number
- Fixes ERC error in PG of 1.1V pin
- Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/16
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-03-29 18:20:43 +03:00 |
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Ilias Daradimos
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055c01d8fa
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Move GND power flag to top sheet
Update symbols
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-03-22 13:23:56 +02:00 |
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Ilias Daradimos
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b8ad60e557
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Reanotate sheets
Update symbol and port direction
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-03-22 12:29:50 +02:00 |
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Agis Zisimatos
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9d3e6155ef
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Add PSU for FPGA
Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-03-22 11:19:58 +02:00 |
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Papadeas Pierros
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046229765a
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Add interfaces between modules (closes #1)
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
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2022-03-16 20:03:26 +02:00 |